ARM: versatile: Drop CLCD platform data
The Versatile family no longer makes any use of the CLCD platform data, we have moved over all users to the DRM driver that has built-in handling of the displays. Delete the old auxdata. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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@ -29,8 +29,6 @@
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#include <linux/of_platform.h>
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#include <linux/of_platform.h>
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#include <linux/slab.h>
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#include <linux/slab.h>
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#include <linux/amba/bus.h>
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#include <linux/amba/bus.h>
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#include <linux/amba/clcd.h>
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#include <linux/platform_data/video-clcd-versatile.h>
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#include <linux/amba/mmci.h>
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#include <linux/amba/mmci.h>
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#include <asm/mach-types.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/arch.h>
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@ -47,14 +45,12 @@
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*/
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*/
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#define VERSATILE_SYS_PCICTL_OFFSET 0x44
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#define VERSATILE_SYS_PCICTL_OFFSET 0x44
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#define VERSATILE_SYS_MCI_OFFSET 0x48
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#define VERSATILE_SYS_MCI_OFFSET 0x48
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#define VERSATILE_SYS_CLCD_OFFSET 0x50
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/*
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/*
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* VERSATILE peripheral addresses
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* VERSATILE peripheral addresses
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*/
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*/
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#define VERSATILE_MMCI0_BASE 0x10005000 /* MMC interface */
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#define VERSATILE_MMCI0_BASE 0x10005000 /* MMC interface */
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#define VERSATILE_MMCI1_BASE 0x1000B000 /* MMC Interface */
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#define VERSATILE_MMCI1_BASE 0x1000B000 /* MMC Interface */
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#define VERSATILE_CLCD_BASE 0x10120000 /* CLCD */
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#define VERSATILE_SCTL_BASE 0x101E0000 /* System controller */
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#define VERSATILE_SCTL_BASE 0x101E0000 /* System controller */
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#define VERSATILE_IB2_BASE 0x24000000 /* IB2 module */
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#define VERSATILE_IB2_BASE 0x24000000 /* IB2 module */
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#define VERSATILE_IB2_CTL_BASE (VERSATILE_IB2_BASE + 0x03000000)
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#define VERSATILE_IB2_CTL_BASE (VERSATILE_IB2_BASE + 0x03000000)
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@ -96,158 +92,6 @@ static struct mmci_platform_data mmc1_plat_data = {
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.status = mmc_status,
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.status = mmc_status,
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};
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};
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/*
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* CLCD support.
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*/
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#define SYS_CLCD_MODE_MASK (3 << 0)
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#define SYS_CLCD_MODE_888 (0 << 0)
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#define SYS_CLCD_MODE_5551 (1 << 0)
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#define SYS_CLCD_MODE_565_RLSB (2 << 0)
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#define SYS_CLCD_MODE_565_BLSB (3 << 0)
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#define SYS_CLCD_NLCDIOON (1 << 2)
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#define SYS_CLCD_VDDPOSSWITCH (1 << 3)
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#define SYS_CLCD_PWR3V5SWITCH (1 << 4)
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#define SYS_CLCD_ID_MASK (0x1f << 8)
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#define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
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#define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
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#define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
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#define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
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#define SYS_CLCD_ID_VGA (0x1f << 8)
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static bool is_sanyo_2_5_lcd;
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/*
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* Disable all display connectors on the interface module.
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*/
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static void versatile_clcd_disable(struct clcd_fb *fb)
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{
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void __iomem *sys_clcd = versatile_sys_base + VERSATILE_SYS_CLCD_OFFSET;
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u32 val;
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val = readl(sys_clcd);
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val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
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writel(val, sys_clcd);
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/*
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* If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off
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*/
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if (of_machine_is_compatible("arm,versatile-ab") && is_sanyo_2_5_lcd) {
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unsigned long ctrl;
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ctrl = readl(versatile_ib2_ctrl);
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ctrl &= ~0x01;
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writel(ctrl, versatile_ib2_ctrl);
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}
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}
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/*
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* Enable the relevant connector on the interface module.
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*/
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static void versatile_clcd_enable(struct clcd_fb *fb)
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{
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struct fb_var_screeninfo *var = &fb->fb.var;
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void __iomem *sys_clcd = versatile_sys_base + VERSATILE_SYS_CLCD_OFFSET;
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u32 val;
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val = readl(sys_clcd);
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val &= ~SYS_CLCD_MODE_MASK;
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switch (var->green.length) {
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case 5:
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val |= SYS_CLCD_MODE_5551;
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break;
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case 6:
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if (var->red.offset == 0)
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val |= SYS_CLCD_MODE_565_RLSB;
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else
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val |= SYS_CLCD_MODE_565_BLSB;
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break;
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case 8:
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val |= SYS_CLCD_MODE_888;
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break;
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}
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/*
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* Set the MUX
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*/
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writel(val, sys_clcd);
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/*
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* And now enable the PSUs
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*/
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val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
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writel(val, sys_clcd);
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/*
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* If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on
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*/
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if (of_machine_is_compatible("arm,versatile-ab") && is_sanyo_2_5_lcd) {
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unsigned long ctrl;
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ctrl = readl(versatile_ib2_ctrl);
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ctrl |= 0x01;
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writel(ctrl, versatile_ib2_ctrl);
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}
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}
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/*
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* Detect which LCD panel is connected, and return the appropriate
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* clcd_panel structure. Note: we do not have any information on
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* the required timings for the 8.4in panel, so we presently assume
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* VGA timings.
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*/
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static int versatile_clcd_setup(struct clcd_fb *fb)
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{
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void __iomem *sys_clcd = versatile_sys_base + VERSATILE_SYS_CLCD_OFFSET;
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const char *panel_name;
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u32 val;
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is_sanyo_2_5_lcd = false;
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val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
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if (val == SYS_CLCD_ID_SANYO_3_8)
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panel_name = "Sanyo TM38QV67A02A";
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else if (val == SYS_CLCD_ID_SANYO_2_5) {
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panel_name = "Sanyo QVGA Portrait";
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is_sanyo_2_5_lcd = true;
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} else if (val == SYS_CLCD_ID_EPSON_2_2)
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panel_name = "Epson L2F50113T00";
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else if (val == SYS_CLCD_ID_VGA)
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panel_name = "VGA";
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else {
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printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
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val);
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panel_name = "VGA";
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}
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fb->panel = versatile_clcd_get_panel(panel_name);
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if (!fb->panel)
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return -EINVAL;
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return versatile_clcd_setup_dma(fb, SZ_1M);
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}
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static void versatile_clcd_decode(struct clcd_fb *fb, struct clcd_regs *regs)
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{
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clcdfb_decode(fb, regs);
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/* Always clear BGR for RGB565: we do the routing externally */
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if (fb->fb.var.green.length == 6)
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regs->cntl &= ~CNTL_BGR;
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}
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static struct clcd_board clcd_plat_data = {
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.name = "Versatile",
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.caps = CLCD_CAP_5551 | CLCD_CAP_565 | CLCD_CAP_888,
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.check = clcdfb_check,
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.decode = versatile_clcd_decode,
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.disable = versatile_clcd_disable,
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.enable = versatile_clcd_enable,
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.setup = versatile_clcd_setup,
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.mmap = versatile_clcd_mmap_dma,
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.remove = versatile_clcd_remove_dma,
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};
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/*
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/*
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* Lookup table for attaching a specific name and platform_data pointer to
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* Lookup table for attaching a specific name and platform_data pointer to
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* devices as they get created by of_platform_populate(). Ideally this table
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* devices as they get created by of_platform_populate(). Ideally this table
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@ -257,7 +101,6 @@ static struct clcd_board clcd_plat_data = {
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struct of_dev_auxdata versatile_auxdata_lookup[] __initdata = {
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struct of_dev_auxdata versatile_auxdata_lookup[] __initdata = {
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OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI0_BASE, "fpga:05", &mmc0_plat_data),
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OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI0_BASE, "fpga:05", &mmc0_plat_data),
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OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI1_BASE, "fpga:0b", &mmc1_plat_data),
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OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI1_BASE, "fpga:0b", &mmc1_plat_data),
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OF_DEV_AUXDATA("arm,primecell", VERSATILE_CLCD_BASE, "dev:20", &clcd_plat_data),
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{}
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{}
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};
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};
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@ -1,28 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef PLAT_CLCD_H
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#define PLAT_CLCD_H
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#ifdef CONFIG_PLAT_VERSATILE_CLCD
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struct clcd_panel *versatile_clcd_get_panel(const char *);
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int versatile_clcd_setup_dma(struct clcd_fb *, unsigned long);
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int versatile_clcd_mmap_dma(struct clcd_fb *, struct vm_area_struct *);
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void versatile_clcd_remove_dma(struct clcd_fb *);
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#else
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static inline struct clcd_panel *versatile_clcd_get_panel(const char *s)
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{
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return NULL;
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}
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static inline int versatile_clcd_setup_dma(struct clcd_fb *fb, unsigned long framesize)
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{
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return -ENODEV;
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}
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static inline int versatile_clcd_mmap_dma(struct clcd_fb *fb, struct vm_area_struct *vm)
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{
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return -ENODEV;
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}
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static inline void versatile_clcd_remove_dma(struct clcd_fb *fb)
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{
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}
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#endif
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#endif
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