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firewire: ohci: speed up PHY register accesses

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Most PHY chips, when idle, can complete a register access in the time
needed for two or three PCI read transactions; bigger delays occur only
when data is currently being moved over the link/PHY interface.  So if
we busy-wait a few times when waiting for the register access to finish,
it is likely that we can finish without having to sleep.

Signed-off-by: Clemens Ladisch <clemens@ladisch.de>
This commit is contained in:
Clemens Ladisch 2010-06-10 08:22:07 +02:00
parent f9c70f9129
commit 153e397920
1 changed files with 10 additions and 4 deletions
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14
drivers/firewire/ohci.c
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@ -474,12 +474,17 @@ static int read_phy_reg(struct fw_ohci *ohci, int addr)
int i; int i;
reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr)); reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
for (i = 0; i < 10; i++) { for (i = 0; i < 3 + 100; i++) {
val = reg_read(ohci, OHCI1394_PhyControl); val = reg_read(ohci, OHCI1394_PhyControl);
if (val & OHCI1394_PhyControl_ReadDone) if (val & OHCI1394_PhyControl_ReadDone)
return OHCI1394_PhyControl_ReadData(val); return OHCI1394_PhyControl_ReadData(val);
msleep(1); /*
* Try a few times without waiting. Sleeping is necessary
* only when the link/PHY interface is busy.
*/
if (i >= 3)
msleep(1);
} }
fw_error("failed to read phy reg\n"); fw_error("failed to read phy reg\n");
@ -492,12 +497,13 @@ static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
reg_write(ohci, OHCI1394_PhyControl, reg_write(ohci, OHCI1394_PhyControl,
OHCI1394_PhyControl_Write(addr, val)); OHCI1394_PhyControl_Write(addr, val));
for (i = 0; i < 100; i++) { for (i = 0; i < 3 + 100; i++) {
val = reg_read(ohci, OHCI1394_PhyControl); val = reg_read(ohci, OHCI1394_PhyControl);
if (!(val & OHCI1394_PhyControl_WritePending)) if (!(val & OHCI1394_PhyControl_WritePending))
return 0; return 0;
msleep(1); if (i >= 3)
msleep(1);
} }
fw_error("failed to write phy reg\n"); fw_error("failed to write phy reg\n");