arm64: dts: meson: fix PHY deassert timing requirements
[ Upstream commit c183c406c4321002fe85b345b51bc1a3a04b6d33 ] According to the datasheet (Rev. 1.9) the RTL8211F requires at least 72ms "for internal circuits settling time" before accessing the PHY registers. This fixes an issue seen on ODROID-C2 where the Ethernet link doesn't come up when using ip link set down/up: [ 6630.714855] meson8b-dwmac c9410000.ethernet eth0: Link is Down [ 6630.785775] meson8b-dwmac c9410000.ethernet eth0: PHY [stmmac-0:00] driver [RTL8211F Gigabit Ethernet] (irq=36) [ 6630.893071] meson8b-dwmac c9410000.ethernet: Failed to reset the dma [ 6630.893800] meson8b-dwmac c9410000.ethernet eth0: stmmac_hw_setup: DMA engine initialization failed [ 6630.902835] meson8b-dwmac c9410000.ethernet eth0: stmmac_open: Hw setup failed Fixes: f29cabf240ed ("arm64: dts: meson: use the generic Ethernet PHY reset GPIO bindings") Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/4a322c198b86e4c8b3dda015560a683babea4d63.1607363522.git.stefan@agner.ch Signed-off-by: Sasha Levin <sashal@kernel.org>
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@ -165,7 +165,7 @@
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reg = <0>;
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reset-assert-us = <10000>;
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reset-deassert-us = <30000>;
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reset-deassert-us = <80000>;
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reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
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interrupt-parent = <&gpio_intc>;
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@ -138,7 +138,7 @@
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reg = <0>;
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reset-assert-us = <10000>;
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reset-deassert-us = <30000>;
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reset-deassert-us = <80000>;
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reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
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interrupt-parent = <&gpio_intc>;
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@ -126,7 +126,7 @@
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reg = <0>;
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reset-assert-us = <10000>;
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reset-deassert-us = <30000>;
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reset-deassert-us = <80000>;
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reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
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interrupt-parent = <&gpio_intc>;
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@ -147,7 +147,7 @@
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reg = <0>;
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reset-assert-us = <10000>;
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reset-deassert-us = <30000>;
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reset-deassert-us = <80000>;
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reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
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};
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};
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@ -82,7 +82,7 @@
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/* External PHY reset is shared with internal PHY Led signal */
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reset-assert-us = <10000>;
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reset-deassert-us = <30000>;
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reset-deassert-us = <80000>;
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reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
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interrupt-parent = <&gpio_intc>;
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@ -251,7 +251,7 @@
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reg = <0>;
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reset-assert-us = <10000>;
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reset-deassert-us = <30000>;
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reset-deassert-us = <80000>;
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reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
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interrupt-parent = <&gpio_intc>;
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@ -112,7 +112,7 @@
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max-speed = <1000>;
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reset-assert-us = <10000>;
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reset-deassert-us = <30000>;
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reset-deassert-us = <80000>;
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reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
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};
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};
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@ -64,7 +64,7 @@
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/* External PHY reset is shared with internal PHY Led signal */
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reset-assert-us = <10000>;
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reset-deassert-us = <30000>;
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reset-deassert-us = <80000>;
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reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
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interrupt-parent = <&gpio_intc>;
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@ -114,7 +114,7 @@
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max-speed = <1000>;
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reset-assert-us = <10000>;
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reset-deassert-us = <30000>;
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reset-deassert-us = <80000>;
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reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
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};
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};
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