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tty: serial: fsl_lpuart: fix the potential risk of division or modulo by zero

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[ Upstream commit fcb10ee27fb91b25b68d7745db9817ecea9f1038 ]

We should be very careful about the register values that will be used
for division or modulo operations, althrough the possibility that the
UARTBAUD register value is zero is very low, but we had better to deal
with the "bad data" of hardware in advance to avoid division or modulo
by zero leading to undefined kernel behavior.

Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
Link: https://lore.kernel.org/r/20210427021226.27468-1-sherry.sun@nxp.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Sherry Sun 2021-04-27 10:12:26 +08:00 committed by Greg Kroah-Hartman
parent 74f26d6fb5
commit 154dee4027
1 changed files with 3 additions and 0 deletions
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3
drivers/tty/serial/fsl_lpuart.c
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@ -1766,6 +1766,9 @@ lpuart32_console_get_options(struct lpuart_port *sport, int *baud,
bd = lpuart32_read(sport->port.membase + UARTBAUD);
bd &= UARTBAUD_SBR_MASK;
if (!bd)
return;
sbr = bd;
uartclk = clk_get_rate(sport->clk);
/*