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drm/i915/mtl: PERF_LIMIT_REASONS changes for MTL

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PERF_LIMIT_REASONS register for MTL media gt is different now.

v2: Avoid static inline for intel_gt_perf_limit_reasons_reg() (Jani)

Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Badal Nilawar <badal.nilawar@intel.com>
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220910143844.1755324-3-ashutosh.dixit@intel.com
This commit is contained in:
Ashutosh Dixit 2022-09-10 07:38:43 -07:00 committed by Rodrigo Vivi
parent fe5979665f
commit 1551b9164f
5 changed files with 13 additions and 5 deletions
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6
drivers/gpu/drm/i915/gt/intel_gt.c
View File

@ -230,6 +230,12 @@ static void gen6_clear_engine_error_register(struct intel_engine_cs *engine)
GEN6_RING_FAULT_REG_POSTING_READ(engine);
}
i915_reg_t intel_gt_perf_limit_reasons_reg(struct intel_gt *gt)
{
return gt->type == GT_MEDIA ?
MTL_MEDIA_PERF_LIMIT_REASONS : GT0_PERF_LIMIT_REASONS;
}
void
intel_gt_clear_error_registers(struct intel_gt *gt,
intel_engine_mask_t engine_mask)

1
drivers/gpu/drm/i915/gt/intel_gt.h
View File

@ -60,6 +60,7 @@ void intel_gt_driver_late_release_all(struct drm_i915_private *i915);
int intel_gt_wait_for_idle(struct intel_gt *gt, long timeout);
void intel_gt_check_and_clear_faults(struct intel_gt *gt);
i915_reg_t intel_gt_perf_limit_reasons_reg(struct intel_gt *gt);
void intel_gt_clear_error_registers(struct intel_gt *gt,
intel_engine_mask_t engine_mask);

4
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
View File

@ -661,7 +661,7 @@ static int perf_limit_reasons_get(void *data, u64 *val)
intel_wakeref_t wakeref;
with_intel_runtime_pm(gt->uncore->rpm, wakeref)
*val = intel_uncore_read(gt->uncore, GT0_PERF_LIMIT_REASONS);
*val = intel_uncore_read(gt->uncore, intel_gt_perf_limit_reasons_reg(gt));
return 0;
}
@ -677,7 +677,7 @@ static int perf_limit_reasons_clear(void *data, u64 val)
* "status" bits except that the "log" bits remain set until cleared.
*/
with_intel_runtime_pm(gt->uncore->rpm, wakeref)
intel_uncore_rmw(gt->uncore, GT0_PERF_LIMIT_REASONS,
intel_uncore_rmw(gt->uncore, intel_gt_perf_limit_reasons_reg(gt),
GT0_PERF_LIMIT_REASONS_LOG_MASK, 0);
return 0;

6
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
View File

@ -510,7 +510,7 @@ struct intel_gt_bool_throttle_attr {
struct attribute attr;
ssize_t (*show)(struct device *dev, struct device_attribute *attr,
char *buf);
i915_reg_t reg32;
i915_reg_t (*reg32)(struct intel_gt *gt);
u32 mask;
};
@ -521,7 +521,7 @@ static ssize_t throttle_reason_bool_show(struct device *dev,
struct intel_gt *gt = intel_gt_sysfs_get_drvdata(dev, attr->attr.name);
struct intel_gt_bool_throttle_attr *t_attr =
(struct intel_gt_bool_throttle_attr *) attr;
bool val = rps_read_mask_mmio(&gt->rps, t_attr->reg32, t_attr->mask);
bool val = rps_read_mask_mmio(&gt->rps, t_attr->reg32(gt), t_attr->mask);
return sysfs_emit(buff, "%u\n", val);
}
@ -530,7 +530,7 @@ static ssize_t throttle_reason_bool_show(struct device *dev,
struct intel_gt_bool_throttle_attr attr_##sysfs_func__ = { \
.attr = { .name = __stringify(sysfs_func__), .mode = 0444 }, \
.show = throttle_reason_bool_show, \
.reg32 = GT0_PERF_LIMIT_REASONS, \
.reg32 = intel_gt_perf_limit_reasons_reg, \
.mask = mask__, \
}

1
drivers/gpu/drm/i915/i915_reg.h
View File

@ -1867,6 +1867,7 @@
#define POWER_LIMIT_1_MASK REG_BIT(10)
#define POWER_LIMIT_2_MASK REG_BIT(11)
#define GT0_PERF_LIMIT_REASONS_LOG_MASK REG_GENMASK(31, 16)
#define MTL_MEDIA_PERF_LIMIT_REASONS _MMIO(0x138030)
#define CHV_CLK_CTL1 _MMIO(0x101100)
#define VLV_CLK_CTL2 _MMIO(0x101104)