clk: renesas: rzg2l: Add FOUTPOSTDIV clk support
PLL5 generates FOUTPOSTDIV clk and is sourced by LCDC/DSI modules. The FOUTPOSTDIV is connected to PLL5_4 MUX. Video clock is sourced from DSI divider which is connected to PLL5_4 MUX. This patch adds support for generating FOUTPOSTDIV clk. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220430114156.6260-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Biju Das
Geert Uytterhoeven
parent
0ab55cf183
commit
1561380ee7
@ -27,6 +27,7 @@
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#include <linux/pm_domain.h>
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#include <linux/reset-controller.h>
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#include <linux/slab.h>
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#include <linux/units.h>
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#include <dt-bindings/clock/renesas-cpg-mssr.h>
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@ -64,6 +65,21 @@ struct sd_hw_data {
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#define to_sd_hw_data(_hw) container_of(_hw, struct sd_hw_data, hw)
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struct rzg2l_pll5_param {
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u32 pl5_fracin;
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u8 pl5_refdiv;
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u8 pl5_intin;
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u8 pl5_postdiv1;
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u8 pl5_postdiv2;
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u8 pl5_spread;
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};
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struct rzg2l_pll5_mux_dsi_div_param {
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u8 clksrc;
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u8 dsi_div_a;
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u8 dsi_div_b;
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};
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/**
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* struct rzg2l_cpg_priv - Clock Pulse Generator Private Data
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*
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@ -77,6 +93,7 @@ struct sd_hw_data {
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* @num_resets: Number of Module Resets in info->resets[]
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* @last_dt_core_clk: ID of the last Core Clock exported to DT
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* @info: Pointer to platform data
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* @pll5_mux_dsi_div_params: pll5 mux and dsi div parameters
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*/
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struct rzg2l_cpg_priv {
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struct reset_controller_dev rcdev;
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@ -91,6 +108,8 @@ struct rzg2l_cpg_priv {
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unsigned int last_dt_core_clk;
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const struct rzg2l_cpg_info *info;
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struct rzg2l_pll5_mux_dsi_div_param mux_dsi_div_params;
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};
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static void rzg2l_cpg_del_clk_provider(void *data)
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@ -264,6 +283,196 @@ rzg2l_cpg_sd_mux_clk_register(const struct cpg_core_clk *core,
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return clk_hw->clk;
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}
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static unsigned long
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rzg2l_cpg_get_foutpostdiv_rate(struct rzg2l_pll5_param *params,
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unsigned long rate)
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{
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unsigned long foutpostdiv_rate;
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params->pl5_intin = rate / MEGA;
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params->pl5_fracin = div_u64(((u64)rate % MEGA) << 24, MEGA);
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params->pl5_refdiv = 2;
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params->pl5_postdiv1 = 1;
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params->pl5_postdiv2 = 1;
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params->pl5_spread = 0x16;
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foutpostdiv_rate =
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EXTAL_FREQ_IN_MEGA_HZ * MEGA / params->pl5_refdiv *
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((((params->pl5_intin << 24) + params->pl5_fracin)) >> 24) /
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(params->pl5_postdiv1 * params->pl5_postdiv2);
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return foutpostdiv_rate;
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}
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struct sipll5 {
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struct clk_hw hw;
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u32 conf;
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unsigned long foutpostdiv_rate;
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struct rzg2l_cpg_priv *priv;
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};
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#define to_sipll5(_hw) container_of(_hw, struct sipll5, hw)
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static unsigned long rzg2l_cpg_get_vclk_rate(struct clk_hw *hw,
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unsigned long rate)
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{
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struct sipll5 *sipll5 = to_sipll5(hw);
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struct rzg2l_cpg_priv *priv = sipll5->priv;
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unsigned long vclk;
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vclk = rate / ((1 << priv->mux_dsi_div_params.dsi_div_a) *
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(priv->mux_dsi_div_params.dsi_div_b + 1));
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if (priv->mux_dsi_div_params.clksrc)
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vclk /= 2;
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return vclk;
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}
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static unsigned long rzg2l_cpg_sipll5_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct sipll5 *sipll5 = to_sipll5(hw);
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unsigned long pll5_rate = sipll5->foutpostdiv_rate;
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if (!pll5_rate)
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pll5_rate = parent_rate;
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return pll5_rate;
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}
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static long rzg2l_cpg_sipll5_round_rate(struct clk_hw *hw,
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unsigned long rate,
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unsigned long *parent_rate)
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{
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return rate;
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}
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static int rzg2l_cpg_sipll5_set_rate(struct clk_hw *hw,
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unsigned long rate,
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unsigned long parent_rate)
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{
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struct sipll5 *sipll5 = to_sipll5(hw);
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struct rzg2l_cpg_priv *priv = sipll5->priv;
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struct rzg2l_pll5_param params;
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unsigned long vclk_rate;
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int ret;
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u32 val;
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/*
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* OSC --> PLL5 --> FOUTPOSTDIV-->|
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* | | -->MUX -->DIV_DSIA_B -->M3 -->VCLK
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* |--FOUT1PH0-->|
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*
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* Based on the dot clock, the DSI divider clock calculates the parent
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* rate and the pll5 parameters for generating FOUTPOSTDIV. It propagates
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* that info to sipll5 which sets parameters for generating FOUTPOSTDIV.
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*
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* OSC --> PLL5 --> FOUTPOSTDIV
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*/
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if (!rate)
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return -EINVAL;
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vclk_rate = rzg2l_cpg_get_vclk_rate(hw, rate);
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sipll5->foutpostdiv_rate =
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rzg2l_cpg_get_foutpostdiv_rate(¶ms, vclk_rate);
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/* Put PLL5 into standby mode */
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writel(CPG_SIPLL5_STBY_RESETB_WEN, priv->base + CPG_SIPLL5_STBY);
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ret = readl_poll_timeout(priv->base + CPG_SIPLL5_MON, val,
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!(val & CPG_SIPLL5_MON_PLL5_LOCK), 100, 250000);
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if (ret) {
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dev_err(priv->dev, "failed to release pll5 lock");
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return ret;
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}
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/* Output clock setting 1 */
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writel(CPG_SIPLL5_CLK1_POSTDIV1_WEN | CPG_SIPLL5_CLK1_POSTDIV2_WEN |
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CPG_SIPLL5_CLK1_REFDIV_WEN | (params.pl5_postdiv1 << 0) |
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(params.pl5_postdiv2 << 4) | (params.pl5_refdiv << 8),
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priv->base + CPG_SIPLL5_CLK1);
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/* Output clock setting, SSCG modulation value setting 3 */
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writel((params.pl5_fracin << 8), priv->base + CPG_SIPLL5_CLK3);
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/* Output clock setting 4 */
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writel(CPG_SIPLL5_CLK4_RESV_LSB | (params.pl5_intin << 16),
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priv->base + CPG_SIPLL5_CLK4);
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/* Output clock setting 5 */
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writel(params.pl5_spread, priv->base + CPG_SIPLL5_CLK5);
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/* PLL normal mode setting */
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writel(CPG_SIPLL5_STBY_DOWNSPREAD_WEN | CPG_SIPLL5_STBY_SSCG_EN_WEN |
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CPG_SIPLL5_STBY_RESETB_WEN | CPG_SIPLL5_STBY_RESETB,
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priv->base + CPG_SIPLL5_STBY);
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/* PLL normal mode transition, output clock stability check */
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ret = readl_poll_timeout(priv->base + CPG_SIPLL5_MON, val,
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(val & CPG_SIPLL5_MON_PLL5_LOCK), 100, 250000);
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if (ret) {
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dev_err(priv->dev, "failed to lock pll5");
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return ret;
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}
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return 0;
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}
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static const struct clk_ops rzg2l_cpg_sipll5_ops = {
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.recalc_rate = rzg2l_cpg_sipll5_recalc_rate,
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.round_rate = rzg2l_cpg_sipll5_round_rate,
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.set_rate = rzg2l_cpg_sipll5_set_rate,
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};
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static struct clk * __init
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rzg2l_cpg_sipll5_register(const struct cpg_core_clk *core,
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struct clk **clks,
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struct rzg2l_cpg_priv *priv)
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{
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const struct clk *parent;
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struct clk_init_data init;
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const char *parent_name;
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struct sipll5 *sipll5;
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struct clk_hw *clk_hw;
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int ret;
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parent = clks[core->parent & 0xffff];
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if (IS_ERR(parent))
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return ERR_CAST(parent);
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sipll5 = devm_kzalloc(priv->dev, sizeof(*sipll5), GFP_KERNEL);
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if (!sipll5)
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return ERR_PTR(-ENOMEM);
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init.name = core->name;
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parent_name = __clk_get_name(parent);
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init.ops = &rzg2l_cpg_sipll5_ops;
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init.flags = 0;
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init.parent_names = &parent_name;
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init.num_parents = 1;
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sipll5->hw.init = &init;
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sipll5->conf = core->conf;
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sipll5->priv = priv;
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writel(CPG_SIPLL5_STBY_SSCG_EN_WEN | CPG_SIPLL5_STBY_RESETB_WEN |
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CPG_SIPLL5_STBY_RESETB, priv->base + CPG_SIPLL5_STBY);
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clk_hw = &sipll5->hw;
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clk_hw->init = &init;
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ret = devm_clk_hw_register(priv->dev, clk_hw);
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if (ret)
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return ERR_PTR(ret);
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priv->mux_dsi_div_params.clksrc = 1; /* Use clk src 1 for DSI */
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priv->mux_dsi_div_params.dsi_div_a = 1; /* Divided by 2 */
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priv->mux_dsi_div_params.dsi_div_b = 2; /* Divided by 3 */
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return clk_hw->clk;
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}
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struct pll_clk {
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struct clk_hw hw;
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unsigned int conf;
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@ -418,6 +627,9 @@ rzg2l_cpg_register_core_clk(const struct cpg_core_clk *core,
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clk = rzg2l_cpg_pll_clk_register(core, priv->clks,
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priv->base, priv);
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break;
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case CLK_TYPE_SIPLL5:
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clk = rzg2l_cpg_sipll5_register(core, priv->clks, priv);
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break;
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case CLK_TYPE_DIV:
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clk = rzg2l_cpg_div_clk_register(core, priv->clks,
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priv->base, priv);
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@ -9,6 +9,12 @@
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#ifndef __RENESAS_RZG2L_CPG_H__
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#define __RENESAS_RZG2L_CPG_H__
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#define CPG_SIPLL5_STBY (0x140)
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#define CPG_SIPLL5_CLK1 (0x144)
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#define CPG_SIPLL5_CLK3 (0x14C)
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#define CPG_SIPLL5_CLK4 (0x150)
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#define CPG_SIPLL5_CLK5 (0x154)
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#define CPG_SIPLL5_MON (0x15C)
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#define CPG_PL1_DDIV (0x200)
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#define CPG_PL2_DDIV (0x204)
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#define CPG_PL3A_DDIV (0x208)
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@ -19,6 +25,16 @@
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#define CPG_PL6_SSEL (0x414)
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#define CPG_PL6_ETH_SSEL (0x418)
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#define CPG_SIPLL5_STBY_RESETB BIT(0)
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#define CPG_SIPLL5_STBY_RESETB_WEN BIT(16)
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#define CPG_SIPLL5_STBY_SSCG_EN_WEN BIT(18)
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#define CPG_SIPLL5_STBY_DOWNSPREAD_WEN BIT(20)
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#define CPG_SIPLL5_CLK1_POSTDIV1_WEN BIT(16)
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#define CPG_SIPLL5_CLK1_POSTDIV2_WEN BIT(20)
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#define CPG_SIPLL5_CLK1_REFDIV_WEN BIT(24)
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#define CPG_SIPLL5_CLK4_RESV_LSB (0xFF)
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#define CPG_SIPLL5_MON_PLL5_LOCK BIT(4)
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#define CPG_CLKSTATUS_SELSDHI0_STS BIT(28)
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#define CPG_CLKSTATUS_SELSDHI1_STS BIT(29)
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@ -49,6 +65,8 @@
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#define SEL_SDHI0 DDIV_PACK(CPG_PL2SDHI_DSEL, 0, 2)
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#define SEL_SDHI1 DDIV_PACK(CPG_PL2SDHI_DSEL, 4, 2)
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#define EXTAL_FREQ_IN_MEGA_HZ (24)
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/**
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* Definitions of CPG Core Clocks
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*
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@ -86,6 +104,9 @@ enum clk_types {
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/* Clock with SD clock source selector */
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CLK_TYPE_SD_MUX,
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/* Clock for SIPLL5 */
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CLK_TYPE_SIPLL5,
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};
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#define DEF_TYPE(_name, _id, _type...) \
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@ -109,6 +130,8 @@ enum clk_types {
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#define DEF_SD_MUX(_name, _id, _conf, _parent_names, _num_parents) \
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DEF_TYPE(_name, _id, CLK_TYPE_SD_MUX, .conf = _conf, \
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.parent_names = _parent_names, .num_parents = _num_parents)
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#define DEF_PLL5_FOUTPOSTDIV(_name, _id, _parent) \
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DEF_TYPE(_name, _id, CLK_TYPE_SIPLL5, .parent = _parent)
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/**
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* struct rzg2l_mod_clk - Module Clocks definitions
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