drm/amdgpu: add RAS error info support for gfx_v9_4_3
add RAS error info support for gfx_v9_4_3. Signed-off-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -3766,6 +3766,12 @@ static void gfx_v9_4_3_inst_query_ras_err_count(struct amdgpu_device *adev,
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unsigned long ce_count = 0, ue_count = 0;
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uint32_t i, j, k;
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/* NOTE: convert xcc_id to physical XCD ID (XCD0 or XCD1) */
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struct amdgpu_smuio_mcm_config_info mcm_info = {
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.socket_id = adev->smuio.funcs->get_socket_id(adev),
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.die_id = xcc_id & 0x01 ? 1 : 0,
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};
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mutex_lock(&adev->grbm_idx_mutex);
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for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) {
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@ -3804,8 +3810,8 @@ static void gfx_v9_4_3_inst_query_ras_err_count(struct amdgpu_device *adev,
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/* the caller should make sure initialize value of
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* err_data->ue_count and err_data->ce_count
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*/
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err_data->ce_count += ce_count;
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err_data->ue_count += ue_count;
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amdgpu_ras_error_statistic_ue_count(err_data, &mcm_info, ue_count);
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amdgpu_ras_error_statistic_ce_count(err_data, &mcm_info, ce_count);
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}
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static void gfx_v9_4_3_inst_reset_ras_err_count(struct amdgpu_device *adev,
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