From 713759291c9ff2f8191cfb6600b87c49832b4c8f Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 2 Jul 2013 09:11:39 -0400 Subject: [PATCH 1/7] drm/radeon/dpm: clarify debugfs warning For chips without debugfs dpm support say that it's not implemented rather than not supported to avoid confusion about DPM support in general. Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/radeon_pm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c index 075f2fa56897..ebbdb477745a 100644 --- a/drivers/gpu/drm/radeon/radeon_pm.c +++ b/drivers/gpu/drm/radeon/radeon_pm.c @@ -1399,7 +1399,7 @@ static int radeon_debugfs_pm_info(struct seq_file *m, void *data) if (rdev->asic->dpm.debugfs_print_current_performance_level) radeon_dpm_debugfs_print_current_performance_level(rdev, m); else - seq_printf(m, "Unsupported\n"); + seq_printf(m, "Debugfs support not implemented for this asic\n"); mutex_unlock(&rdev->pm.mutex); } else { seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk); From bf0936e196ec21b604106578043d4c14831f99e7 Mon Sep 17 00:00:00 2001 From: Mike Lothian Date: Tue, 2 Jul 2013 17:38:11 -0400 Subject: [PATCH 2/7] drm/radeon/dpm: fix compilation with certain versions of gcc Add #include to *_dpm.c files Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/ni_dpm.c | 1 + drivers/gpu/drm/radeon/rv6xx_dpm.c | 1 + drivers/gpu/drm/radeon/rv770_dpm.c | 1 + drivers/gpu/drm/radeon/si_dpm.c | 1 + drivers/gpu/drm/radeon/sumo_dpm.c | 1 + drivers/gpu/drm/radeon/trinity_dpm.c | 1 + 6 files changed, 6 insertions(+) diff --git a/drivers/gpu/drm/radeon/ni_dpm.c b/drivers/gpu/drm/radeon/ni_dpm.c index 8497ca6bb0b1..a4cb99c2da85 100644 --- a/drivers/gpu/drm/radeon/ni_dpm.c +++ b/drivers/gpu/drm/radeon/ni_dpm.c @@ -28,6 +28,7 @@ #include "ni_dpm.h" #include "atom.h" #include +#include #define MC_CG_ARB_FREQ_F0 0x0a #define MC_CG_ARB_FREQ_F1 0x0b diff --git a/drivers/gpu/drm/radeon/rv6xx_dpm.c b/drivers/gpu/drm/radeon/rv6xx_dpm.c index 33705c5c8369..8303de267ee5 100644 --- a/drivers/gpu/drm/radeon/rv6xx_dpm.c +++ b/drivers/gpu/drm/radeon/rv6xx_dpm.c @@ -28,6 +28,7 @@ #include "r600_dpm.h" #include "rv6xx_dpm.h" #include "atom.h" +#include static u32 rv6xx_scale_count_given_unit(struct radeon_device *rdev, u32 unscaled_count, u32 unit); diff --git a/drivers/gpu/drm/radeon/rv770_dpm.c b/drivers/gpu/drm/radeon/rv770_dpm.c index 2436b5c7e66e..9af464d48eaa 100644 --- a/drivers/gpu/drm/radeon/rv770_dpm.c +++ b/drivers/gpu/drm/radeon/rv770_dpm.c @@ -29,6 +29,7 @@ #include "rv770_dpm.h" #include "cypress_dpm.h" #include "atom.h" +#include #define MC_CG_ARB_FREQ_F0 0x0a #define MC_CG_ARB_FREQ_F1 0x0b diff --git a/drivers/gpu/drm/radeon/si_dpm.c b/drivers/gpu/drm/radeon/si_dpm.c index 46e9fc56cee7..a7e97cd05e96 100644 --- a/drivers/gpu/drm/radeon/si_dpm.c +++ b/drivers/gpu/drm/radeon/si_dpm.c @@ -28,6 +28,7 @@ #include "si_dpm.h" #include "atom.h" #include +#include #define MC_CG_ARB_FREQ_F0 0x0a #define MC_CG_ARB_FREQ_F1 0x0b diff --git a/drivers/gpu/drm/radeon/sumo_dpm.c b/drivers/gpu/drm/radeon/sumo_dpm.c index 68fefb916582..bf187a5b3d58 100644 --- a/drivers/gpu/drm/radeon/sumo_dpm.c +++ b/drivers/gpu/drm/radeon/sumo_dpm.c @@ -27,6 +27,7 @@ #include "r600_dpm.h" #include "cypress_dpm.h" #include "sumo_dpm.h" +#include #define SUMO_MAX_DEEPSLEEP_DIVIDER_ID 5 #define SUMO_MINIMUM_ENGINE_CLOCK 800 diff --git a/drivers/gpu/drm/radeon/trinity_dpm.c b/drivers/gpu/drm/radeon/trinity_dpm.c index 502d9153c4d5..b02b5ad92121 100644 --- a/drivers/gpu/drm/radeon/trinity_dpm.c +++ b/drivers/gpu/drm/radeon/trinity_dpm.c @@ -26,6 +26,7 @@ #include "trinityd.h" #include "r600_dpm.h" #include "trinity_dpm.h" +#include #define TRINITY_MAX_DEEPSLEEP_DIVIDER_ID 5 #define TRINITY_MINIMUM_ENGINE_CLOCK 800 From e631227f698f39969eb476d297f3ac65b43b51a5 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 3 Jul 2013 11:18:08 -0400 Subject: [PATCH 3/7] drm/radeon: fix endian bug in radeon_atom_get_mclk_range_table() Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/radeon_atombios.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c index 70d8687e60e0..b1777d10d0b5 100644 --- a/drivers/gpu/drm/radeon/radeon_atombios.c +++ b/drivers/gpu/drm/radeon/radeon_atombios.c @@ -3639,7 +3639,7 @@ int radeon_atom_get_mclk_range_table(struct radeon_device *rdev, p = (u8 *)vram_module->asMemTiming; for (i = 0; i < mclk_range_table->num_entries; i++) { format = (ATOM_MEMORY_TIMING_FORMAT *)p; - mclk_range_table->mclk[i] = format->ulClkRange; + mclk_range_table->mclk[i] = le32_to_cpu(format->ulClkRange); p += mem_timing_size; } } else From 0124853eb1eda5e193e4753bd5d5ac77085027b2 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 3 Jul 2013 12:02:10 -0400 Subject: [PATCH 4/7] drm/radeon/aruba: disable additional rlc features They cause problems with dynamic clocking. Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/evergreen.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index 0de5b74f0287..2e1de4fd2975 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c @@ -4043,8 +4043,6 @@ static void evergreen_rlc_start(struct radeon_device *rdev) if (rdev->flags & RADEON_IS_IGP) { mask |= GFX_POWER_GATING_ENABLE | GFX_POWER_GATING_SRC; - if (rdev->family == CHIP_ARUBA) - mask |= DYN_PER_SIMD_PG_ENABLE | LB_CNT_SPIM_ACTIVE | LOAD_BALANCE_ENABLE; } WREG32(RLC_CNTL, mask); From 2b90eddcd7091dd631ead1d79e28e79ad589bb8d Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 3 Jul 2013 15:07:28 -0400 Subject: [PATCH 5/7] drm/radeon/sumo: disable PG when changing UVD clocks Causes hangs for some people. Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/sumo_dpm.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/radeon/sumo_dpm.c b/drivers/gpu/drm/radeon/sumo_dpm.c index bf187a5b3d58..b13448f13ee8 100644 --- a/drivers/gpu/drm/radeon/sumo_dpm.c +++ b/drivers/gpu/drm/radeon/sumo_dpm.c @@ -811,6 +811,23 @@ static void sumo_program_bootup_state(struct radeon_device *rdev) sumo_power_level_enable(rdev, i, false); } +static void sumo_setup_uvd_clocks(struct radeon_device *rdev, + struct radeon_ps *new_rps, + struct radeon_ps *old_rps) +{ + struct sumo_power_info *pi = sumo_get_pi(rdev); + + if (pi->enable_gfx_power_gating) { + sumo_gfx_powergating_enable(rdev, false); + } + + radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); + + if (pi->enable_gfx_power_gating) { + sumo_gfx_powergating_enable(rdev, true); + } +} + static void sumo_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev, struct radeon_ps *new_rps, struct radeon_ps *old_rps) @@ -826,7 +843,7 @@ static void sumo_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev, current_ps->levels[current_ps->num_levels - 1].sclk) return; - radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); + sumo_setup_uvd_clocks(rdev, new_rps, old_rps); } static void sumo_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev, @@ -844,7 +861,7 @@ static void sumo_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev, current_ps->levels[current_ps->num_levels - 1].sclk) return; - radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); + sumo_setup_uvd_clocks(rdev, new_rps, old_rps); } void sumo_take_smu_control(struct radeon_device *rdev, bool enable) From 62fa44bf7b75e3e482655baa15309bf3ea122bd3 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 3 Jul 2013 15:01:45 -0400 Subject: [PATCH 6/7] drm/radeon/tn: disable PG when changing UVD clocks Causes hangs for some people. Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/trinity_dpm.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/radeon/trinity_dpm.c b/drivers/gpu/drm/radeon/trinity_dpm.c index b02b5ad92121..8a32bcc6bbb5 100644 --- a/drivers/gpu/drm/radeon/trinity_dpm.c +++ b/drivers/gpu/drm/radeon/trinity_dpm.c @@ -921,6 +921,10 @@ static void trinity_setup_uvd_clocks(struct radeon_device *rdev, { struct trinity_power_info *pi = trinity_get_pi(rdev); + if (pi->enable_gfx_power_gating) { + trinity_gfx_powergating_enable(rdev, false); + } + if (pi->uvd_dpm) { if (trinity_uvd_clocks_zero(new_rps) && !trinity_uvd_clocks_zero(old_rps)) { @@ -946,6 +950,10 @@ static void trinity_setup_uvd_clocks(struct radeon_device *rdev, radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); } + + if (pi->enable_gfx_power_gating) { + trinity_gfx_powergating_enable(rdev, true); + } } static void trinity_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev, From 338a95a95508537e23c82d59a2d87be6fde4b6ff Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 3 Jul 2013 15:14:25 -0400 Subject: [PATCH 7/7] drm/radeon/sumo: implement support for disable_gfx_power_gating_in_uvd flag Some asic revisions need to disable PG when UVD is active. Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/sumo_dpm.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/radeon/sumo_dpm.c b/drivers/gpu/drm/radeon/sumo_dpm.c index b13448f13ee8..dc599060a9a4 100644 --- a/drivers/gpu/drm/radeon/sumo_dpm.c +++ b/drivers/gpu/drm/radeon/sumo_dpm.c @@ -824,7 +824,9 @@ static void sumo_setup_uvd_clocks(struct radeon_device *rdev, radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); if (pi->enable_gfx_power_gating) { - sumo_gfx_powergating_enable(rdev, true); + if (!pi->disable_gfx_power_gating_in_uvd || + !r600_is_uvd_state(new_rps->class, new_rps->class2)) + sumo_gfx_powergating_enable(rdev, true); } }