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ASoC: SOF: Intel: HDaudio cleanups

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Merge series from Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>:

This is the part1 of my HDaudio cleanups, before the addition of
to-be-announced HDaudio extensions.

The patchset includes more consistent use of read/write/update
helpers, removal of useless waits, structure members and programming
sequences, removal of confusing sharing of private_data between FE and
BE.

Additional patches are coming to split the controller, codec and
multi-link management functionality in well-identified files.

Pierre-Louis Bossart (16):
  ASoC: SOF: ops: fallback to mmio in helpers
  ASoC: SOF: Intel: use mmio fallback for all platforms
  ASoC: SOF: ops: add readb/writeb helpers
  ASoC: SOF: ops: add snd_sof_dsp_updateb() helper
  ASoC: SOF: Intel: hda-dsp: use SOF helpers for consistency
  ASoC: SOF: Intel: hda-dai: start removing the use of
    runtime->private_data in BE
  ASoC: SOF: Intel: hda-dai: use component_get_drvdata to find hdac_bus
  ASoC: SOF: Intel: hda-dai: remove useless members in hda_pipe_params
  ASoC: SOF: Intel: hda-ctrl: remove useless sleep
  ASoC: SOF: Intel: hda: always do a full reset
  ASoC: SOF: Intel: hda: remove useless check on GCTL
  ASoC: SOF: Intel: hda-stream: use SOF helpers for consistency
  ASoC: SOF: Intel: hda-stream: rename CL_SD_CTL registers as SD_CTL
  ASoC: SOF: Intel: hda: use SOF helper for consistency
  ASoC: SOF: Intel: hda-stream: use snd_sof_dsp_updateb() helper
  ASoC: SOF: Intel: hda-stream: use readb/writeb for stream registers

 sound/soc/sof/intel/bdw.c            |  6 +---
 sound/soc/sof/intel/byt.c            | 12 ++-----
 sound/soc/sof/intel/hda-common-ops.c |  6 +---
 sound/soc/sof/intel/hda-ctrl.c       | 41 ++++++++--------------
 sound/soc/sof/intel/hda-dai.c        | 31 +++++++----------
 sound/soc/sof/intel/hda-dsp.c        | 12 ++++---
 sound/soc/sof/intel/hda-loader-skl.c | 30 ++++++++--------
 sound/soc/sof/intel/hda-loader.c     |  4 +--
 sound/soc/sof/intel/hda-stream.c     | 47 ++++++++++++-------------
 sound/soc/sof/intel/hda.c            |  5 ++-
 sound/soc/sof/intel/hda.h            | 25 +++++++-------
 sound/soc/sof/intel/pci-tng.c        |  6 +---
 sound/soc/sof/ops.h                  | 51 ++++++++++++++++++++--------
 sound/soc/sof/sof-priv.h             |  4 +++
 14 files changed, 136 insertions(+), 144 deletions(-)

--
2.34.1
This commit is contained in:
Mark Brown 2022-10-26 19:53:14 +01:00
commit 1675068469
No known key found for this signature in database
GPG Key ID: 24D68B725D5487D0
14 changed files with 138 additions and 146 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
sound/soc/sof/intel/bdw.c
View File

@ -575,11 +575,7 @@ static struct snd_sof_dsp_ops sof_bdw_ops = {
.run = bdw_run,
.reset = bdw_reset,
/* Register IO */
.write = sof_io_write,
.read = sof_io_read,
.write64 = sof_io_write64,
.read64 = sof_io_read64,
/* Register IO uses direct mmio */
/* Block IO */
.block_read = sof_block_read,

12
sound/soc/sof/intel/byt.c
View File

@ -225,11 +225,7 @@ static struct snd_sof_dsp_ops sof_byt_ops = {
.run = atom_run,
.reset = atom_reset,
/* Register IO */
.write = sof_io_write,
.read = sof_io_read,
.write64 = sof_io_write64,
.read64 = sof_io_read64,
/* Register IO uses direct mmio */
/* Block IO */
.block_read = sof_block_read,
@ -304,11 +300,7 @@ static struct snd_sof_dsp_ops sof_cht_ops = {
.run = atom_run,
.reset = atom_reset,
/* Register IO */
.write = sof_io_write,
.read = sof_io_read,
.write64 = sof_io_write64,
.read64 = sof_io_read64,
/* Register IO uses direct mmio */
/* Block IO */
.block_read = sof_block_read,

6
sound/soc/sof/intel/hda-common-ops.c
View File

@ -19,11 +19,7 @@ struct snd_sof_dsp_ops sof_hda_common_ops = {
.probe = hda_dsp_probe,
.remove = hda_dsp_remove,
/* Register IO */
.write = sof_io_write,
.read = sof_io_read,
.write64 = sof_io_write64,
.read64 = sof_io_read64,
/* Register IO uses direct mmio */
/* Block IO */
.block_read = sof_block_read,

45
sound/soc/sof/intel/hda-ctrl.c
View File

@ -182,7 +182,7 @@ int hda_dsp_ctrl_clock_power_gating(struct snd_sof_dev *sdev, bool enable)
return 0;
}
int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev, bool full_reset)
int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev)
{
struct hdac_bus *bus = sof_to_bus(sdev);
#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
@ -199,34 +199,21 @@ int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev, bool full_reset)
#endif
hda_dsp_ctrl_misc_clock_gating(sdev, false);
if (full_reset) {
/* reset HDA controller */
ret = hda_dsp_ctrl_link_reset(sdev, true);
if (ret < 0) {
dev_err(sdev->dev, "error: failed to reset HDA controller\n");
goto err;
}
usleep_range(500, 1000);
/* exit HDA controller reset */
ret = hda_dsp_ctrl_link_reset(sdev, false);
if (ret < 0) {
dev_err(sdev->dev, "error: failed to exit HDA controller reset\n");
goto err;
}
usleep_range(1000, 1200);
}
#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
/* check to see if controller is ready */
if (!snd_hdac_chip_readb(bus, GCTL)) {
dev_dbg(bus->dev, "controller not ready!\n");
ret = -EBUSY;
/* reset HDA controller */
ret = hda_dsp_ctrl_link_reset(sdev, true);
if (ret < 0) {
dev_err(sdev->dev, "error: failed to reset HDA controller\n");
goto err;
}
/* exit HDA controller reset */
ret = hda_dsp_ctrl_link_reset(sdev, false);
if (ret < 0) {
dev_err(sdev->dev, "error: failed to exit HDA controller reset\n");
goto err;
}
#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
/* Accept unsolicited responses */
snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_UNSOL, AZX_GCTL_UNSOL);
@ -247,7 +234,7 @@ int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev, bool full_reset)
list_for_each_entry(stream, &bus->stream_list, list) {
sd_offset = SOF_STREAM_SD_OFFSET(stream);
snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
sd_offset + SOF_HDA_ADSP_REG_CL_SD_STS,
sd_offset + SOF_HDA_ADSP_REG_SD_STS,
SOF_HDA_CL_DMA_SD_INT_MASK);
}
@ -313,7 +300,7 @@ void hda_dsp_ctrl_stop_chip(struct snd_sof_dev *sdev)
sd_offset = SOF_STREAM_SD_OFFSET(stream);
snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
sd_offset +
SOF_HDA_ADSP_REG_CL_SD_CTL,
SOF_HDA_ADSP_REG_SD_CTL,
SOF_HDA_CL_DMA_SD_INT_MASK,
0);
}
@ -331,7 +318,7 @@ void hda_dsp_ctrl_stop_chip(struct snd_sof_dev *sdev)
list_for_each_entry(stream, &bus->stream_list, list) {
sd_offset = SOF_STREAM_SD_OFFSET(stream);
snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
sd_offset + SOF_HDA_ADSP_REG_CL_SD_STS,
sd_offset + SOF_HDA_ADSP_REG_SD_STS,
SOF_HDA_CL_DMA_SD_INT_MASK);
}

31
sound/soc/sof/intel/hda-dai.c
View File

@ -32,11 +32,8 @@ MODULE_PARM_DESC(sof_use_tplg_nhlt, "SOF topology nhlt override");
struct hda_pipe_params {
u32 ch;
u32 s_freq;
u32 s_fmt;
u8 linktype;
snd_pcm_format_t format;
int link_index;
int stream;
unsigned int link_bps;
};
@ -138,12 +135,12 @@ hda_link_stream_assign(struct hdac_bus *bus,
}
static int hda_link_dma_cleanup(struct snd_pcm_substream *substream,
struct hdac_stream *hstream,
struct hdac_ext_stream *hext_stream,
struct snd_soc_dai *cpu_dai,
struct snd_soc_dai *codec_dai,
bool trigger_suspend_stop)
{
struct hdac_ext_stream *hext_stream = snd_soc_dai_get_dma_data(cpu_dai, substream);
struct hdac_stream *hstream = &hext_stream->hstream;
struct hdac_bus *bus = hstream->bus;
struct sof_intel_hda_stream *hda_stream;
struct hdac_ext_link *hlink;
@ -207,14 +204,17 @@ static int hda_link_dma_params(struct hdac_ext_stream *hext_stream,
static int hda_link_dma_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct hdac_stream *hstream = substream->runtime->private_data;
struct hdac_ext_stream *hext_stream;
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
struct hda_pipe_params p_params = {0};
struct hdac_bus *bus = hstream->bus;
struct hdac_ext_stream *hext_stream;
struct hdac_ext_link *hlink;
struct snd_sof_dev *sdev;
struct hdac_bus *bus;
sdev = snd_soc_component_get_drvdata(cpu_dai->component);
bus = sof_to_bus(sdev);
hext_stream = snd_soc_dai_get_dma_data(cpu_dai, substream);
if (!hext_stream) {
@ -232,10 +232,8 @@ static int hda_link_dma_hw_params(struct snd_pcm_substream *substream,
/* set the hdac_stream in the codec dai */
snd_soc_dai_set_stream(codec_dai, hdac_stream(hext_stream), substream->stream);
p_params.s_fmt = snd_pcm_format_width(params_format(params));
p_params.ch = params_channels(params);
p_params.s_freq = params_rate(params);
p_params.stream = substream->stream;
p_params.link_index = hlink->index;
p_params.format = params_format(params);
@ -257,7 +255,6 @@ static int hda_link_dma_prepare(struct snd_pcm_substream *substream)
static int hda_link_dma_trigger(struct snd_pcm_substream *substream, int cmd)
{
struct hdac_stream *hstream = substream->runtime->private_data;
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
@ -274,7 +271,7 @@ static int hda_link_dma_trigger(struct snd_pcm_substream *substream, int cmd)
break;
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_STOP:
ret = hda_link_dma_cleanup(substream, hstream, cpu_dai, codec_dai, true);
ret = hda_link_dma_cleanup(substream, hext_stream, cpu_dai, codec_dai, true);
if (ret < 0)
return ret;
@ -291,7 +288,6 @@ static int hda_link_dma_trigger(struct snd_pcm_substream *substream, int cmd)
static int hda_link_dma_hw_free(struct snd_pcm_substream *substream)
{
struct hdac_stream *hstream = substream->runtime->private_data;
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
@ -301,7 +297,7 @@ static int hda_link_dma_hw_free(struct snd_pcm_substream *substream)
if (!hext_stream)
return 0;
return hda_link_dma_cleanup(substream, hstream, cpu_dai, codec_dai, false);
return hda_link_dma_cleanup(substream, hext_stream, cpu_dai, codec_dai, false);
}
static int hda_dai_widget_update(struct snd_soc_dapm_widget *w,
@ -458,14 +454,12 @@ static int ipc4_hda_dai_trigger(struct snd_pcm_substream *substream,
struct snd_sof_widget *swidget;
struct snd_soc_dapm_widget *w;
struct snd_soc_dai *codec_dai;
struct hdac_stream *hstream;
struct snd_soc_dai *cpu_dai;
int ret;
dev_dbg(dai->dev, "cmd=%d dai %s direction %d\n", cmd,
dai->name, substream->stream);
hstream = substream->runtime->private_data;
rtd = asoc_substream_to_rtd(substream);
cpu_dai = asoc_rtd_to_cpu(rtd, 0);
codec_dai = asoc_rtd_to_codec(rtd, 0);
@ -500,7 +494,7 @@ static int ipc4_hda_dai_trigger(struct snd_pcm_substream *substream,
pipeline->state = SOF_IPC4_PIPE_RESET;
ret = hda_link_dma_cleanup(substream, hstream, cpu_dai, codec_dai, false);
ret = hda_link_dma_cleanup(substream, hext_stream, cpu_dai, codec_dai, false);
if (ret < 0) {
dev_err(sdev->dev, "%s: failed to clean up link DMA\n", __func__);
return ret;
@ -575,7 +569,8 @@ static int hda_dai_suspend(struct hdac_bus *bus)
cpu_dai = asoc_rtd_to_cpu(rtd, 0);
codec_dai = asoc_rtd_to_codec(rtd, 0);
ret = hda_link_dma_cleanup(hext_stream->link_substream, s,
ret = hda_link_dma_cleanup(hext_stream->link_substream,
hext_stream,
cpu_dai, codec_dai, false);
if (ret < 0)
return ret;

12
sound/soc/sof/intel/hda-dsp.c
View File

@ -347,10 +347,9 @@ void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev)
static int hda_dsp_wait_d0i3c_done(struct snd_sof_dev *sdev)
{
struct hdac_bus *bus = sof_to_bus(sdev);
int retry = HDA_DSP_REG_POLL_RETRY_COUNT;
while (snd_hdac_chip_readb(bus, VS_D0I3C) & SOF_HDA_VS_D0I3C_CIP) {
while (snd_sof_dsp_readb(sdev, HDA_DSP_HDA_BAR, SOF_HDA_VS_D0I3C) & SOF_HDA_VS_D0I3C_CIP) {
if (!retry--)
return -ETIMEDOUT;
usleep_range(10, 15);
@ -380,6 +379,7 @@ static int hda_dsp_update_d0i3c_register(struct snd_sof_dev *sdev, u8 value)
{
struct hdac_bus *bus = sof_to_bus(sdev);
int ret;
u8 reg;
/* Write to D0I3C after Command-In-Progress bit is cleared */
ret = hda_dsp_wait_d0i3c_done(sdev);
@ -389,7 +389,8 @@ static int hda_dsp_update_d0i3c_register(struct snd_sof_dev *sdev, u8 value)
}
/* Update D0I3C register */
snd_hdac_chip_updateb(bus, VS_D0I3C, SOF_HDA_VS_D0I3C_I3, value);
snd_sof_dsp_updateb(sdev, HDA_DSP_HDA_BAR,
SOF_HDA_VS_D0I3C, SOF_HDA_VS_D0I3C_I3, value);
/* Wait for cmd in progress to be cleared before exiting the function */
ret = hda_dsp_wait_d0i3c_done(sdev);
@ -398,7 +399,8 @@ static int hda_dsp_update_d0i3c_register(struct snd_sof_dev *sdev, u8 value)
return ret;
}
trace_sof_intel_D0I3C_updated(sdev, snd_hdac_chip_readb(bus, VS_D0I3C));
reg = snd_sof_dsp_readb(sdev, HDA_DSP_HDA_BAR, SOF_HDA_VS_D0I3C);
trace_sof_intel_D0I3C_updated(sdev, reg);
return 0;
}
@ -689,7 +691,7 @@ static int hda_resume(struct snd_sof_dev *sdev, bool runtime_resume)
snd_sof_pci_update_bits(sdev, PCI_TCSEL, 0x07, 0);
/* reset and start hda controller */
ret = hda_dsp_ctrl_init_chip(sdev, true);
ret = hda_dsp_ctrl_init_chip(sdev);
if (ret < 0) {
dev_err(sdev->dev,
"error: failed to start controller after resume\n");

30
sound/soc/sof/intel/hda-loader-skl.c
View File

@ -141,7 +141,7 @@ static void cl_skl_cldma_stream_run(struct snd_sof_dev *sdev, bool enable)
u32 run = enable ? 0x1 : 0;
snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
sd_offset + SOF_HDA_ADSP_REG_CL_SD_CTL,
sd_offset + SOF_HDA_ADSP_REG_SD_CTL,
HDA_CL_SD_CTL_RUN(1), HDA_CL_SD_CTL_RUN(run));
retries = 300;
@ -150,7 +150,7 @@ static void cl_skl_cldma_stream_run(struct snd_sof_dev *sdev, bool enable)
/* waiting for hardware to report the stream Run bit set */
val = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
sd_offset + SOF_HDA_ADSP_REG_CL_SD_CTL);
sd_offset + SOF_HDA_ADSP_REG_SD_CTL);
val &= HDA_CL_SD_CTL_RUN(1);
if (enable && val)
break;
@ -174,23 +174,23 @@ static void cl_skl_cldma_stream_clear(struct snd_sof_dev *sdev)
* Descriptor Error Interrupt and set the cldma stream number to 0.
*/
snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
sd_offset + SOF_HDA_ADSP_REG_CL_SD_CTL,
sd_offset + SOF_HDA_ADSP_REG_SD_CTL,
HDA_CL_SD_CTL_INT_MASK, HDA_CL_SD_CTL_INT(0));
snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
sd_offset + SOF_HDA_ADSP_REG_CL_SD_CTL,
sd_offset + SOF_HDA_ADSP_REG_SD_CTL,
HDA_CL_SD_CTL_STRM(0xf), HDA_CL_SD_CTL_STRM(0));
snd_sof_dsp_write(sdev, HDA_DSP_BAR,
sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPL, HDA_CL_SD_BDLPLBA(0));
sd_offset + SOF_HDA_ADSP_REG_SD_BDLPL, HDA_CL_SD_BDLPLBA(0));
snd_sof_dsp_write(sdev, HDA_DSP_BAR,
sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPU, 0);
sd_offset + SOF_HDA_ADSP_REG_SD_BDLPU, 0);
/* Set the Cyclic Buffer Length to 0. */
snd_sof_dsp_write(sdev, HDA_DSP_BAR,
sd_offset + SOF_HDA_ADSP_REG_CL_SD_CBL, 0);
sd_offset + SOF_HDA_ADSP_REG_SD_CBL, 0);
/* Set the Last Valid Index. */
snd_sof_dsp_write(sdev, HDA_DSP_BAR,
sd_offset + SOF_HDA_ADSP_REG_CL_SD_LVI, 0);
sd_offset + SOF_HDA_ADSP_REG_SD_LVI, 0);
}
static void cl_skl_cldma_setup_spb(struct snd_sof_dev *sdev,
@ -240,27 +240,27 @@ static void cl_skl_cldma_setup_controller(struct snd_sof_dev *sdev,
/* setting the stream register */
snd_sof_dsp_write(sdev, HDA_DSP_BAR,
sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPL,
sd_offset + SOF_HDA_ADSP_REG_SD_BDLPL,
HDA_CL_SD_BDLPLBA(dmab_bdl->addr));
snd_sof_dsp_write(sdev, HDA_DSP_BAR,
sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPU,
sd_offset + SOF_HDA_ADSP_REG_SD_BDLPU,
HDA_CL_SD_BDLPUBA(dmab_bdl->addr));
/* Set the Cyclic Buffer Length. */
snd_sof_dsp_write(sdev, HDA_DSP_BAR,
sd_offset + SOF_HDA_ADSP_REG_CL_SD_CBL, max_size);
sd_offset + SOF_HDA_ADSP_REG_SD_CBL, max_size);
/* Set the Last Valid Index. */
snd_sof_dsp_write(sdev, HDA_DSP_BAR,
sd_offset + SOF_HDA_ADSP_REG_CL_SD_LVI, count - 1);
sd_offset + SOF_HDA_ADSP_REG_SD_LVI, count - 1);
/* Set the Interrupt On Completion, FIFO Error Interrupt,
* Descriptor Error Interrupt and the cldma stream number.
*/
snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
sd_offset + SOF_HDA_ADSP_REG_CL_SD_CTL,
sd_offset + SOF_HDA_ADSP_REG_SD_CTL,
HDA_CL_SD_CTL_INT_MASK, HDA_CL_SD_CTL_INT(1));
snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
sd_offset + SOF_HDA_ADSP_REG_CL_SD_CTL,
sd_offset + SOF_HDA_ADSP_REG_SD_CTL,
HDA_CL_SD_CTL_STRM(0xf),
HDA_CL_SD_CTL_STRM(1));
}
@ -439,7 +439,7 @@ static int cl_skl_cldma_wait_interruptible(struct snd_sof_dev *sdev,
/* now check DMA interrupt status */
cl_dma_intr_status = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
sd_offset + SOF_HDA_ADSP_REG_CL_SD_STS);
sd_offset + SOF_HDA_ADSP_REG_SD_STS);
if (!(cl_dma_intr_status & HDA_CL_DMA_SD_INT_COMPLETE)) {
dev_err(sdev->dev, "cldma copy failed\n");

4
sound/soc/sof/intel/hda-loader.c
View File

@ -265,9 +265,9 @@ int hda_cl_cleanup(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab,
/* reset BDL address */
snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPL, 0);
sd_offset + SOF_HDA_ADSP_REG_SD_BDLPL, 0);
snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPU, 0);
sd_offset + SOF_HDA_ADSP_REG_SD_BDLPU, 0);
snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, sd_offset, 0);
snd_dma_free_pages(dmab);

47
sound/soc/sof/intel/hda-stream.c
View File

@ -367,7 +367,7 @@ int hda_dsp_stream_trigger(struct snd_sof_dev *sdev,
if (ret >= 0) {
snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
sd_offset + SOF_HDA_ADSP_REG_CL_SD_STS,
sd_offset + SOF_HDA_ADSP_REG_SD_STS,
SOF_HDA_CL_DMA_SD_INT_MASK);
hstream->running = false;
@ -398,7 +398,6 @@ int hda_dsp_iccmax_stream_hw_params(struct snd_sof_dev *sdev, struct hdac_ext_st
struct snd_dma_buffer *dmab,
struct snd_pcm_hw_params *params)
{
struct hdac_bus *bus = sof_to_bus(sdev);
struct hdac_stream *hstream = &hext_stream->hstream;
int sd_offset = SOF_STREAM_SD_OFFSET(hstream);
int ret;
@ -419,10 +418,10 @@ int hda_dsp_iccmax_stream_hw_params(struct snd_sof_dev *sdev, struct hdac_ext_st
/* reset BDL address */
snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPL,
sd_offset + SOF_HDA_ADSP_REG_SD_BDLPL,
0x0);
snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPU,
sd_offset + SOF_HDA_ADSP_REG_SD_BDLPU,
0x0);
hstream->frags = 0;
@ -435,20 +434,20 @@ int hda_dsp_iccmax_stream_hw_params(struct snd_sof_dev *sdev, struct hdac_ext_st
/* program BDL address */
snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPL,
sd_offset + SOF_HDA_ADSP_REG_SD_BDLPL,
(u32)hstream->bdl.addr);
snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPU,
sd_offset + SOF_HDA_ADSP_REG_SD_BDLPU,
upper_32_bits(hstream->bdl.addr));
/* program cyclic buffer length */
snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
sd_offset + SOF_HDA_ADSP_REG_CL_SD_CBL,
sd_offset + SOF_HDA_ADSP_REG_SD_CBL,
hstream->bufsize);
/* program last valid index */
snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
sd_offset + SOF_HDA_ADSP_REG_CL_SD_LVI,
sd_offset + SOF_HDA_ADSP_REG_SD_LVI,
0xffff, (hstream->frags - 1));
/* decouple host and link DMA, enable DSP features */
@ -456,7 +455,8 @@ int hda_dsp_iccmax_stream_hw_params(struct snd_sof_dev *sdev, struct hdac_ext_st
mask, mask);
/* Follow HW recommendation to set the guardband value to 95us during FW boot */
snd_hdac_chip_updateb(bus, VS_LTRP, HDA_VS_INTEL_LTRP_GB_MASK, HDA_LTRP_GB_VALUE_US);
snd_sof_dsp_updateb(sdev, HDA_DSP_HDA_BAR, HDA_VS_INTEL_LTRP,
HDA_VS_INTEL_LTRP_GB_MASK, HDA_LTRP_GB_VALUE_US);
/* start DMA */
snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset,
@ -520,7 +520,7 @@ int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev,
}
snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
sd_offset + SOF_HDA_ADSP_REG_CL_SD_STS,
sd_offset + SOF_HDA_ADSP_REG_SD_STS,
SOF_HDA_CL_DMA_SD_INT_MASK,
SOF_HDA_CL_DMA_SD_INT_MASK);
@ -534,10 +534,10 @@ int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev,
/* reset BDL address */
snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPL,
sd_offset + SOF_HDA_ADSP_REG_SD_BDLPL,
0x0);
snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPU,
sd_offset + SOF_HDA_ADSP_REG_SD_BDLPU,
0x0);
/* clear stream status */
@ -562,7 +562,7 @@ int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev,
}
snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
sd_offset + SOF_HDA_ADSP_REG_CL_SD_STS,
sd_offset + SOF_HDA_ADSP_REG_SD_STS,
SOF_HDA_CL_DMA_SD_INT_MASK,
SOF_HDA_CL_DMA_SD_INT_MASK);
@ -582,7 +582,7 @@ int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev,
/* program cyclic buffer length */
snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
sd_offset + SOF_HDA_ADSP_REG_CL_SD_CBL,
sd_offset + SOF_HDA_ADSP_REG_SD_CBL,
hstream->bufsize);
/*
@ -606,7 +606,7 @@ int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev,
/* program stream format */
snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
sd_offset +
SOF_HDA_ADSP_REG_CL_SD_FORMAT,
SOF_HDA_ADSP_REG_SD_FORMAT,
0xffff, hstream->format_val);
if (chip->quirks & SOF_INTEL_PROCEN_FMT_QUIRK) {
@ -617,15 +617,15 @@ int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev,
/* program last valid index */
snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
sd_offset + SOF_HDA_ADSP_REG_CL_SD_LVI,
sd_offset + SOF_HDA_ADSP_REG_SD_LVI,
0xffff, (hstream->frags - 1));
/* program BDL address */
snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPL,
sd_offset + SOF_HDA_ADSP_REG_SD_BDLPL,
(u32)hstream->bdl.addr);
snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPU,
sd_offset + SOF_HDA_ADSP_REG_SD_BDLPU,
upper_32_bits(hstream->bdl.addr));
/* enable position buffer, if needed */
@ -649,7 +649,7 @@ int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev,
hstream->fifo_size =
snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR,
sd_offset +
SOF_HDA_ADSP_REG_CL_SD_FIFOSIZE);
SOF_HDA_ADSP_REG_SD_FIFOSIZE);
hstream->fifo_size &= 0xffff;
hstream->fifo_size += 1;
} else {
@ -697,7 +697,8 @@ bool hda_dsp_check_stream_irq(struct snd_sof_dev *sdev)
/* The function can be called at irq thread, so use spin_lock_irq */
spin_lock_irq(&bus->reg_lock);
status = snd_hdac_chip_readl(bus, INTSTS);
status = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS);
trace_sof_intel_hda_dsp_check_stream_irq(sdev, status);
/* if Register inaccessible, ignore it.*/
@ -735,11 +736,11 @@ static bool hda_dsp_stream_check(struct hdac_bus *bus, u32 status)
list_for_each_entry(s, &bus->stream_list, list) {
if (status & BIT(s->index) && s->opened) {
sd_status = snd_hdac_stream_readb(s, SD_STS);
sd_status = readb(s->sd_addr + SOF_HDA_ADSP_REG_SD_STS);
trace_sof_intel_hda_dsp_stream_status(bus->dev, s, sd_status);
snd_hdac_stream_writeb(s, SD_STS, sd_status);
writeb(sd_status, s->sd_addr + SOF_HDA_ADSP_REG_SD_STS);
active = true;
if ((!s->substream && !s->cstream) ||
@ -778,7 +779,7 @@ irqreturn_t hda_dsp_stream_threaded_handler(int irq, void *context)
for (i = 0, active = true; i < 10 && active; i++) {
spin_lock_irq(&bus->reg_lock);
status = snd_hdac_chip_readl(bus, INTSTS);
status = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS);
/* check streams */
active = hda_dsp_stream_check(bus, status);

5
sound/soc/sof/intel/hda.c
View File

@ -625,7 +625,6 @@ static bool hda_check_ipc_irq(struct snd_sof_dev *sdev)
void hda_ipc_irq_dump(struct snd_sof_dev *sdev)
{
struct hdac_bus *bus = sof_to_bus(sdev);
u32 adspis;
u32 intsts;
u32 intctl;
@ -637,7 +636,7 @@ void hda_ipc_irq_dump(struct snd_sof_dev *sdev)
intsts = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS);
intctl = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL);
ppsts = snd_sof_dsp_read(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPSTS);
rirbsts = snd_hdac_chip_readb(bus, RIRBSTS);
rirbsts = snd_sof_dsp_readb(sdev, HDA_DSP_HDA_BAR, AZX_REG_RIRBSTS);
dev_err(sdev->dev, "hda irq intsts 0x%8.8x intlctl 0x%8.8x rirb %2.2x\n",
intsts, intctl, rirbsts);
@ -890,7 +889,7 @@ static int hda_init_caps(struct snd_sof_dev *sdev)
dev_dbg(sdev->dev, "PP capability, will probe DSP later.\n");
/* Init HDA controller after i915 init */
ret = hda_dsp_ctrl_init_chip(sdev, true);
ret = hda_dsp_ctrl_init_chip(sdev);
if (ret < 0) {
dev_err(bus->dev, "error: init chip failed with ret: %d\n",
ret);

25
sound/soc/sof/intel/hda.h
View File

@ -122,17 +122,17 @@
#define SOF_HDA_ADSP_DPLBASE_ENABLE 0x01
/* Stream Registers */
#define SOF_HDA_ADSP_REG_CL_SD_CTL 0x00
#define SOF_HDA_ADSP_REG_CL_SD_STS 0x03
#define SOF_HDA_ADSP_REG_CL_SD_LPIB 0x04
#define SOF_HDA_ADSP_REG_CL_SD_CBL 0x08
#define SOF_HDA_ADSP_REG_CL_SD_LVI 0x0C
#define SOF_HDA_ADSP_REG_CL_SD_FIFOW 0x0E
#define SOF_HDA_ADSP_REG_CL_SD_FIFOSIZE 0x10
#define SOF_HDA_ADSP_REG_CL_SD_FORMAT 0x12
#define SOF_HDA_ADSP_REG_CL_SD_FIFOL 0x14
#define SOF_HDA_ADSP_REG_CL_SD_BDLPL 0x18
#define SOF_HDA_ADSP_REG_CL_SD_BDLPU 0x1C
#define SOF_HDA_ADSP_REG_SD_CTL 0x00
#define SOF_HDA_ADSP_REG_SD_STS 0x03
#define SOF_HDA_ADSP_REG_SD_LPIB 0x04
#define SOF_HDA_ADSP_REG_SD_CBL 0x08
#define SOF_HDA_ADSP_REG_SD_LVI 0x0C
#define SOF_HDA_ADSP_REG_SD_FIFOW 0x0E
#define SOF_HDA_ADSP_REG_SD_FIFOSIZE 0x10
#define SOF_HDA_ADSP_REG_SD_FORMAT 0x12
#define SOF_HDA_ADSP_REG_SD_FIFOL 0x14
#define SOF_HDA_ADSP_REG_SD_BDLPL 0x18
#define SOF_HDA_ADSP_REG_SD_BDLPU 0x1C
#define SOF_HDA_ADSP_SD_ENTRY_SIZE 0x20
/* CL: Software Position Based FIFO Capability Registers */
@ -307,6 +307,7 @@
/* Intel Vendor Specific Registers */
#define HDA_VS_INTEL_EM2 0x1030
#define HDA_VS_INTEL_EM2_L1SEN BIT(13)
#define HDA_VS_INTEL_LTRP 0x1048
#define HDA_VS_INTEL_LTRP_GB_MASK 0x3F
/* HIPCI */
@ -702,7 +703,7 @@ void hda_dsp_ctrl_ppcap_int_enable(struct snd_sof_dev *sdev, bool enable);
int hda_dsp_ctrl_link_reset(struct snd_sof_dev *sdev, bool reset);
void hda_dsp_ctrl_misc_clock_gating(struct snd_sof_dev *sdev, bool enable);
int hda_dsp_ctrl_clock_power_gating(struct snd_sof_dev *sdev, bool enable);
int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev, bool full_reset);
int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev);
void hda_dsp_ctrl_stop_chip(struct snd_sof_dev *sdev);
/*
* HDA bus operations.

6
sound/soc/sof/intel/pci-tng.c
View File

@ -144,11 +144,7 @@ struct snd_sof_dsp_ops sof_tng_ops = {
.run = atom_run,
.reset = atom_reset,
/* Register IO */
.write = sof_io_write,
.read = sof_io_read,
.write64 = sof_io_write64,
.read64 = sof_io_read64,
/* Register IO uses direct mmio */
/* Block IO */
.block_read = sof_block_read,

51
sound/soc/sof/ops.h
View File

@ -302,26 +302,40 @@ static inline int snd_sof_debugfs_add_region_item(struct snd_sof_dev *sdev,
}
/* register IO */
static inline void snd_sof_dsp_writeb(struct snd_sof_dev *sdev, u32 bar,
u32 offset, u8 value)
{
if (sof_ops(sdev)->writeb)
sof_ops(sdev)->writeb(sdev, sdev->bar[bar] + offset, value);
else
writeb(value, sdev->bar[bar] + offset);
}
static inline void snd_sof_dsp_write(struct snd_sof_dev *sdev, u32 bar,
u32 offset, u32 value)
{
if (sof_ops(sdev)->write) {
if (sof_ops(sdev)->write)
sof_ops(sdev)->write(sdev, sdev->bar[bar] + offset, value);
return;
}
dev_err_ratelimited(sdev->dev, "error: %s not defined\n", __func__);
else
writel(value, sdev->bar[bar] + offset);
}
static inline void snd_sof_dsp_write64(struct snd_sof_dev *sdev, u32 bar,
u32 offset, u64 value)
{
if (sof_ops(sdev)->write64) {
if (sof_ops(sdev)->write64)
sof_ops(sdev)->write64(sdev, sdev->bar[bar] + offset, value);
return;
}
else
writeq(value, sdev->bar[bar] + offset);
}
dev_err_ratelimited(sdev->dev, "error: %s not defined\n", __func__);
static inline u8 snd_sof_dsp_readb(struct snd_sof_dev *sdev, u32 bar,
u32 offset)
{
if (sof_ops(sdev)->readb)
return sof_ops(sdev)->readb(sdev, sdev->bar[bar] + offset);
else
return readb(sdev->bar[bar] + offset);
}
static inline u32 snd_sof_dsp_read(struct snd_sof_dev *sdev, u32 bar,
@ -329,9 +343,8 @@ static inline u32 snd_sof_dsp_read(struct snd_sof_dev *sdev, u32 bar,
{
if (sof_ops(sdev)->read)
return sof_ops(sdev)->read(sdev, sdev->bar[bar] + offset);
dev_err(sdev->dev, "error: %s not defined\n", __func__);
return -ENOTSUPP;
else
return readl(sdev->bar[bar] + offset);
}
static inline u64 snd_sof_dsp_read64(struct snd_sof_dev *sdev, u32 bar,
@ -339,9 +352,19 @@ static inline u64 snd_sof_dsp_read64(struct snd_sof_dev *sdev, u32 bar,
{
if (sof_ops(sdev)->read64)
return sof_ops(sdev)->read64(sdev, sdev->bar[bar] + offset);
else
return readq(sdev->bar[bar] + offset);
}
dev_err(sdev->dev, "error: %s not defined\n", __func__);
return -ENOTSUPP;
static inline void snd_sof_dsp_updateb(struct snd_sof_dev *sdev, u32 bar,
u32 offset, u8 value, u8 mask)
{
u8 reg;
reg = snd_sof_dsp_readb(sdev, bar, offset);
reg &= ~mask;
reg |= value;
snd_sof_dsp_writeb(sdev, bar, offset, reg);
}
/* block IO */

4
sound/soc/sof/sof-priv.h
View File

@ -171,6 +171,10 @@ struct snd_sof_dsp_ops {
* TODO: consider removing these operations and calling respective
* implementations directly
*/
void (*writeb)(struct snd_sof_dev *sof_dev, void __iomem *addr,
u8 value); /* optional */
u8 (*readb)(struct snd_sof_dev *sof_dev,
void __iomem *addr); /* optional */
void (*write)(struct snd_sof_dev *sof_dev, void __iomem *addr,
u32 value); /* optional */
u32 (*read)(struct snd_sof_dev *sof_dev,