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ASoC: cs42l42: Wait for debounce interval after resume

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Since clock stop causes bus reset on Intel controllers, we need
to wait for the debounce interval on resume, to ensure all the
interrupt status registers are set correctly.

Signed-off-by: Stefan Binding <sbinding@opensource.cirrus.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20230127165111.3010960-9-sbinding@opensource.cirrus.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Stefan Binding 2023-01-27 16:51:11 +00:00 committed by Mark Brown
parent e0bd53a4d1
commit 16838bfbf6
No known key found for this signature in database
GPG Key ID: 24D68B725D5487D0
1 changed files with 9 additions and 1 deletions
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10
sound/soc/codecs/cs42l42-sdw.c
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@ -447,7 +447,9 @@ static int __maybe_unused cs42l42_sdw_handle_unattach(struct cs42l42_private *cs
static int __maybe_unused cs42l42_sdw_runtime_resume(struct device *dev)
{
static const unsigned int ts_dbnce_ms[] = { 0, 125, 250, 500, 750, 1000, 1250, 1500};
struct cs42l42_private *cs42l42 = dev_get_drvdata(dev);
unsigned int dbnce;
int ret;
dev_dbg(dev, "Runtime resume\n");
@ -456,8 +458,14 @@ static int __maybe_unused cs42l42_sdw_runtime_resume(struct device *dev)
return 0;
ret = cs42l42_sdw_handle_unattach(cs42l42);
if (ret < 0)
if (ret < 0) {
return ret;
} else if (ret > 0) {
dbnce = max(cs42l42->ts_dbnc_rise, cs42l42->ts_dbnc_fall);
if (dbnce > 0)
msleep(ts_dbnce_ms[dbnce]);
}
regcache_cache_only(cs42l42->regmap, false);