drm/vc4: Increase the core clock based on HVS load
Depending on a given HVS output (HVS to PixelValves) and input (planes attached to a channel) load, the HVS needs for the core clock to be raised above its boot time default. Failing to do so will result in a vblank timeout and a stalled display pipeline. Signed-off-by: Maxime Ripard <maxime@cerno.tech> Reviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com> Link: https://lore.kernel.org/r/20211025152903.1088803-11-maxime@cerno.tech
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@ -659,12 +659,27 @@ static int vc4_crtc_atomic_check(struct drm_crtc *crtc,
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struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);
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struct drm_connector *conn;
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struct drm_connector_state *conn_state;
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struct drm_encoder *encoder;
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int ret, i;
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ret = vc4_hvs_atomic_check(crtc, state);
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if (ret)
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return ret;
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encoder = vc4_get_crtc_encoder(crtc, crtc_state);
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if (encoder) {
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const struct drm_display_mode *mode = &crtc_state->adjusted_mode;
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struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
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mode = &crtc_state->adjusted_mode;
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if (vc4_encoder->type == VC4_ENCODER_TYPE_HDMI0) {
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vc4_state->hvs_load = max(mode->clock * mode->hdisplay / mode->htotal + 1000,
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mode->clock * 9 / 10) * 1000;
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} else {
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vc4_state->hvs_load = mode->clock * 1000;
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}
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}
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for_each_new_connector_in_state(state, conn, conn_state,
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i) {
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if (conn_state->crtc != crtc)
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@ -532,6 +532,8 @@ struct vc4_crtc_state {
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unsigned int bottom;
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} margins;
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unsigned long hvs_load;
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/* Transitional state below, only valid during atomic commits */
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bool update_muxing;
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};
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@ -39,9 +39,11 @@ static struct vc4_ctm_state *to_vc4_ctm_state(struct drm_private_state *priv)
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struct vc4_hvs_state {
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struct drm_private_state base;
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unsigned long core_clock_rate;
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struct {
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unsigned in_use: 1;
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unsigned long fifo_load;
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struct drm_crtc_commit *pending_commit;
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} fifo_state[HVS_NUM_CHANNELS];
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};
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@ -339,10 +341,19 @@ static void vc4_atomic_commit_tail(struct drm_atomic_state *state)
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struct vc4_hvs *hvs = vc4->hvs;
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struct drm_crtc_state *old_crtc_state;
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struct drm_crtc_state *new_crtc_state;
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struct vc4_hvs_state *new_hvs_state;
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struct drm_crtc *crtc;
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struct vc4_hvs_state *old_hvs_state;
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int i;
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old_hvs_state = vc4_hvs_get_old_global_state(state);
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if (WARN_ON(!old_hvs_state))
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return;
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new_hvs_state = vc4_hvs_get_new_global_state(state);
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if (WARN_ON(!new_hvs_state))
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return;
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for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
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struct vc4_crtc_state *vc4_crtc_state;
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@ -353,12 +364,13 @@ static void vc4_atomic_commit_tail(struct drm_atomic_state *state)
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vc4_hvs_mask_underrun(dev, vc4_crtc_state->assigned_channel);
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}
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if (vc4->hvs->hvs5)
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clk_set_min_rate(hvs->core_clk, 500000000);
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if (vc4->hvs->hvs5) {
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unsigned long core_rate = max_t(unsigned long,
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500000000,
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new_hvs_state->core_clock_rate);
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old_hvs_state = vc4_hvs_get_old_global_state(state);
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if (!old_hvs_state)
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return;
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clk_set_min_rate(hvs->core_clk, core_rate);
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}
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for_each_old_crtc_in_state(state, crtc, old_crtc_state, i) {
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struct vc4_crtc_state *vc4_crtc_state =
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@ -398,8 +410,12 @@ static void vc4_atomic_commit_tail(struct drm_atomic_state *state)
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drm_atomic_helper_cleanup_planes(dev, state);
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if (vc4->hvs->hvs5)
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clk_set_min_rate(hvs->core_clk, 0);
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if (vc4->hvs->hvs5) {
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drm_dbg(dev, "Running the core clock at %lu Hz\n",
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new_hvs_state->core_clock_rate);
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clk_set_min_rate(hvs->core_clk, new_hvs_state->core_clock_rate);
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}
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}
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static int vc4_atomic_commit_setup(struct drm_atomic_state *state)
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@ -656,9 +672,9 @@ vc4_hvs_channels_duplicate_state(struct drm_private_obj *obj)
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__drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);
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for (i = 0; i < HVS_NUM_CHANNELS; i++) {
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state->fifo_state[i].in_use = old_state->fifo_state[i].in_use;
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state->fifo_state[i].fifo_load = old_state->fifo_state[i].fifo_load;
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if (!old_state->fifo_state[i].pending_commit)
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continue;
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@ -667,6 +683,8 @@ vc4_hvs_channels_duplicate_state(struct drm_private_obj *obj)
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drm_crtc_commit_get(old_state->fifo_state[i].pending_commit);
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}
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state->core_clock_rate = old_state->core_clock_rate;
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return &state->base;
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}
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@ -821,6 +839,76 @@ static int vc4_pv_muxing_atomic_check(struct drm_device *dev,
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return 0;
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}
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static int
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vc4_core_clock_atomic_check(struct drm_atomic_state *state)
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{
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struct vc4_dev *vc4 = to_vc4_dev(state->dev);
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struct drm_private_state *priv_state;
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struct vc4_hvs_state *hvs_new_state;
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struct vc4_load_tracker_state *load_state;
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struct drm_crtc_state *old_crtc_state, *new_crtc_state;
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struct drm_crtc *crtc;
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unsigned int num_outputs;
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unsigned long pixel_rate;
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unsigned long cob_rate;
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unsigned int i;
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priv_state = drm_atomic_get_private_obj_state(state,
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&vc4->load_tracker);
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if (IS_ERR(priv_state))
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return PTR_ERR(priv_state);
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load_state = to_vc4_load_tracker_state(priv_state);
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hvs_new_state = vc4_hvs_get_global_state(state);
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if (!hvs_new_state)
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return -EINVAL;
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for_each_oldnew_crtc_in_state(state, crtc,
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old_crtc_state,
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new_crtc_state,
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i) {
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if (old_crtc_state->active) {
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struct vc4_crtc_state *old_vc4_state =
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to_vc4_crtc_state(old_crtc_state);
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unsigned int channel = old_vc4_state->assigned_channel;
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hvs_new_state->fifo_state[channel].fifo_load = 0;
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}
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if (new_crtc_state->active) {
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struct vc4_crtc_state *new_vc4_state =
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to_vc4_crtc_state(new_crtc_state);
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unsigned int channel = new_vc4_state->assigned_channel;
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hvs_new_state->fifo_state[channel].fifo_load =
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new_vc4_state->hvs_load;
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}
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}
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cob_rate = 0;
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num_outputs = 0;
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for (i = 0; i < HVS_NUM_CHANNELS; i++) {
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if (!hvs_new_state->fifo_state[i].in_use)
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continue;
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num_outputs++;
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cob_rate += hvs_new_state->fifo_state[i].fifo_load;
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}
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pixel_rate = load_state->hvs_load;
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if (num_outputs > 1) {
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pixel_rate = (pixel_rate * 40) / 100;
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} else {
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pixel_rate = (pixel_rate * 60) / 100;
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}
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hvs_new_state->core_clock_rate = max(cob_rate, pixel_rate);
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return 0;
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}
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static int
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vc4_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
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{
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@ -838,7 +926,11 @@ vc4_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
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if (ret)
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return ret;
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return vc4_load_tracker_atomic_check(state);
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ret = vc4_load_tracker_atomic_check(state);
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if (ret)
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return ret;
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return vc4_core_clock_atomic_check(state);
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}
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static struct drm_mode_config_helper_funcs vc4_mode_config_helpers = {
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