mlx5: implement ethtool::get_fec_stats
Report corrected bits. v2: catch reg access errors (Saeed) Signed-off-by: Jakub Kicinski <kuba@kernel.org> Acked-by: Saeed Mahameed <saeedm@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -1602,6 +1602,14 @@ static int mlx5e_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
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return mlx5_set_port_wol(mdev, mlx5_wol_mode);
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}
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static void mlx5e_get_fec_stats(struct net_device *netdev,
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struct ethtool_fec_stats *fec_stats)
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{
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struct mlx5e_priv *priv = netdev_priv(netdev);
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mlx5e_stats_fec_get(priv, fec_stats);
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}
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static int mlx5e_get_fecparam(struct net_device *netdev,
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struct ethtool_fecparam *fecparam)
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{
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@ -2209,6 +2217,7 @@ const struct ethtool_ops mlx5e_ethtool_ops = {
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.self_test = mlx5e_self_test,
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.get_msglevel = mlx5e_get_msglevel,
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.set_msglevel = mlx5e_set_msglevel,
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.get_fec_stats = mlx5e_get_fec_stats,
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.get_fecparam = mlx5e_get_fecparam,
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.set_fecparam = mlx5e_set_fecparam,
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};
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@ -768,10 +768,10 @@ static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(802_3)
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mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
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}
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#define MLX5E_READ_CTR64_BE_F(ptr, c) \
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#define MLX5E_READ_CTR64_BE_F(ptr, set, c) \
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be64_to_cpu(*(__be64 *)((char *)ptr + \
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MLX5_BYTE_OFF(ppcnt_reg, \
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counter_set.eth_802_3_cntrs_grp_data_layout.c##_high)))
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counter_set.set.c##_high)))
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void mlx5e_stats_pause_get(struct mlx5e_priv *priv,
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struct ethtool_pause_stats *pause_stats)
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@ -791,9 +791,11 @@ void mlx5e_stats_pause_get(struct mlx5e_priv *priv,
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pause_stats->tx_pause_frames =
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MLX5E_READ_CTR64_BE_F(ppcnt_ieee_802_3,
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eth_802_3_cntrs_grp_data_layout,
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a_pause_mac_ctrl_frames_transmitted);
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pause_stats->rx_pause_frames =
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MLX5E_READ_CTR64_BE_F(ppcnt_ieee_802_3,
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eth_802_3_cntrs_grp_data_layout,
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a_pause_mac_ctrl_frames_received);
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}
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@ -1015,6 +1017,29 @@ static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(phy)
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mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
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}
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void mlx5e_stats_fec_get(struct mlx5e_priv *priv,
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struct ethtool_fec_stats *fec_stats)
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{
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u32 ppcnt_phy_statistical[MLX5_ST_SZ_DW(ppcnt_reg)];
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struct mlx5_core_dev *mdev = priv->mdev;
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u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
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int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
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if (!MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group))
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return;
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MLX5_SET(ppcnt_reg, in, local_port, 1);
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MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
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if (mlx5_core_access_reg(mdev, in, sz, ppcnt_phy_statistical,
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sz, MLX5_REG_PPCNT, 0, 0))
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return;
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fec_stats->corrected_bits.total =
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MLX5E_READ_CTR64_BE_F(ppcnt_phy_statistical,
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phys_layer_statistical_cntrs,
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phy_corrected_bits);
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}
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#define PPORT_ETH_EXT_OFF(c) \
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MLX5_BYTE_OFF(ppcnt_reg, \
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counter_set.eth_extended_cntrs_grp_data_layout.c##_high)
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@ -114,6 +114,8 @@ void mlx5e_stats_update_ndo_stats(struct mlx5e_priv *priv);
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void mlx5e_stats_pause_get(struct mlx5e_priv *priv,
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struct ethtool_pause_stats *pause_stats);
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void mlx5e_stats_fec_get(struct mlx5e_priv *priv,
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struct ethtool_fec_stats *fec_stats);
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/* Concrete NIC Stats */
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