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ARM: dts: r8a7794: Add DU1 clock to device tree

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Add the missing module clock for the second channel of the display unit.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Geert Uytterhoeven 2017-03-28 12:45:30 +02:00 committed by Simon Horman
parent 3932197c01
commit 1764f8081f
2 changed files with 6 additions and 3 deletions
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8
arch/arm/boot/dts/r8a7794.dtsi
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@ -1270,19 +1270,21 @@
clocks = <&mp_clk>, <&hp_clk>, clocks = <&mp_clk>, <&hp_clk>,
<&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
<&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
<&zx_clk>; <&zx_clk>, <&zx_clk>;
#clock-cells = <1>; #clock-cells = <1>;
clock-indices = < clock-indices = <
R8A7794_CLK_EHCI R8A7794_CLK_HSUSB R8A7794_CLK_EHCI R8A7794_CLK_HSUSB
R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5 R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5
R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0 R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0
R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1 R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1
R8A7794_CLK_SCIF0 R8A7794_CLK_DU0 R8A7794_CLK_SCIF0
R8A7794_CLK_DU1 R8A7794_CLK_DU0
>; >;
clock-output-names = clock-output-names =
"ehci", "hsusb", "ehci", "hsusb",
"hscif2", "scif5", "scif4", "hscif1", "hscif0", "hscif2", "scif5", "scif4", "hscif1", "hscif0",
"scif3", "scif2", "scif1", "scif0", "du0"; "scif3", "scif2", "scif1", "scif0",
"du1", "du0";
}; };
mstp8_clks: mstp8_clks@e6150990 { mstp8_clks: mstp8_clks@e6150990 {
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";

1
include/dt-bindings/clock/r8a7794-clock.h
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@ -82,6 +82,7 @@
#define R8A7794_CLK_SCIF2 19 #define R8A7794_CLK_SCIF2 19
#define R8A7794_CLK_SCIF1 20 #define R8A7794_CLK_SCIF1 20
#define R8A7794_CLK_SCIF0 21 #define R8A7794_CLK_SCIF0 21
#define R8A7794_CLK_DU1 23
#define R8A7794_CLK_DU0 24 #define R8A7794_CLK_DU0 24
/* MSTP8 */ /* MSTP8 */