spi: zynq-qspi: switch to use modern name
Change legacy name master/slave to modern name host/target or controller. No functional changed. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://msgid.link/r/20231128093031.3707034-24-yangyingliang@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -54,10 +54,10 @@
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#define ZYNQ_QSPI_CONFIG_MSTREN_MASK BIT(0) /* Master Mode */
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#define ZYNQ_QSPI_CONFIG_MSTREN_MASK BIT(0) /* Master Mode */
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/*
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/*
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* QSPI Configuration Register - Baud rate and slave select
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* QSPI Configuration Register - Baud rate and target select
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*
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*
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* These are the values used in the calculation of baud rate divisor and
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* These are the values used in the calculation of baud rate divisor and
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* setting the slave select.
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* setting the target select.
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*/
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*/
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#define ZYNQ_QSPI_CONFIG_BAUD_DIV_MAX GENMASK(2, 0) /* Baud rate maximum */
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#define ZYNQ_QSPI_CONFIG_BAUD_DIV_MAX GENMASK(2, 0) /* Baud rate maximum */
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#define ZYNQ_QSPI_CONFIG_BAUD_DIV_SHIFT 3 /* Baud rate divisor shift */
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#define ZYNQ_QSPI_CONFIG_BAUD_DIV_SHIFT 3 /* Baud rate divisor shift */
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@ -164,14 +164,14 @@ static inline void zynq_qspi_write(struct zynq_qspi *xqspi, u32 offset,
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*
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*
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* The default settings of the QSPI controller's configurable parameters on
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* The default settings of the QSPI controller's configurable parameters on
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* reset are
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* reset are
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* - Master mode
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* - Host mode
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* - Baud rate divisor is set to 2
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* - Baud rate divisor is set to 2
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* - Tx threshold set to 1l Rx threshold set to 32
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* - Tx threshold set to 1l Rx threshold set to 32
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* - Flash memory interface mode enabled
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* - Flash memory interface mode enabled
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* - Size of the word to be transferred as 8 bit
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* - Size of the word to be transferred as 8 bit
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* This function performs the following actions
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* This function performs the following actions
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* - Disable and clear all the interrupts
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* - Disable and clear all the interrupts
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* - Enable manual slave select
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* - Enable manual target select
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* - Enable manual start
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* - Enable manual start
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* - Deselect all the chip select lines
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* - Deselect all the chip select lines
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* - Set the size of the word to be transferred as 32 bit
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* - Set the size of the word to be transferred as 32 bit
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@ -289,7 +289,7 @@ static void zynq_qspi_txfifo_op(struct zynq_qspi *xqspi, unsigned int size)
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*/
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*/
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static void zynq_qspi_chipselect(struct spi_device *spi, bool assert)
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static void zynq_qspi_chipselect(struct spi_device *spi, bool assert)
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{
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{
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struct spi_controller *ctlr = spi->master;
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struct spi_controller *ctlr = spi->controller;
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struct zynq_qspi *xqspi = spi_controller_get_devdata(ctlr);
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struct zynq_qspi *xqspi = spi_controller_get_devdata(ctlr);
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u32 config_reg;
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u32 config_reg;
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@ -377,7 +377,7 @@ static int zynq_qspi_config_op(struct zynq_qspi *xqspi, struct spi_device *spi)
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*/
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*/
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static int zynq_qspi_setup_op(struct spi_device *spi)
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static int zynq_qspi_setup_op(struct spi_device *spi)
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{
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{
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struct spi_controller *ctlr = spi->master;
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struct spi_controller *ctlr = spi->controller;
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struct zynq_qspi *qspi = spi_controller_get_devdata(ctlr);
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struct zynq_qspi *qspi = spi_controller_get_devdata(ctlr);
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if (ctlr->busy)
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if (ctlr->busy)
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@ -525,7 +525,7 @@ static irqreturn_t zynq_qspi_irq(int irq, void *dev_id)
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static int zynq_qspi_exec_mem_op(struct spi_mem *mem,
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static int zynq_qspi_exec_mem_op(struct spi_mem *mem,
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const struct spi_mem_op *op)
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const struct spi_mem_op *op)
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{
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{
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struct zynq_qspi *xqspi = spi_controller_get_devdata(mem->spi->master);
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struct zynq_qspi *xqspi = spi_controller_get_devdata(mem->spi->controller);
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int err = 0, i;
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int err = 0, i;
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u8 *tmpbuf;
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u8 *tmpbuf;
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@ -637,7 +637,7 @@ static int zynq_qspi_probe(struct platform_device *pdev)
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struct zynq_qspi *xqspi;
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struct zynq_qspi *xqspi;
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u32 num_cs;
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u32 num_cs;
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ctlr = spi_alloc_master(&pdev->dev, sizeof(*xqspi));
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ctlr = spi_alloc_host(&pdev->dev, sizeof(*xqspi));
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if (!ctlr)
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if (!ctlr)
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return -ENOMEM;
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return -ENOMEM;
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@ -647,14 +647,14 @@ static int zynq_qspi_probe(struct platform_device *pdev)
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xqspi->regs = devm_platform_ioremap_resource(pdev, 0);
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xqspi->regs = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(xqspi->regs)) {
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if (IS_ERR(xqspi->regs)) {
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ret = PTR_ERR(xqspi->regs);
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ret = PTR_ERR(xqspi->regs);
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goto remove_master;
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goto remove_ctlr;
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}
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}
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xqspi->pclk = devm_clk_get(&pdev->dev, "pclk");
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xqspi->pclk = devm_clk_get(&pdev->dev, "pclk");
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if (IS_ERR(xqspi->pclk)) {
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if (IS_ERR(xqspi->pclk)) {
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dev_err(&pdev->dev, "pclk clock not found.\n");
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dev_err(&pdev->dev, "pclk clock not found.\n");
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ret = PTR_ERR(xqspi->pclk);
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ret = PTR_ERR(xqspi->pclk);
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goto remove_master;
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goto remove_ctlr;
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}
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}
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init_completion(&xqspi->data_completion);
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init_completion(&xqspi->data_completion);
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@ -663,13 +663,13 @@ static int zynq_qspi_probe(struct platform_device *pdev)
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if (IS_ERR(xqspi->refclk)) {
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if (IS_ERR(xqspi->refclk)) {
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dev_err(&pdev->dev, "ref_clk clock not found.\n");
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dev_err(&pdev->dev, "ref_clk clock not found.\n");
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ret = PTR_ERR(xqspi->refclk);
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ret = PTR_ERR(xqspi->refclk);
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goto remove_master;
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goto remove_ctlr;
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}
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}
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ret = clk_prepare_enable(xqspi->pclk);
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ret = clk_prepare_enable(xqspi->pclk);
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if (ret) {
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if (ret) {
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dev_err(&pdev->dev, "Unable to enable APB clock.\n");
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dev_err(&pdev->dev, "Unable to enable APB clock.\n");
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goto remove_master;
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goto remove_ctlr;
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}
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}
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ret = clk_prepare_enable(xqspi->refclk);
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ret = clk_prepare_enable(xqspi->refclk);
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@ -715,7 +715,7 @@ static int zynq_qspi_probe(struct platform_device *pdev)
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ret = devm_spi_register_controller(&pdev->dev, ctlr);
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ret = devm_spi_register_controller(&pdev->dev, ctlr);
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if (ret) {
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if (ret) {
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dev_err(&pdev->dev, "spi_register_master failed\n");
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dev_err(&pdev->dev, "devm_spi_register_controller failed\n");
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goto clk_dis_all;
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goto clk_dis_all;
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}
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}
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@ -725,7 +725,7 @@ clk_dis_all:
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clk_disable_unprepare(xqspi->refclk);
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clk_disable_unprepare(xqspi->refclk);
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clk_dis_pclk:
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clk_dis_pclk:
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clk_disable_unprepare(xqspi->pclk);
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clk_disable_unprepare(xqspi->pclk);
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remove_master:
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remove_ctlr:
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spi_controller_put(ctlr);
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spi_controller_put(ctlr);
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return ret;
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return ret;
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