net/irda: Add SuperH IrDA driver support
This is very simple driver for SuperH Mobile IrDA which support SIR/MIR/FIR. This patch add only SIR support for now. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Kuninori Morimoto
David S. Miller
parent
33d8212c4d
commit
17a328ca8c
@ -397,5 +397,11 @@ config MCS_FIR
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To compile it as a module, choose M here: the module will be called
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mcs7780.
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config SH_IRDA
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tristate "SuperH IrDA driver"
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depends on IRDA && ARCH_SHMOBILE
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help
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Say Y here if your want to enable SuperH IrDA devices.
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endmenu
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@ -19,6 +19,7 @@ obj-$(CONFIG_VIA_FIR) += via-ircc.o
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obj-$(CONFIG_PXA_FICP) += pxaficp_ir.o
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obj-$(CONFIG_MCS_FIR) += mcs7780.o
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obj-$(CONFIG_AU1000_FIR) += au1k_ir.o
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obj-$(CONFIG_SH_IRDA) += sh_irda.o
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# SIR drivers
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obj-$(CONFIG_IRTTY_SIR) += irtty-sir.o sir-dev.o
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obj-$(CONFIG_BFIN_SIR) += bfin_sir.o
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865
drivers/net/irda/sh_irda.c
Normal file
865
drivers/net/irda/sh_irda.c
Normal file
@ -0,0 +1,865 @@
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/*
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* SuperH IrDA Driver
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*
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* Copyright (C) 2010 Renesas Solutions Corp.
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* Kuninori Morimoto <morimoto.kuninori@renesas.com>
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*
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* Based on sh_sir.c
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* Copyright (C) 2009 Renesas Solutions Corp.
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* Copyright 2006-2009 Analog Devices Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/*
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* CAUTION
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*
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* This driver is very simple.
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* So, it doesn't have below support now
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* - MIR/FIR support
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* - DMA transfer support
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* - FIFO mode support
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <net/irda/wrapper.h>
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#include <net/irda/irda_device.h>
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#define DRIVER_NAME "sh_irda"
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#if defined(CONFIG_ARCH_SH7367) || defined(CONFIG_ARCH_SH7377)
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#define __IRDARAM_LEN 0x13FF
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#else
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#define __IRDARAM_LEN 0x1039
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#endif
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#define IRTMR 0x1F00 /* Transfer mode */
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#define IRCFR 0x1F02 /* Configuration */
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#define IRCTR 0x1F04 /* IR control */
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#define IRTFLR 0x1F20 /* Transmit frame length */
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#define IRTCTR 0x1F22 /* Transmit control */
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#define IRRFLR 0x1F40 /* Receive frame length */
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#define IRRCTR 0x1F42 /* Receive control */
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#define SIRISR 0x1F60 /* SIR-UART mode interrupt source */
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#define SIRIMR 0x1F62 /* SIR-UART mode interrupt mask */
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#define SIRICR 0x1F64 /* SIR-UART mode interrupt clear */
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#define SIRBCR 0x1F68 /* SIR-UART mode baud rate count */
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#define MFIRISR 0x1F70 /* MIR/FIR mode interrupt source */
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#define MFIRIMR 0x1F72 /* MIR/FIR mode interrupt mask */
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#define MFIRICR 0x1F74 /* MIR/FIR mode interrupt clear */
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#define CRCCTR 0x1F80 /* CRC engine control */
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#define CRCIR 0x1F86 /* CRC engine input data */
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#define CRCCR 0x1F8A /* CRC engine calculation */
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#define CRCOR 0x1F8E /* CRC engine output data */
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#define FIFOCP 0x1FC0 /* FIFO current pointer */
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#define FIFOFP 0x1FC2 /* FIFO follow pointer */
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#define FIFORSMSK 0x1FC4 /* FIFO receive status mask */
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#define FIFORSOR 0x1FC6 /* FIFO receive status OR */
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#define FIFOSEL 0x1FC8 /* FIFO select */
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#define FIFORS 0x1FCA /* FIFO receive status */
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#define FIFORFL 0x1FCC /* FIFO receive frame length */
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#define FIFORAMCP 0x1FCE /* FIFO RAM current pointer */
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#define FIFORAMFP 0x1FD0 /* FIFO RAM follow pointer */
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#define BIFCTL 0x1FD2 /* BUS interface control */
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#define IRDARAM 0x0000 /* IrDA buffer RAM */
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#define IRDARAM_LEN __IRDARAM_LEN /* - 8/16/32 (read-only for 32) */
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/* IRTMR */
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#define TMD_MASK (0x3 << 14) /* Transfer Mode */
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#define TMD_SIR (0x0 << 14)
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#define TMD_MIR (0x3 << 14)
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#define TMD_FIR (0x2 << 14)
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#define FIFORIM (1 << 8) /* FIFO receive interrupt mask */
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#define MIM (1 << 4) /* MIR/FIR Interrupt Mask */
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#define SIM (1 << 0) /* SIR Interrupt Mask */
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#define xIM_MASK (FIFORIM | MIM | SIM)
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/* IRCFR */
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#define RTO_SHIFT 8 /* shift for Receive Timeout */
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#define RTO (0x3 << RTO_SHIFT)
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/* IRTCTR */
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#define ARMOD (1 << 15) /* Auto-Receive Mode */
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#define TE (1 << 0) /* Transmit Enable */
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/* IRRFLR */
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#define RFL_MASK (0x1FFF) /* mask for Receive Frame Length */
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/* IRRCTR */
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#define RE (1 << 0) /* Receive Enable */
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/*
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* SIRISR, SIRIMR, SIRICR,
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* MFIRISR, MFIRIMR, MFIRICR
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*/
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#define FRE (1 << 15) /* Frame Receive End */
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#define TROV (1 << 11) /* Transfer Area Overflow */
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#define xIR_9 (1 << 9)
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#define TOT xIR_9 /* for SIR Timeout */
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#define ABTD xIR_9 /* for MIR/FIR Abort Detection */
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#define xIR_8 (1 << 8)
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#define FER xIR_8 /* for SIR Framing Error */
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#define CRCER xIR_8 /* for MIR/FIR CRC error */
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#define FTE (1 << 7) /* Frame Transmit End */
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#define xIR_MASK (FRE | TROV | xIR_9 | xIR_8 | FTE)
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/* SIRBCR */
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#define BRC_MASK (0x3F) /* mask for Baud Rate Count */
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/* CRCCTR */
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#define CRC_RST (1 << 15) /* CRC Engine Reset */
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#define CRC_CT_MASK 0x0FFF /* mask for CRC Engine Input Data Count */
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/* CRCIR */
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#define CRC_IN_MASK 0x0FFF /* mask for CRC Engine Input Data */
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/************************************************************************
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enum / structure
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************************************************************************/
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enum sh_irda_mode {
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SH_IRDA_NONE = 0,
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SH_IRDA_SIR,
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SH_IRDA_MIR,
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SH_IRDA_FIR,
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};
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struct sh_irda_self;
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struct sh_irda_xir_func {
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int (*xir_fre) (struct sh_irda_self *self);
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int (*xir_trov) (struct sh_irda_self *self);
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int (*xir_9) (struct sh_irda_self *self);
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int (*xir_8) (struct sh_irda_self *self);
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int (*xir_fte) (struct sh_irda_self *self);
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};
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struct sh_irda_self {
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void __iomem *membase;
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unsigned int irq;
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struct clk *clk;
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struct net_device *ndev;
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struct irlap_cb *irlap;
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struct qos_info qos;
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iobuff_t tx_buff;
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iobuff_t rx_buff;
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enum sh_irda_mode mode;
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spinlock_t lock;
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struct sh_irda_xir_func *xir_func;
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};
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/************************************************************************
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common function
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************************************************************************/
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static void sh_irda_write(struct sh_irda_self *self, u32 offset, u16 data)
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{
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unsigned long flags;
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spin_lock_irqsave(&self->lock, flags);
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iowrite16(data, self->membase + offset);
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spin_unlock_irqrestore(&self->lock, flags);
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}
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static u16 sh_irda_read(struct sh_irda_self *self, u32 offset)
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{
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unsigned long flags;
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u16 ret;
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spin_lock_irqsave(&self->lock, flags);
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ret = ioread16(self->membase + offset);
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spin_unlock_irqrestore(&self->lock, flags);
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return ret;
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}
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static void sh_irda_update_bits(struct sh_irda_self *self, u32 offset,
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u16 mask, u16 data)
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{
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unsigned long flags;
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u16 old, new;
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spin_lock_irqsave(&self->lock, flags);
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old = ioread16(self->membase + offset);
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new = (old & ~mask) | data;
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if (old != new)
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iowrite16(data, self->membase + offset);
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spin_unlock_irqrestore(&self->lock, flags);
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}
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/************************************************************************
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mode function
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************************************************************************/
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/*=====================================
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*
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* common
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*
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*=====================================*/
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static void sh_irda_rcv_ctrl(struct sh_irda_self *self, int enable)
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{
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struct device *dev = &self->ndev->dev;
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sh_irda_update_bits(self, IRRCTR, RE, enable ? RE : 0);
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dev_dbg(dev, "recv %s\n", enable ? "enable" : "disable");
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}
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static int sh_irda_set_timeout(struct sh_irda_self *self, int interval)
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{
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struct device *dev = &self->ndev->dev;
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if (SH_IRDA_SIR != self->mode)
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interval = 0;
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if (interval < 0 || interval > 2) {
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dev_err(dev, "unsupported timeout interval\n");
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return -EINVAL;
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}
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sh_irda_update_bits(self, IRCFR, RTO, interval << RTO_SHIFT);
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return 0;
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}
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static int sh_irda_set_baudrate(struct sh_irda_self *self, int baudrate)
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{
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struct device *dev = &self->ndev->dev;
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u16 val;
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if (baudrate < 0)
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return 0;
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if (SH_IRDA_SIR != self->mode) {
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dev_err(dev, "it is not SIR mode\n");
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return -EINVAL;
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}
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/*
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* Baud rate (bits/s) =
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* (48 MHz / 26) / (baud rate counter value + 1) x 16
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*/
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val = (48000000 / 26 / 16 / baudrate) - 1;
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dev_dbg(dev, "baudrate = %d, val = 0x%02x\n", baudrate, val);
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sh_irda_update_bits(self, SIRBCR, BRC_MASK, val);
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return 0;
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}
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static int xir_get_rcv_length(struct sh_irda_self *self)
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{
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return RFL_MASK & sh_irda_read(self, IRRFLR);
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}
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/*=====================================
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*
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* NONE MODE
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*
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*=====================================*/
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static int xir_fre(struct sh_irda_self *self)
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{
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struct device *dev = &self->ndev->dev;
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dev_err(dev, "none mode: frame recv\n");
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return 0;
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}
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static int xir_trov(struct sh_irda_self *self)
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{
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struct device *dev = &self->ndev->dev;
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dev_err(dev, "none mode: buffer ram over\n");
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return 0;
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}
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static int xir_9(struct sh_irda_self *self)
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{
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struct device *dev = &self->ndev->dev;
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dev_err(dev, "none mode: time over\n");
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return 0;
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}
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static int xir_8(struct sh_irda_self *self)
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{
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struct device *dev = &self->ndev->dev;
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dev_err(dev, "none mode: framing error\n");
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return 0;
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}
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static int xir_fte(struct sh_irda_self *self)
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{
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struct device *dev = &self->ndev->dev;
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dev_err(dev, "none mode: frame transmit end\n");
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return 0;
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}
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static struct sh_irda_xir_func xir_func = {
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.xir_fre = xir_fre,
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.xir_trov = xir_trov,
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.xir_9 = xir_9,
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.xir_8 = xir_8,
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.xir_fte = xir_fte,
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};
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/*=====================================
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*
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* MIR/FIR MODE
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*
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* MIR/FIR are not supported now
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*=====================================*/
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static struct sh_irda_xir_func mfir_func = {
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.xir_fre = xir_fre,
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.xir_trov = xir_trov,
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.xir_9 = xir_9,
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.xir_8 = xir_8,
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.xir_fte = xir_fte,
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};
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/*=====================================
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*
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* SIR MODE
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*
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*=====================================*/
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static int sir_fre(struct sh_irda_self *self)
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{
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struct device *dev = &self->ndev->dev;
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u16 data16;
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u8 *data = (u8 *)&data16;
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int len = xir_get_rcv_length(self);
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int i, j;
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if (len > IRDARAM_LEN)
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len = IRDARAM_LEN;
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dev_dbg(dev, "frame recv length = %d\n", len);
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for (i = 0; i < len; i++) {
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j = i % 2;
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if (!j)
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data16 = sh_irda_read(self, IRDARAM + i);
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async_unwrap_char(self->ndev, &self->ndev->stats,
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&self->rx_buff, data[j]);
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}
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self->ndev->last_rx = jiffies;
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sh_irda_rcv_ctrl(self, 1);
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return 0;
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}
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static int sir_trov(struct sh_irda_self *self)
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{
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struct device *dev = &self->ndev->dev;
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dev_err(dev, "buffer ram over\n");
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sh_irda_rcv_ctrl(self, 1);
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return 0;
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}
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static int sir_tot(struct sh_irda_self *self)
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{
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struct device *dev = &self->ndev->dev;
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dev_err(dev, "time over\n");
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sh_irda_set_baudrate(self, 9600);
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sh_irda_rcv_ctrl(self, 1);
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return 0;
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}
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static int sir_fer(struct sh_irda_self *self)
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{
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struct device *dev = &self->ndev->dev;
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dev_err(dev, "framing error\n");
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sh_irda_rcv_ctrl(self, 1);
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return 0;
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}
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static int sir_fte(struct sh_irda_self *self)
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{
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struct device *dev = &self->ndev->dev;
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dev_dbg(dev, "frame transmit end\n");
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netif_wake_queue(self->ndev);
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return 0;
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}
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static struct sh_irda_xir_func sir_func = {
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.xir_fre = sir_fre,
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.xir_trov = sir_trov,
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.xir_9 = sir_tot,
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.xir_8 = sir_fer,
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.xir_fte = sir_fte,
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};
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static void sh_irda_set_mode(struct sh_irda_self *self, enum sh_irda_mode mode)
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{
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struct device *dev = &self->ndev->dev;
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struct sh_irda_xir_func *func;
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const char *name;
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u16 data;
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switch (mode) {
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case SH_IRDA_SIR:
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name = "SIR";
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data = TMD_SIR;
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func = &sir_func;
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break;
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case SH_IRDA_MIR:
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name = "MIR";
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data = TMD_MIR;
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func = &mfir_func;
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break;
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case SH_IRDA_FIR:
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name = "FIR";
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data = TMD_FIR;
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func = &mfir_func;
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break;
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default:
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name = "NONE";
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data = 0;
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func = &xir_func;
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break;
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}
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self->mode = mode;
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self->xir_func = func;
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sh_irda_update_bits(self, IRTMR, TMD_MASK, data);
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dev_dbg(dev, "switch to %s mode", name);
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}
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/************************************************************************
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irq function
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************************************************************************/
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static void sh_irda_set_irq_mask(struct sh_irda_self *self)
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{
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u16 tmr_hole;
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u16 xir_reg;
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||||
|
||||
/* set all mask */
|
||||
sh_irda_update_bits(self, IRTMR, xIM_MASK, xIM_MASK);
|
||||
sh_irda_update_bits(self, SIRIMR, xIR_MASK, xIR_MASK);
|
||||
sh_irda_update_bits(self, MFIRIMR, xIR_MASK, xIR_MASK);
|
||||
|
||||
/* clear irq */
|
||||
sh_irda_update_bits(self, SIRICR, xIR_MASK, xIR_MASK);
|
||||
sh_irda_update_bits(self, MFIRICR, xIR_MASK, xIR_MASK);
|
||||
|
||||
switch (self->mode) {
|
||||
case SH_IRDA_SIR:
|
||||
tmr_hole = SIM;
|
||||
xir_reg = SIRIMR;
|
||||
break;
|
||||
case SH_IRDA_MIR:
|
||||
case SH_IRDA_FIR:
|
||||
tmr_hole = MIM;
|
||||
xir_reg = MFIRIMR;
|
||||
break;
|
||||
default:
|
||||
tmr_hole = 0;
|
||||
xir_reg = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
/* open mask */
|
||||
if (xir_reg) {
|
||||
sh_irda_update_bits(self, IRTMR, tmr_hole, 0);
|
||||
sh_irda_update_bits(self, xir_reg, xIR_MASK, 0);
|
||||
}
|
||||
}
|
||||
|
||||
static irqreturn_t sh_irda_irq(int irq, void *dev_id)
|
||||
{
|
||||
struct sh_irda_self *self = dev_id;
|
||||
struct sh_irda_xir_func *func = self->xir_func;
|
||||
u16 isr = sh_irda_read(self, SIRISR);
|
||||
|
||||
/* clear irq */
|
||||
sh_irda_write(self, SIRICR, isr);
|
||||
|
||||
if (isr & FRE)
|
||||
func->xir_fre(self);
|
||||
if (isr & TROV)
|
||||
func->xir_trov(self);
|
||||
if (isr & xIR_9)
|
||||
func->xir_9(self);
|
||||
if (isr & xIR_8)
|
||||
func->xir_8(self);
|
||||
if (isr & FTE)
|
||||
func->xir_fte(self);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
/************************************************************************
|
||||
|
||||
|
||||
CRC function
|
||||
|
||||
|
||||
************************************************************************/
|
||||
static void sh_irda_crc_reset(struct sh_irda_self *self)
|
||||
{
|
||||
sh_irda_write(self, CRCCTR, CRC_RST);
|
||||
}
|
||||
|
||||
static void sh_irda_crc_add(struct sh_irda_self *self, u16 data)
|
||||
{
|
||||
sh_irda_write(self, CRCIR, data & CRC_IN_MASK);
|
||||
}
|
||||
|
||||
static u16 sh_irda_crc_cnt(struct sh_irda_self *self)
|
||||
{
|
||||
return CRC_CT_MASK & sh_irda_read(self, CRCCTR);
|
||||
}
|
||||
|
||||
static u16 sh_irda_crc_out(struct sh_irda_self *self)
|
||||
{
|
||||
return sh_irda_read(self, CRCOR);
|
||||
}
|
||||
|
||||
static int sh_irda_crc_init(struct sh_irda_self *self)
|
||||
{
|
||||
struct device *dev = &self->ndev->dev;
|
||||
int ret = -EIO;
|
||||
u16 val;
|
||||
|
||||
sh_irda_crc_reset(self);
|
||||
|
||||
sh_irda_crc_add(self, 0xCC);
|
||||
sh_irda_crc_add(self, 0xF5);
|
||||
sh_irda_crc_add(self, 0xF1);
|
||||
sh_irda_crc_add(self, 0xA7);
|
||||
|
||||
val = sh_irda_crc_cnt(self);
|
||||
if (4 != val) {
|
||||
dev_err(dev, "CRC count error %x\n", val);
|
||||
goto crc_init_out;
|
||||
}
|
||||
|
||||
val = sh_irda_crc_out(self);
|
||||
if (0x51DF != val) {
|
||||
dev_err(dev, "CRC result error%x\n", val);
|
||||
goto crc_init_out;
|
||||
}
|
||||
|
||||
ret = 0;
|
||||
|
||||
crc_init_out:
|
||||
|
||||
sh_irda_crc_reset(self);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/************************************************************************
|
||||
|
||||
|
||||
iobuf function
|
||||
|
||||
|
||||
************************************************************************/
|
||||
static void sh_irda_remove_iobuf(struct sh_irda_self *self)
|
||||
{
|
||||
kfree(self->rx_buff.head);
|
||||
|
||||
self->tx_buff.head = NULL;
|
||||
self->tx_buff.data = NULL;
|
||||
self->rx_buff.head = NULL;
|
||||
self->rx_buff.data = NULL;
|
||||
}
|
||||
|
||||
static int sh_irda_init_iobuf(struct sh_irda_self *self, int rxsize, int txsize)
|
||||
{
|
||||
if (self->rx_buff.head ||
|
||||
self->tx_buff.head) {
|
||||
dev_err(&self->ndev->dev, "iobuff has already existed.");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* rx_buff */
|
||||
self->rx_buff.head = kmalloc(rxsize, GFP_KERNEL);
|
||||
if (!self->rx_buff.head)
|
||||
return -ENOMEM;
|
||||
|
||||
self->rx_buff.truesize = rxsize;
|
||||
self->rx_buff.in_frame = FALSE;
|
||||
self->rx_buff.state = OUTSIDE_FRAME;
|
||||
self->rx_buff.data = self->rx_buff.head;
|
||||
|
||||
/* tx_buff */
|
||||
self->tx_buff.head = self->membase + IRDARAM;
|
||||
self->tx_buff.truesize = IRDARAM_LEN;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/************************************************************************
|
||||
|
||||
|
||||
net_device_ops function
|
||||
|
||||
|
||||
************************************************************************/
|
||||
static int sh_irda_hard_xmit(struct sk_buff *skb, struct net_device *ndev)
|
||||
{
|
||||
struct sh_irda_self *self = netdev_priv(ndev);
|
||||
struct device *dev = &self->ndev->dev;
|
||||
int speed = irda_get_next_speed(skb);
|
||||
int ret;
|
||||
|
||||
dev_dbg(dev, "hard xmit\n");
|
||||
|
||||
netif_stop_queue(ndev);
|
||||
sh_irda_rcv_ctrl(self, 0);
|
||||
|
||||
ret = sh_irda_set_baudrate(self, speed);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
self->tx_buff.len = 0;
|
||||
if (skb->len) {
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&self->lock, flags);
|
||||
self->tx_buff.len = async_wrap_skb(skb,
|
||||
self->tx_buff.head,
|
||||
self->tx_buff.truesize);
|
||||
spin_unlock_irqrestore(&self->lock, flags);
|
||||
|
||||
if (self->tx_buff.len > self->tx_buff.truesize)
|
||||
self->tx_buff.len = self->tx_buff.truesize;
|
||||
|
||||
sh_irda_write(self, IRTFLR, self->tx_buff.len);
|
||||
sh_irda_write(self, IRTCTR, ARMOD | TE);
|
||||
}
|
||||
|
||||
dev_kfree_skb(skb);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sh_irda_ioctl(struct net_device *ndev, struct ifreq *ifreq, int cmd)
|
||||
{
|
||||
/*
|
||||
* FIXME
|
||||
*
|
||||
* This function is needed for irda framework.
|
||||
* But nothing to do now
|
||||
*/
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct net_device_stats *sh_irda_stats(struct net_device *ndev)
|
||||
{
|
||||
struct sh_irda_self *self = netdev_priv(ndev);
|
||||
|
||||
return &self->ndev->stats;
|
||||
}
|
||||
|
||||
static int sh_irda_open(struct net_device *ndev)
|
||||
{
|
||||
struct sh_irda_self *self = netdev_priv(ndev);
|
||||
int err;
|
||||
|
||||
clk_enable(self->clk);
|
||||
err = sh_irda_crc_init(self);
|
||||
if (err)
|
||||
goto open_err;
|
||||
|
||||
sh_irda_set_mode(self, SH_IRDA_SIR);
|
||||
sh_irda_set_timeout(self, 2);
|
||||
sh_irda_set_baudrate(self, 9600);
|
||||
|
||||
self->irlap = irlap_open(ndev, &self->qos, DRIVER_NAME);
|
||||
if (!self->irlap) {
|
||||
err = -ENODEV;
|
||||
goto open_err;
|
||||
}
|
||||
|
||||
netif_start_queue(ndev);
|
||||
sh_irda_rcv_ctrl(self, 1);
|
||||
sh_irda_set_irq_mask(self);
|
||||
|
||||
dev_info(&ndev->dev, "opened\n");
|
||||
|
||||
return 0;
|
||||
|
||||
open_err:
|
||||
clk_disable(self->clk);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static int sh_irda_stop(struct net_device *ndev)
|
||||
{
|
||||
struct sh_irda_self *self = netdev_priv(ndev);
|
||||
|
||||
/* Stop IrLAP */
|
||||
if (self->irlap) {
|
||||
irlap_close(self->irlap);
|
||||
self->irlap = NULL;
|
||||
}
|
||||
|
||||
netif_stop_queue(ndev);
|
||||
|
||||
dev_info(&ndev->dev, "stoped\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct net_device_ops sh_irda_ndo = {
|
||||
.ndo_open = sh_irda_open,
|
||||
.ndo_stop = sh_irda_stop,
|
||||
.ndo_start_xmit = sh_irda_hard_xmit,
|
||||
.ndo_do_ioctl = sh_irda_ioctl,
|
||||
.ndo_get_stats = sh_irda_stats,
|
||||
};
|
||||
|
||||
/************************************************************************
|
||||
|
||||
|
||||
platform_driver function
|
||||
|
||||
|
||||
************************************************************************/
|
||||
static int __devinit sh_irda_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct net_device *ndev;
|
||||
struct sh_irda_self *self;
|
||||
struct resource *res;
|
||||
char clk_name[8];
|
||||
unsigned int irq;
|
||||
int err = -ENOMEM;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (!res || irq < 0) {
|
||||
dev_err(&pdev->dev, "Not enough platform resources.\n");
|
||||
goto exit;
|
||||
}
|
||||
|
||||
ndev = alloc_irdadev(sizeof(*self));
|
||||
if (!ndev)
|
||||
goto exit;
|
||||
|
||||
self = netdev_priv(ndev);
|
||||
self->membase = ioremap_nocache(res->start, resource_size(res));
|
||||
if (!self->membase) {
|
||||
err = -ENXIO;
|
||||
dev_err(&pdev->dev, "Unable to ioremap.\n");
|
||||
goto err_mem_1;
|
||||
}
|
||||
|
||||
err = sh_irda_init_iobuf(self, IRDA_SKB_MAX_MTU, IRDA_SIR_MAX_FRAME);
|
||||
if (err)
|
||||
goto err_mem_2;
|
||||
|
||||
snprintf(clk_name, sizeof(clk_name), "irda%d", pdev->id);
|
||||
self->clk = clk_get(&pdev->dev, clk_name);
|
||||
if (IS_ERR(self->clk)) {
|
||||
dev_err(&pdev->dev, "cannot get clock \"%s\"\n", clk_name);
|
||||
goto err_mem_3;
|
||||
}
|
||||
|
||||
irda_init_max_qos_capabilies(&self->qos);
|
||||
|
||||
ndev->netdev_ops = &sh_irda_ndo;
|
||||
ndev->irq = irq;
|
||||
|
||||
self->ndev = ndev;
|
||||
self->qos.baud_rate.bits &= IR_9600; /* FIXME */
|
||||
self->qos.min_turn_time.bits = 1; /* 10 ms or more */
|
||||
spin_lock_init(&self->lock);
|
||||
|
||||
irda_qos_bits_to_value(&self->qos);
|
||||
|
||||
err = register_netdev(ndev);
|
||||
if (err)
|
||||
goto err_mem_4;
|
||||
|
||||
platform_set_drvdata(pdev, ndev);
|
||||
|
||||
if (request_irq(irq, sh_irda_irq, IRQF_DISABLED, "sh_irda", self)) {
|
||||
dev_warn(&pdev->dev, "Unable to attach sh_irda interrupt\n");
|
||||
goto err_mem_4;
|
||||
}
|
||||
|
||||
dev_info(&pdev->dev, "SuperH IrDA probed\n");
|
||||
|
||||
goto exit;
|
||||
|
||||
err_mem_4:
|
||||
clk_put(self->clk);
|
||||
err_mem_3:
|
||||
sh_irda_remove_iobuf(self);
|
||||
err_mem_2:
|
||||
iounmap(self->membase);
|
||||
err_mem_1:
|
||||
free_netdev(ndev);
|
||||
exit:
|
||||
return err;
|
||||
}
|
||||
|
||||
static int __devexit sh_irda_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct net_device *ndev = platform_get_drvdata(pdev);
|
||||
struct sh_irda_self *self = netdev_priv(ndev);
|
||||
|
||||
if (!self)
|
||||
return 0;
|
||||
|
||||
unregister_netdev(ndev);
|
||||
clk_put(self->clk);
|
||||
sh_irda_remove_iobuf(self);
|
||||
iounmap(self->membase);
|
||||
free_netdev(ndev);
|
||||
platform_set_drvdata(pdev, NULL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver sh_irda_driver = {
|
||||
.probe = sh_irda_probe,
|
||||
.remove = __devexit_p(sh_irda_remove),
|
||||
.driver = {
|
||||
.name = DRIVER_NAME,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init sh_irda_init(void)
|
||||
{
|
||||
return platform_driver_register(&sh_irda_driver);
|
||||
}
|
||||
|
||||
static void __exit sh_irda_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&sh_irda_driver);
|
||||
}
|
||||
|
||||
module_init(sh_irda_init);
|
||||
module_exit(sh_irda_exit);
|
||||
|
||||
MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");
|
||||
MODULE_DESCRIPTION("SuperH IrDA driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
Loading…
Reference in New Issue
Block a user