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i2c-designware: always set the STOP bit after last byte

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If IC_EMPTYFIFO_HOLD_MASTER_EN is set to one, the DesignWare I2C controller
doesn't generate STOP on the bus when the FIFO is empty. This violates the
rules of Linux I2C stack as it requires that the STOP is issued once the
i2c_transfer() is finished.

However, there is no way to detect this from the hardware registers, so we
must make sure that the STOP bit is always set once the last byte of the
last message is transferred.

This patch is based on the work of Dirk Brandewie.

Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
This commit is contained in:
Mika Westerberg 2013-01-17 12:31:05 +02:00 committed by Wolfram Sang
parent 5c38dc8911
commit 17a76b4b32
1 changed files with 14 additions and 2 deletions
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16
drivers/i2c/busses/i2c-designware-core.c
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@ -413,11 +413,23 @@ i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
rx_limit = dev->rx_fifo_depth - dw_readl(dev, DW_IC_RXFLR);
while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) {
u32 cmd = 0;
/*
* If IC_EMPTYFIFO_HOLD_MASTER_EN is set we must
* manually set the stop bit. However, it cannot be
* detected from the registers so we set it always
* when writing/reading the last byte.
*/
if (dev->msg_write_idx == dev->msgs_num - 1 &&
buf_len == 1)
cmd |= BIT(9);
if (msgs[dev->msg_write_idx].flags & I2C_M_RD) {
dw_writel(dev, 0x100, DW_IC_DATA_CMD);
dw_writel(dev, cmd | 0x100, DW_IC_DATA_CMD);
rx_limit--;
} else
dw_writel(dev, *buf++, DW_IC_DATA_CMD);
dw_writel(dev, cmd | *buf++, DW_IC_DATA_CMD);
tx_limit--; buf_len--;
}