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ARM: dts: usr8200: Fix phy registers

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The MV88E6060 switch has internal PHY registers at MDIO
addresses 0x00..0x04. Tie each port to the corresponding
PHY.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20231020-ixp4xx-usr8200-dtsfix-v1-1-3a8591dea259@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Linus Walleij 2023-10-20 15:11:41 +02:00 committed by Arnd Bergmann
parent 3f2f25b5ae
commit 18a1ee9d71
1 changed files with 22 additions and 0 deletions
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22
arch/arm/boot/dts/intel/ixp/intel-ixp42x-usrobotics-usr8200.dts
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@ -165,6 +165,24 @@
#address-cells = <1>;
#size-cells = <0>;
/*
* PHY 0..4 are internal to the MV88E6060 switch but appear
* as independent devices.
*/
phy0: ethernet-phy@0 {
reg = <0>;
};
phy1: ethernet-phy@1 {
reg = <1>;
};
phy2: ethernet-phy@2 {
reg = <2>;
};
phy3: ethernet-phy@3 {
reg = <3>;
};
/* Altima AMI101L used by the WAN port */
phy9: ethernet-phy@9 {
reg = <9>;
};
@ -181,21 +199,25 @@
port@0 {
reg = <0>;
label = "lan1";
phy-handle = <&phy0>;
};
port@1 {
reg = <1>;
label = "lan2";
phy-handle = <&phy1>;
};
port@2 {
reg = <2>;
label = "lan3";
phy-handle = <&phy2>;
};
port@3 {
reg = <3>;
label = "lan4";
phy-handle = <&phy3>;
};
port@5 {