drm/amd/display: Implement DPIA clock recovery phase
[Why] Clock recovery is the mandatory first phase of DP link training. [How] - Implement clock recovery phase in DPIA training module. - Add helper functions for building SET_CONFIG messages. Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Wayne Lin <Wayne.Lin@amd.com> Acked-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Jimmy Kizito <Jimmy.Kizito@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Jimmy Kizito
Alex Deucher
parent
187c236aac
commit
18b11f9bd4
@ -29,6 +29,9 @@
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#include "inc/core_status.h"
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#include "inc/core_status.h"
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#include "dc_link.h"
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#include "dc_link.h"
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#include "dc_link_dp.h"
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#include "dc_link_dp.h"
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#include "dpcd_defs.h"
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#include "link_hwss.h"
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#include "inc/link_dpcd.h"
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#define DC_LOGGER \
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#define DC_LOGGER \
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link->ctx->logger
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link->ctx->logger
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@ -88,17 +91,389 @@ static enum link_training_result dpia_configure_link(struct dc_link *link,
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return LINK_TRAINING_SUCCESS;
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return LINK_TRAINING_SUCCESS;
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}
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}
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static enum dc_status core_link_send_set_config(struct dc_link *link,
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uint8_t msg_type, uint8_t msg_data)
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{
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/** @todo Implement */
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return DC_OK;
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}
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/* Build SET_CONFIG message data payload for specified message type. */
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static uint8_t dpia_build_set_config_data(enum dpia_set_config_type type,
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struct dc_link *link,
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struct link_training_settings *lt_settings)
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{
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union dpia_set_config_data data;
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data.raw = 0;
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switch (type) {
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case DPIA_SET_CFG_SET_LINK:
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data.set_link.mode = link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT ? 1 : 0;
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break;
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case DPIA_SET_CFG_SET_PHY_TEST_MODE:
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break;
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case DPIA_SET_CFG_SET_VSPE:
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/* Assume all lanes have same drive settings. */
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data.set_vspe.swing = lt_settings->lane_settings[0].VOLTAGE_SWING;
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data.set_vspe.pre_emph = lt_settings->lane_settings[0].PRE_EMPHASIS;
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data.set_vspe.max_swing_reached =
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lt_settings->lane_settings[0].VOLTAGE_SWING ==
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VOLTAGE_SWING_MAX_LEVEL ? 1 : 0;
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data.set_vspe.max_pre_emph_reached =
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lt_settings->lane_settings[0].PRE_EMPHASIS ==
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PRE_EMPHASIS_MAX_LEVEL ? 1 : 0;
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break;
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default:
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ASSERT(false); /* Message type not supported by helper function. */
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break;
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}
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return data.raw;
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}
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/* Convert DC training pattern to DPIA training stage. */
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static enum dpia_set_config_ts convert_trng_ptn_to_trng_stg(enum dc_dp_training_pattern tps)
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{
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enum dpia_set_config_ts ts;
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switch (tps) {
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case DP_TRAINING_PATTERN_SEQUENCE_1:
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ts = DPIA_TS_TPS1;
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break;
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case DP_TRAINING_PATTERN_SEQUENCE_2:
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ts = DPIA_TS_TPS2;
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break;
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case DP_TRAINING_PATTERN_SEQUENCE_3:
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ts = DPIA_TS_TPS3;
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break;
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case DP_TRAINING_PATTERN_SEQUENCE_4:
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ts = DPIA_TS_TPS4;
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break;
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default:
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ASSERT(false); /* TPS not supported by helper function. */
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break;
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}
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return ts;
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}
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/* Write training pattern to DPCD. */
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static enum dc_status dpcd_set_lt_pattern(struct dc_link *link,
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enum dc_dp_training_pattern pattern,
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uint32_t hop)
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{
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union dpcd_training_pattern dpcd_pattern = { {0} };
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uint32_t dpcd_tps_offset = DP_TRAINING_PATTERN_SET;
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enum dc_status status;
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if (hop != DPRX)
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dpcd_tps_offset = DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
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((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (hop - 1));
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/* DpcdAddress_TrainingPatternSet */
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dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
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dc_dp_training_pattern_to_dpcd_training_pattern(link, pattern);
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dpcd_pattern.v1_4.SCRAMBLING_DISABLE =
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dc_dp_initialize_scrambling_data_symbols(link, pattern);
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if (hop != DPRX) {
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DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n 0x%X pattern = %x\n",
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__func__,
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hop,
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dpcd_tps_offset,
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dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
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} else {
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DC_LOG_HW_LINK_TRAINING("%s\n 0x%X pattern = %x\n",
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__func__,
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dpcd_tps_offset,
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dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
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}
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status = core_link_write_dpcd(link,
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DP_TRAINING_PATTERN_SET,
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&dpcd_pattern.raw,
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sizeof(dpcd_pattern.raw));
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return status;
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}
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/* Execute clock recovery phase of link training for specified hop in display
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* path.in non-transparent mode:
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* - Driver issues both DPCD and SET_CONFIG transactions.
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* - TPS1 is transmitted for any hops downstream of DPOA.
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* - Drive (VS/PE) only transmitted for the hop immediately downstream of DPOA.
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* - CR for the first hop (DPTX-to-DPIA) is assumed to be successful.
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*
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* @param link DPIA link being trained.
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* @param lt_settings link_setting and drive settings (voltage swing and pre-emphasis).
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* @param hop The Hop in display path. DPRX = 0.
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*/
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static enum link_training_result dpia_training_cr_non_transparent(struct dc_link *link,
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struct link_training_settings *lt_settings,
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uint32_t hop)
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{
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enum link_training_result result = LINK_TRAINING_CR_FAIL_LANE0;
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uint8_t repeater_cnt = 0; /* Number of hops/repeaters in display path. */
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enum dc_status status;
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uint32_t retries_cr = 0; /* Number of consecutive attempts with same VS or PE. */
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uint32_t retry_count = 0;
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/* From DP spec, CR read interval is always 100us. */
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uint32_t wait_time_microsec = TRAINING_AUX_RD_INTERVAL;
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struct link_training_settings req_settings;
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enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
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union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } };
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union lane_align_status_updated dpcd_lane_status_updated = { {0} };
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uint8_t set_cfg_data;
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enum dpia_set_config_ts ts;
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repeater_cnt = dp_convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
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/* Cap of LINK_TRAINING_MAX_CR_RETRY attempts at clock recovery.
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* Fix inherited from perform_clock_recovery_sequence() -
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* the DP equivalent of this function:
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* Required for Synaptics MST hub which can put the LT in
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* infinite loop by switching the VS between level 0 and level 1
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* continuously.
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*/
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while ((retries_cr < LINK_TRAINING_MAX_RETRY_COUNT) &&
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(retry_count < LINK_TRAINING_MAX_CR_RETRY)) {
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/* DPTX-to-DPIA */
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if (hop == repeater_cnt) {
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/* Send SET_CONFIG(SET_LINK:LC,LR,LTTPR) to notify DPOA that
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* non-transparent link training has started.
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* This also enables the transmission of clk_sync packets.
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*/
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set_cfg_data = dpia_build_set_config_data(DPIA_SET_CFG_SET_LINK,
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link,
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lt_settings);
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status = core_link_send_set_config(link,
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DPIA_SET_CFG_SET_LINK,
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set_cfg_data);
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/* CR for this hop is considered successful as long as
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* SET_CONFIG message is acknowledged by DPOA.
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*/
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if (status == DC_OK)
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result = LINK_TRAINING_SUCCESS;
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else
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result = LINK_TRAINING_ABORT;
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break;
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}
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/* DPOA-to-x */
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/* Instruct DPOA to transmit TPS1 then update DPCD. */
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if (retry_count == 0) {
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ts = convert_trng_ptn_to_trng_stg(lt_settings->pattern_for_cr);
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status = core_link_send_set_config(link,
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DPIA_SET_CFG_SET_TRAINING,
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ts);
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if (status != DC_OK) {
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result = LINK_TRAINING_ABORT;
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break;
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}
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status = dpcd_set_lt_pattern(link, lt_settings->pattern_for_cr, hop);
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if (status != DC_OK) {
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result = LINK_TRAINING_ABORT;
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break;
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}
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}
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/* Update DPOA drive settings then DPCD. DPOA does only adjusts
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* drive settings for hops immediately downstream.
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*/
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if (hop == repeater_cnt - 1) {
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set_cfg_data = dpia_build_set_config_data(DPIA_SET_CFG_SET_VSPE,
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link,
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lt_settings);
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status = core_link_send_set_config(link,
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DPIA_SET_CFG_SET_VSPE,
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set_cfg_data);
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if (status != DC_OK) {
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result = LINK_TRAINING_ABORT;
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break;
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}
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}
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status = dpcd_set_lane_settings(link, lt_settings, hop);
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if (status != DC_OK) {
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result = LINK_TRAINING_ABORT;
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break;
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}
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dp_wait_for_training_aux_rd_interval(link, wait_time_microsec);
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/* Read status and adjustment requests from DPCD. */
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status = dp_get_lane_status_and_drive_settings(link,
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lt_settings,
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dpcd_lane_status,
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&dpcd_lane_status_updated,
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&req_settings,
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hop);
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if (status != DC_OK) {
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result = LINK_TRAINING_ABORT;
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break;
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}
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/* Check if clock recovery successful. */
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if (dp_is_cr_done(lane_count, dpcd_lane_status)) {
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result = LINK_TRAINING_SUCCESS;
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break;
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}
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result = dp_get_cr_failure(lane_count, dpcd_lane_status);
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if (dp_is_max_vs_reached(lt_settings))
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break;
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/* Count number of attempts with same drive settings.
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* Note: settings are the same for all lanes,
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* so comparing first lane is sufficient.
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*/
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if (lt_settings->lane_settings[0].VOLTAGE_SWING ==
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req_settings.lane_settings[0].VOLTAGE_SWING &&
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lt_settings->lane_settings[0].PRE_EMPHASIS ==
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req_settings.lane_settings[0].PRE_EMPHASIS)
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retries_cr++;
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else
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retries_cr = 0;
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/* Update VS/PE. */
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dp_update_drive_settings(lt_settings, req_settings);
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retry_count++;
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}
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/* Abort link training if clock recovery failed due to HPD unplug. */
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if (!link->hpd_status)
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result = LINK_TRAINING_ABORT;
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DC_LOG_HW_LINK_TRAINING("%s\n DPIA(%d) clock recovery\n"
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" -hop(%d)\n - result(%d)\n - retries(%d)\n",
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__func__,
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link->link_id.enum_id - ENUM_ID_1,
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hop,
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result,
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retry_count);
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return result;
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}
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/* Execute clock recovery phase of link training in transparent LTTPR mode:
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* - Driver only issues DPCD transactions and leaves USB4 tunneling (SET_CONFIG) messages to DPIA.
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* - Driver writes TPS1 to DPCD to kick off training.
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* - Clock recovery (CR) for link is handled by DPOA, which reports result to DPIA on completion.
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* - DPIA communicates result to driver by updating CR status when driver reads DPCD.
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*
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* @param link DPIA link being trained.
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* @param lt_settings link_setting and drive settings (voltage swing and pre-emphasis).
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*/
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static enum link_training_result dpia_training_cr_transparent(struct dc_link *link,
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struct link_training_settings *lt_settings)
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{
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enum link_training_result result = LINK_TRAINING_CR_FAIL_LANE0;
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enum dc_status status;
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uint32_t retries_cr = 0; /* Number of consecutive attempts with same VS or PE. */
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uint32_t retry_count = 0;
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uint32_t wait_time_microsec = lt_settings->cr_pattern_time;
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struct link_training_settings req_settings;
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enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
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union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } };
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union lane_align_status_updated dpcd_lane_status_updated = { {0} };
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/* Cap of LINK_TRAINING_MAX_CR_RETRY attempts at clock recovery.
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* Fix inherited from perform_clock_recovery_sequence() -
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* the DP equivalent of this function:
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* Required for Synaptics MST hub which can put the LT in
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* infinite loop by switching the VS between level 0 and level 1
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* continuously.
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*/
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while ((retries_cr < LINK_TRAINING_MAX_RETRY_COUNT) &&
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(retry_count < LINK_TRAINING_MAX_CR_RETRY)) {
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/* Write TPS1 (not VS or PE) to DPCD to start CR phase.
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* DPIA sends SET_CONFIG(SET_LINK) to notify DPOA to
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* start link training.
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*/
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if (retry_count == 0) {
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status = dpcd_set_lt_pattern(link, lt_settings->pattern_for_cr, DPRX);
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if (status != DC_OK) {
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result = LINK_TRAINING_ABORT;
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break;
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}
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}
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dp_wait_for_training_aux_rd_interval(link, wait_time_microsec);
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/* Read status and adjustment requests from DPCD. */
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status = dp_get_lane_status_and_drive_settings(link,
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lt_settings,
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dpcd_lane_status,
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&dpcd_lane_status_updated,
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&req_settings,
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DPRX);
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if (status != DC_OK) {
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result = LINK_TRAINING_ABORT;
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break;
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}
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/* Check if clock recovery successful. */
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if (dp_is_cr_done(lane_count, dpcd_lane_status)) {
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result = LINK_TRAINING_SUCCESS;
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break;
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}
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result = dp_get_cr_failure(lane_count, dpcd_lane_status);
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if (dp_is_max_vs_reached(lt_settings))
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break;
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||||||
|
/* Count number of attempts with same drive settings.
|
||||||
|
* Note: settings are the same for all lanes,
|
||||||
|
* so comparing first lane is sufficient.
|
||||||
|
*/
|
||||||
|
if (lt_settings->lane_settings[0].VOLTAGE_SWING ==
|
||||||
|
req_settings.lane_settings[0].VOLTAGE_SWING &&
|
||||||
|
lt_settings->lane_settings[0].PRE_EMPHASIS ==
|
||||||
|
req_settings.lane_settings[0].PRE_EMPHASIS)
|
||||||
|
retries_cr++;
|
||||||
|
else
|
||||||
|
retries_cr = 0;
|
||||||
|
|
||||||
|
/* Update VS/PE. */
|
||||||
|
dp_update_drive_settings(lt_settings, req_settings);
|
||||||
|
retry_count++;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Abort link training if clock recovery failed due to HPD unplug. */
|
||||||
|
if (!link->hpd_status)
|
||||||
|
result = LINK_TRAINING_ABORT;
|
||||||
|
|
||||||
|
DC_LOG_HW_LINK_TRAINING("%s\n DPIA(%d) clock recovery\n"
|
||||||
|
" -hop(%d)\n - result(%d)\n - retries(%d)\n",
|
||||||
|
__func__,
|
||||||
|
link->link_id.enum_id - ENUM_ID_1,
|
||||||
|
DPRX,
|
||||||
|
result,
|
||||||
|
retry_count);
|
||||||
|
|
||||||
|
return result;
|
||||||
|
}
|
||||||
|
|
||||||
/* Execute clock recovery phase of link training for specified hop in display
|
/* Execute clock recovery phase of link training for specified hop in display
|
||||||
* path.
|
* path.
|
||||||
|
*
|
||||||
|
* @param link DPIA link being trained.
|
||||||
|
* @param lt_settings link_setting and drive settings (voltage swing and pre-emphasis).
|
||||||
|
* @param hop The Hop in display path. DPRX = 0.
|
||||||
*/
|
*/
|
||||||
static enum link_training_result dpia_training_cr_phase(struct dc_link *link,
|
static enum link_training_result dpia_training_cr_phase(struct dc_link *link,
|
||||||
struct link_training_settings *lt_settings,
|
struct link_training_settings *lt_settings,
|
||||||
uint32_t hop)
|
uint32_t hop)
|
||||||
{
|
{
|
||||||
enum link_training_result result;
|
enum link_training_result result = LINK_TRAINING_CR_FAIL_LANE0;
|
||||||
|
|
||||||
/** @todo Fail until implemented. */
|
if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT)
|
||||||
result = LINK_TRAINING_ABORT;
|
result = dpia_training_cr_non_transparent(link, lt_settings, hop);
|
||||||
|
else
|
||||||
|
result = dpia_training_cr_transparent(link, lt_settings);
|
||||||
|
|
||||||
return result;
|
return result;
|
||||||
}
|
}
|
||||||
@ -130,6 +505,38 @@ static enum link_training_result dpia_training_end(struct dc_link *link,
|
|||||||
return result;
|
return result;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/* When aborting training of specified hop in display path, clean up by:
|
||||||
|
* - Attempting to clear DPCD TRAINING_PATTERN_SET, LINK_BW_SET and LANE_COUNT_SET.
|
||||||
|
* - Sending SET_CONFIG(SET_LINK) with lane count and link rate set to 0.
|
||||||
|
*
|
||||||
|
* @param link DPIA link being trained.
|
||||||
|
* @param hop The Hop in display path. DPRX = 0.
|
||||||
|
*/
|
||||||
|
static void dpia_training_abort(struct dc_link *link, uint32_t hop)
|
||||||
|
{
|
||||||
|
uint8_t data = 0;
|
||||||
|
uint32_t dpcd_tps_offset = DP_TRAINING_PATTERN_SET;
|
||||||
|
|
||||||
|
DC_LOG_HW_LINK_TRAINING("%s\n DPIA(%d) aborting\n - LTTPR mode(%d)\n - HPD(%d)\n",
|
||||||
|
__func__,
|
||||||
|
link->link_id.enum_id - ENUM_ID_1,
|
||||||
|
link->lttpr_mode,
|
||||||
|
link->hpd_status);
|
||||||
|
|
||||||
|
/* Abandon clean-up if sink unplugged. */
|
||||||
|
if (!link->hpd_status)
|
||||||
|
return;
|
||||||
|
|
||||||
|
if (hop != DPRX)
|
||||||
|
dpcd_tps_offset = DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
|
||||||
|
((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (hop - 1));
|
||||||
|
|
||||||
|
core_link_write_dpcd(link, dpcd_tps_offset, &data, 1);
|
||||||
|
core_link_write_dpcd(link, DP_LINK_BW_SET, &data, 1);
|
||||||
|
core_link_write_dpcd(link, DP_LANE_COUNT_SET, &data, 1);
|
||||||
|
core_link_send_set_config(link, DPIA_SET_CFG_SET_LINK, data);
|
||||||
|
}
|
||||||
|
|
||||||
enum link_training_result dc_link_dpia_perform_link_training(struct dc_link *link,
|
enum link_training_result dc_link_dpia_perform_link_training(struct dc_link *link,
|
||||||
const struct dc_link_settings *link_setting,
|
const struct dc_link_settings *link_setting,
|
||||||
bool skip_video_pattern)
|
bool skip_video_pattern)
|
||||||
@ -167,14 +574,17 @@ enum link_training_result dc_link_dpia_perform_link_training(struct dc_link *lin
|
|||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Double-check link status if training successful; gracefully stop
|
/* Double-check link status if training successful; gracefully abort
|
||||||
* training of current hop if training failed for any reason other than
|
* training of current hop if training failed due to message tunneling
|
||||||
* sink unplug.
|
* failure; end training of hop if training ended conventionally and
|
||||||
|
* falling back to lower bandwidth settings possible.
|
||||||
*/
|
*/
|
||||||
if (result == LINK_TRAINING_SUCCESS) {
|
if (result == LINK_TRAINING_SUCCESS) {
|
||||||
msleep(5);
|
msleep(5);
|
||||||
result = dp_check_link_loss_status(link, <_settings);
|
result = dp_check_link_loss_status(link, <_settings);
|
||||||
} else if (result != LINK_TRAINING_ABORT) {
|
} else if (result == LINK_TRAINING_ABORT) {
|
||||||
|
dpia_training_abort(link, repeater_id);
|
||||||
|
} else {
|
||||||
dpia_training_end(link, repeater_id);
|
dpia_training_end(link, repeater_id);
|
||||||
}
|
}
|
||||||
return result;
|
return result;
|
||||||
|
|||||||
@ -32,6 +32,46 @@
|
|||||||
struct dc_link;
|
struct dc_link;
|
||||||
struct dc_link_settings;
|
struct dc_link_settings;
|
||||||
|
|
||||||
|
/* The approximate time (us) it takes to transmit 9 USB4 DP clock sync packets. */
|
||||||
|
#define DPIA_CLK_SYNC_DELAY 16000
|
||||||
|
|
||||||
|
/* SET_CONFIG message types sent by driver. */
|
||||||
|
enum dpia_set_config_type {
|
||||||
|
DPIA_SET_CFG_SET_LINK = 0x01,
|
||||||
|
DPIA_SET_CFG_SET_PHY_TEST_MODE = 0x05,
|
||||||
|
DPIA_SET_CFG_SET_TRAINING = 0x18,
|
||||||
|
DPIA_SET_CFG_SET_VSPE = 0x19
|
||||||
|
};
|
||||||
|
|
||||||
|
/* Training stages (TS) in SET_CONFIG(SET_TRAINING) message. */
|
||||||
|
enum dpia_set_config_ts {
|
||||||
|
DPIA_TS_DPRX_DONE = 0x00, /* Done training DPRX. */
|
||||||
|
DPIA_TS_TPS1 = 0x01,
|
||||||
|
DPIA_TS_TPS2 = 0x02,
|
||||||
|
DPIA_TS_TPS3 = 0x03,
|
||||||
|
DPIA_TS_TPS4 = 0x07,
|
||||||
|
DPIA_TS_UFP_DONE = 0xff /* Done training DPTX-to-DPIA hop. */
|
||||||
|
};
|
||||||
|
|
||||||
|
/* SET_CONFIG message data associated with messages sent by driver. */
|
||||||
|
union dpia_set_config_data {
|
||||||
|
struct {
|
||||||
|
uint8_t mode : 1;
|
||||||
|
uint8_t reserved : 7;
|
||||||
|
} set_link;
|
||||||
|
struct {
|
||||||
|
uint8_t stage;
|
||||||
|
} set_training;
|
||||||
|
struct {
|
||||||
|
uint8_t swing : 2;
|
||||||
|
uint8_t max_swing_reached : 1;
|
||||||
|
uint8_t pre_emph : 2;
|
||||||
|
uint8_t max_pre_emph_reached : 1;
|
||||||
|
uint8_t reserved : 2;
|
||||||
|
} set_vspe;
|
||||||
|
uint8_t raw;
|
||||||
|
};
|
||||||
|
|
||||||
/* Read tunneling device capability from DPCD and update link capability
|
/* Read tunneling device capability from DPCD and update link capability
|
||||||
* accordingly.
|
* accordingly.
|
||||||
*/
|
*/
|
||||||
|
|||||||
Loading…
x
Reference in New Issue
Block a user