fbdev: sh_mipi_dsi: remove driver
Remove the sh_mipi_dsi driver as it appears to be unused since
c0bb9b3027 ("ARCH: ARM: shmobile: Remove ag5evm board support").
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
This commit is contained in:
Simon Horman
Tomi Valkeinen
parent
cc6df3a245
commit
18b6562c24
@ -8,10 +8,6 @@ menu "Graphics support"
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config HAVE_FB_ATMEL
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bool
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config SH_MIPI_DSI
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tristate
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depends on (SUPERH || ARCH_SHMOBILE) && HAVE_CLK
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config SH_LCD_MIPI_DSI
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bool
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@ -1993,7 +1993,6 @@ config FB_SH_MOBILE_LCDC
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select FB_SYS_FOPS
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select FB_DEFERRED_IO
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select FB_BACKLIGHT
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select SH_MIPI_DSI if SH_LCD_MIPI_DSI
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---help---
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Frame buffer driver for the on-chip SH-Mobile LCD controller.
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@ -117,7 +117,6 @@ obj-$(CONFIG_FB_SM501) += sm501fb.o
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obj-$(CONFIG_FB_UDL) += udlfb.o
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obj-$(CONFIG_FB_SMSCUFX) += smscufx.o
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obj-$(CONFIG_FB_XILINX) += xilinxfb.o
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obj-$(CONFIG_SH_MIPI_DSI) += sh_mipi_dsi.o
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obj-$(CONFIG_FB_SH_MOBILE_MERAM) += sh_mobile_meram.o
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obj-$(CONFIG_FB_SH_MOBILE_LCDC) += sh_mobile_lcdcfb.o
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obj-$(CONFIG_FB_OMAP) += omap/
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@ -1,587 +0,0 @@
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/*
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* Renesas SH-mobile MIPI DSI support
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*
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* Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
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*
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* This is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*/
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#include <linux/bitmap.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/slab.h>
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#include <linux/string.h>
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#include <linux/types.h>
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#include <linux/module.h>
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#include <video/mipi_display.h>
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#include <video/sh_mipi_dsi.h>
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#include <video/sh_mobile_lcdc.h>
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#include "sh_mobile_lcdcfb.h"
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#define SYSCTRL 0x0000
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#define SYSCONF 0x0004
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#define TIMSET 0x0008
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#define RESREQSET0 0x0018
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#define RESREQSET1 0x001c
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#define HSTTOVSET 0x0020
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#define LPRTOVSET 0x0024
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#define TATOVSET 0x0028
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#define PRTOVSET 0x002c
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#define DSICTRL 0x0030
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#define DSIINTE 0x0060
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#define PHYCTRL 0x0070
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/* relative to linkbase */
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#define DTCTR 0x0000
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#define VMCTR1 0x0020
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#define VMCTR2 0x0024
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#define VMLEN1 0x0028
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#define VMLEN2 0x002c
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#define CMTSRTREQ 0x0070
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#define CMTSRTCTR 0x00d0
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/* E.g., sh7372 has 2 MIPI-DSIs - one for each LCDC */
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#define MAX_SH_MIPI_DSI 2
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struct sh_mipi {
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struct sh_mobile_lcdc_entity entity;
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void __iomem *base;
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void __iomem *linkbase;
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struct clk *dsit_clk;
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struct platform_device *pdev;
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};
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#define to_sh_mipi(e) container_of(e, struct sh_mipi, entity)
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static struct sh_mipi *mipi_dsi[MAX_SH_MIPI_DSI];
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/* Protect the above array */
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static DEFINE_MUTEX(array_lock);
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static struct sh_mipi *sh_mipi_by_handle(int handle)
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{
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if (handle >= ARRAY_SIZE(mipi_dsi) || handle < 0)
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return NULL;
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return mipi_dsi[handle];
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}
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static int sh_mipi_send_short(struct sh_mipi *mipi, u8 dsi_cmd,
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u8 cmd, u8 param)
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{
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u32 data = (dsi_cmd << 24) | (cmd << 16) | (param << 8);
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int cnt = 100;
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/* transmit a short packet to LCD panel */
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iowrite32(1 | data, mipi->linkbase + CMTSRTCTR);
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iowrite32(1, mipi->linkbase + CMTSRTREQ);
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while ((ioread32(mipi->linkbase + CMTSRTREQ) & 1) && --cnt)
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udelay(1);
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return cnt ? 0 : -ETIMEDOUT;
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}
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#define LCD_CHAN2MIPI(c) ((c) < LCDC_CHAN_MAINLCD || (c) > LCDC_CHAN_SUBLCD ? \
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-EINVAL : (c) - 1)
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static int sh_mipi_dcs(int handle, u8 cmd)
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{
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struct sh_mipi *mipi = sh_mipi_by_handle(LCD_CHAN2MIPI(handle));
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if (!mipi)
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return -ENODEV;
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return sh_mipi_send_short(mipi, MIPI_DSI_DCS_SHORT_WRITE, cmd, 0);
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}
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static int sh_mipi_dcs_param(int handle, u8 cmd, u8 param)
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{
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struct sh_mipi *mipi = sh_mipi_by_handle(LCD_CHAN2MIPI(handle));
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if (!mipi)
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return -ENODEV;
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return sh_mipi_send_short(mipi, MIPI_DSI_DCS_SHORT_WRITE_PARAM, cmd,
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param);
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}
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static void sh_mipi_dsi_enable(struct sh_mipi *mipi, bool enable)
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{
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/*
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* enable LCDC data tx, transition to LPS after completion of each HS
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* packet
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*/
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iowrite32(0x00000002 | enable, mipi->linkbase + DTCTR);
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}
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static void sh_mipi_shutdown(struct platform_device *pdev)
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{
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struct sh_mipi *mipi = to_sh_mipi(platform_get_drvdata(pdev));
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sh_mipi_dsi_enable(mipi, false);
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}
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static int sh_mipi_setup(struct sh_mipi *mipi, const struct fb_videomode *mode)
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{
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void __iomem *base = mipi->base;
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struct sh_mipi_dsi_info *pdata = mipi->pdev->dev.platform_data;
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u32 pctype, datatype, pixfmt, linelength, vmctr2;
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u32 tmp, top, bottom, delay, div;
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int bpp;
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/*
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* Select data format. MIPI DSI is not hot-pluggable, so, we just use
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* the default videomode. If this ever becomes a problem, We'll have to
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* move this to mipi_display_on() above and use info->var.xres
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*/
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switch (pdata->data_format) {
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case MIPI_RGB888:
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pctype = 0;
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datatype = MIPI_DSI_PACKED_PIXEL_STREAM_24;
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pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
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linelength = mode->xres * 3;
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break;
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case MIPI_RGB565:
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pctype = 1;
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datatype = MIPI_DSI_PACKED_PIXEL_STREAM_16;
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pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
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linelength = mode->xres * 2;
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break;
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case MIPI_RGB666_LP:
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pctype = 2;
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datatype = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
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pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
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linelength = mode->xres * 3;
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break;
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case MIPI_RGB666:
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pctype = 3;
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datatype = MIPI_DSI_PACKED_PIXEL_STREAM_18;
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pixfmt = MIPI_DCS_PIXEL_FMT_18BIT;
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linelength = (mode->xres * 18 + 7) / 8;
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break;
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case MIPI_BGR888:
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pctype = 8;
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datatype = MIPI_DSI_PACKED_PIXEL_STREAM_24;
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pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
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linelength = mode->xres * 3;
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break;
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case MIPI_BGR565:
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pctype = 9;
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datatype = MIPI_DSI_PACKED_PIXEL_STREAM_16;
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pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
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linelength = mode->xres * 2;
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break;
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case MIPI_BGR666_LP:
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pctype = 0xa;
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datatype = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
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pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
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linelength = mode->xres * 3;
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break;
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case MIPI_BGR666:
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pctype = 0xb;
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datatype = MIPI_DSI_PACKED_PIXEL_STREAM_18;
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pixfmt = MIPI_DCS_PIXEL_FMT_18BIT;
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linelength = (mode->xres * 18 + 7) / 8;
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break;
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case MIPI_YUYV:
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pctype = 4;
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datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16;
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pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
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linelength = mode->xres * 2;
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break;
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case MIPI_UYVY:
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pctype = 5;
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datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16;
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pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
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linelength = mode->xres * 2;
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break;
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case MIPI_YUV420_L:
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pctype = 6;
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datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12;
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pixfmt = MIPI_DCS_PIXEL_FMT_12BIT;
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linelength = (mode->xres * 12 + 7) / 8;
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break;
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case MIPI_YUV420:
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pctype = 7;
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datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12;
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pixfmt = MIPI_DCS_PIXEL_FMT_12BIT;
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/* Length of U/V line */
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linelength = (mode->xres + 1) / 2;
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break;
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default:
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return -EINVAL;
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}
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if (!pdata->lane)
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return -EINVAL;
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/* reset DSI link */
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iowrite32(0x00000001, base + SYSCTRL);
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/* Hold reset for 100 cycles of the slowest of bus, HS byte and LP clock */
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udelay(50);
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iowrite32(0x00000000, base + SYSCTRL);
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/* setup DSI link */
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/*
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* T_wakeup = 0x7000
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* T_hs-trail = 3
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* T_hs-prepare = 3
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* T_clk-trail = 3
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* T_clk-prepare = 2
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*/
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iowrite32(0x70003332, base + TIMSET);
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/* no responses requested */
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iowrite32(0x00000000, base + RESREQSET0);
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/* request response to packets of type 0x28 */
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iowrite32(0x00000100, base + RESREQSET1);
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/* High-speed transmission timeout, default 0xffffffff */
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iowrite32(0x0fffffff, base + HSTTOVSET);
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/* LP reception timeout, default 0xffffffff */
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iowrite32(0x0fffffff, base + LPRTOVSET);
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/* Turn-around timeout, default 0xffffffff */
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iowrite32(0x0fffffff, base + TATOVSET);
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/* Peripheral reset timeout, default 0xffffffff */
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iowrite32(0x0fffffff, base + PRTOVSET);
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/* Interrupts not used, disable all */
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iowrite32(0, base + DSIINTE);
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/* DSI-Tx bias on */
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iowrite32(0x00000001, base + PHYCTRL);
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udelay(200);
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/* Deassert resets, power on */
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iowrite32(0x03070001 | pdata->phyctrl, base + PHYCTRL);
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/*
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* Default = ULPS enable |
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* Contention detection enabled |
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* EoT packet transmission enable |
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* CRC check enable |
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* ECC check enable
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*/
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bitmap_fill((unsigned long *)&tmp, pdata->lane);
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tmp |= 0x00003700;
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iowrite32(tmp, base + SYSCONF);
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/* setup l-bridge */
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/*
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* Enable transmission of all packets,
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* transmit LPS after each HS packet completion
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*/
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iowrite32(0x00000006, mipi->linkbase + DTCTR);
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/* VSYNC width = 2 (<< 17) */
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iowrite32((mode->vsync_len << pdata->vsynw_offset) |
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(pdata->clksrc << 16) | (pctype << 12) | datatype,
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mipi->linkbase + VMCTR1);
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/*
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* Non-burst mode with sync pulses: VSE and HSE are output,
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* HSA period allowed, no commands in LP
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*/
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vmctr2 = 0;
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if (pdata->flags & SH_MIPI_DSI_VSEE)
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vmctr2 |= 1 << 23;
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if (pdata->flags & SH_MIPI_DSI_HSEE)
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vmctr2 |= 1 << 22;
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if (pdata->flags & SH_MIPI_DSI_HSAE)
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vmctr2 |= 1 << 21;
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if (pdata->flags & SH_MIPI_DSI_BL2E)
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vmctr2 |= 1 << 17;
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if (pdata->flags & SH_MIPI_DSI_HSABM)
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vmctr2 |= 1 << 5;
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if (pdata->flags & SH_MIPI_DSI_HBPBM)
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vmctr2 |= 1 << 4;
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if (pdata->flags & SH_MIPI_DSI_HFPBM)
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vmctr2 |= 1 << 3;
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iowrite32(vmctr2, mipi->linkbase + VMCTR2);
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/*
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* VMLEN1 = RGBLEN | HSALEN
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*
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* see
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* Video mode - Blanking Packet setting
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*/
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top = linelength << 16; /* RGBLEN */
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bottom = 0x00000001;
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if (pdata->flags & SH_MIPI_DSI_HSABM) /* HSALEN */
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bottom = (pdata->lane * mode->hsync_len) - 10;
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iowrite32(top | bottom , mipi->linkbase + VMLEN1);
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/*
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* VMLEN2 = HBPLEN | HFPLEN
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*
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* see
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* Video mode - Blanking Packet setting
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*/
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top = 0x00010000;
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bottom = 0x00000001;
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delay = 0;
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div = 1; /* HSbyteCLK is calculation base
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* HS4divCLK = HSbyteCLK/2
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* HS6divCLK is not supported for now */
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if (pdata->flags & SH_MIPI_DSI_HS4divCLK)
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div = 2;
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if (pdata->flags & SH_MIPI_DSI_HFPBM) { /* HBPLEN */
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top = mode->hsync_len + mode->left_margin;
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top = ((pdata->lane * top / div) - 10) << 16;
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}
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if (pdata->flags & SH_MIPI_DSI_HBPBM) { /* HFPLEN */
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bottom = mode->right_margin;
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bottom = (pdata->lane * bottom / div) - 12;
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}
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bpp = linelength / mode->xres; /* byte / pixel */
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if ((pdata->lane / div) > bpp) {
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tmp = mode->xres / bpp; /* output cycle */
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tmp = mode->xres - tmp; /* (input - output) cycle */
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delay = (pdata->lane * tmp);
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}
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iowrite32(top | (bottom + delay) , mipi->linkbase + VMLEN2);
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msleep(5);
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/* setup LCD panel */
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/* cf. drivers/video/omap/lcd_mipid.c */
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sh_mipi_dcs(pdata->channel, MIPI_DCS_EXIT_SLEEP_MODE);
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msleep(120);
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/*
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* [7] - Page Address Mode
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* [6] - Column Address Mode
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* [5] - Page / Column Address Mode
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* [4] - Display Device Line Refresh Order
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* [3] - RGB/BGR Order
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* [2] - Display Data Latch Data Order
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* [1] - Flip Horizontal
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* [0] - Flip Vertical
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*/
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sh_mipi_dcs_param(pdata->channel, MIPI_DCS_SET_ADDRESS_MODE, 0x00);
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/* cf. set_data_lines() */
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sh_mipi_dcs_param(pdata->channel, MIPI_DCS_SET_PIXEL_FORMAT,
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pixfmt << 4);
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sh_mipi_dcs(pdata->channel, MIPI_DCS_SET_DISPLAY_ON);
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/* Enable timeout counters */
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iowrite32(0x00000f00, base + DSICTRL);
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return 0;
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}
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static int mipi_display_on(struct sh_mobile_lcdc_entity *entity)
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{
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struct sh_mipi *mipi = to_sh_mipi(entity);
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struct sh_mipi_dsi_info *pdata = mipi->pdev->dev.platform_data;
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int ret;
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pm_runtime_get_sync(&mipi->pdev->dev);
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ret = pdata->set_dot_clock(mipi->pdev, mipi->base, 1);
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if (ret < 0)
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goto mipi_display_on_fail1;
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ret = sh_mipi_setup(mipi, &entity->def_mode);
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if (ret < 0)
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goto mipi_display_on_fail2;
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sh_mipi_dsi_enable(mipi, true);
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|
||||
return SH_MOBILE_LCDC_DISPLAY_CONNECTED;
|
||||
|
||||
mipi_display_on_fail1:
|
||||
pm_runtime_put_sync(&mipi->pdev->dev);
|
||||
mipi_display_on_fail2:
|
||||
pdata->set_dot_clock(mipi->pdev, mipi->base, 0);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void mipi_display_off(struct sh_mobile_lcdc_entity *entity)
|
||||
{
|
||||
struct sh_mipi *mipi = to_sh_mipi(entity);
|
||||
struct sh_mipi_dsi_info *pdata = mipi->pdev->dev.platform_data;
|
||||
|
||||
sh_mipi_dsi_enable(mipi, false);
|
||||
|
||||
pdata->set_dot_clock(mipi->pdev, mipi->base, 0);
|
||||
|
||||
pm_runtime_put_sync(&mipi->pdev->dev);
|
||||
}
|
||||
|
||||
static const struct sh_mobile_lcdc_entity_ops mipi_ops = {
|
||||
.display_on = mipi_display_on,
|
||||
.display_off = mipi_display_off,
|
||||
};
|
||||
|
||||
static int __init sh_mipi_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct sh_mipi *mipi;
|
||||
struct sh_mipi_dsi_info *pdata = pdev->dev.platform_data;
|
||||
struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
struct resource *res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
||||
unsigned long rate, f_current;
|
||||
int idx = pdev->id, ret;
|
||||
|
||||
if (!res || !res2 || idx >= ARRAY_SIZE(mipi_dsi) || !pdata)
|
||||
return -ENODEV;
|
||||
|
||||
if (!pdata->set_dot_clock)
|
||||
return -EINVAL;
|
||||
|
||||
mutex_lock(&array_lock);
|
||||
if (idx < 0)
|
||||
for (idx = 0; idx < ARRAY_SIZE(mipi_dsi) && mipi_dsi[idx]; idx++)
|
||||
;
|
||||
|
||||
if (idx == ARRAY_SIZE(mipi_dsi)) {
|
||||
ret = -EBUSY;
|
||||
goto efindslot;
|
||||
}
|
||||
|
||||
mipi = kzalloc(sizeof(*mipi), GFP_KERNEL);
|
||||
if (!mipi) {
|
||||
ret = -ENOMEM;
|
||||
goto ealloc;
|
||||
}
|
||||
|
||||
mipi->entity.owner = THIS_MODULE;
|
||||
mipi->entity.ops = &mipi_ops;
|
||||
|
||||
if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
|
||||
dev_err(&pdev->dev, "MIPI register region already claimed\n");
|
||||
ret = -EBUSY;
|
||||
goto ereqreg;
|
||||
}
|
||||
|
||||
mipi->base = ioremap(res->start, resource_size(res));
|
||||
if (!mipi->base) {
|
||||
ret = -ENOMEM;
|
||||
goto emap;
|
||||
}
|
||||
|
||||
if (!request_mem_region(res2->start, resource_size(res2), pdev->name)) {
|
||||
dev_err(&pdev->dev, "MIPI register region 2 already claimed\n");
|
||||
ret = -EBUSY;
|
||||
goto ereqreg2;
|
||||
}
|
||||
|
||||
mipi->linkbase = ioremap(res2->start, resource_size(res2));
|
||||
if (!mipi->linkbase) {
|
||||
ret = -ENOMEM;
|
||||
goto emap2;
|
||||
}
|
||||
|
||||
mipi->pdev = pdev;
|
||||
|
||||
mipi->dsit_clk = clk_get(&pdev->dev, "dsit_clk");
|
||||
if (IS_ERR(mipi->dsit_clk)) {
|
||||
ret = PTR_ERR(mipi->dsit_clk);
|
||||
goto eclktget;
|
||||
}
|
||||
|
||||
f_current = clk_get_rate(mipi->dsit_clk);
|
||||
/* 80MHz required by the datasheet */
|
||||
rate = clk_round_rate(mipi->dsit_clk, 80000000);
|
||||
if (rate > 0 && rate != f_current)
|
||||
ret = clk_set_rate(mipi->dsit_clk, rate);
|
||||
else
|
||||
ret = rate;
|
||||
if (ret < 0)
|
||||
goto esettrate;
|
||||
|
||||
dev_dbg(&pdev->dev, "DSI-T clk %lu -> %lu\n", f_current, rate);
|
||||
|
||||
ret = clk_enable(mipi->dsit_clk);
|
||||
if (ret < 0)
|
||||
goto eclkton;
|
||||
|
||||
mipi_dsi[idx] = mipi;
|
||||
|
||||
pm_runtime_enable(&pdev->dev);
|
||||
pm_runtime_resume(&pdev->dev);
|
||||
|
||||
mutex_unlock(&array_lock);
|
||||
platform_set_drvdata(pdev, &mipi->entity);
|
||||
|
||||
return 0;
|
||||
|
||||
eclkton:
|
||||
esettrate:
|
||||
clk_put(mipi->dsit_clk);
|
||||
eclktget:
|
||||
iounmap(mipi->linkbase);
|
||||
emap2:
|
||||
release_mem_region(res2->start, resource_size(res2));
|
||||
ereqreg2:
|
||||
iounmap(mipi->base);
|
||||
emap:
|
||||
release_mem_region(res->start, resource_size(res));
|
||||
ereqreg:
|
||||
kfree(mipi);
|
||||
ealloc:
|
||||
efindslot:
|
||||
mutex_unlock(&array_lock);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int sh_mipi_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
struct resource *res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
||||
struct sh_mipi *mipi = to_sh_mipi(platform_get_drvdata(pdev));
|
||||
int i, ret;
|
||||
|
||||
mutex_lock(&array_lock);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(mipi_dsi) && mipi_dsi[i] != mipi; i++)
|
||||
;
|
||||
|
||||
if (i == ARRAY_SIZE(mipi_dsi)) {
|
||||
ret = -EINVAL;
|
||||
} else {
|
||||
ret = 0;
|
||||
mipi_dsi[i] = NULL;
|
||||
}
|
||||
|
||||
mutex_unlock(&array_lock);
|
||||
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
clk_disable(mipi->dsit_clk);
|
||||
clk_put(mipi->dsit_clk);
|
||||
|
||||
iounmap(mipi->linkbase);
|
||||
if (res2)
|
||||
release_mem_region(res2->start, resource_size(res2));
|
||||
iounmap(mipi->base);
|
||||
if (res)
|
||||
release_mem_region(res->start, resource_size(res));
|
||||
kfree(mipi);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver sh_mipi_driver = {
|
||||
.remove = sh_mipi_remove,
|
||||
.shutdown = sh_mipi_shutdown,
|
||||
.driver = {
|
||||
.name = "sh-mipi-dsi",
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver_probe(sh_mipi_driver, sh_mipi_probe);
|
||||
|
||||
MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
|
||||
MODULE_DESCRIPTION("SuperH / ARM-shmobile MIPI DSI driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
@ -1,59 +0,0 @@
|
||||
/*
|
||||
* Public SH-mobile MIPI DSI header
|
||||
*
|
||||
* Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#ifndef VIDEO_SH_MIPI_DSI_H
|
||||
#define VIDEO_SH_MIPI_DSI_H
|
||||
|
||||
enum sh_mipi_dsi_data_fmt {
|
||||
MIPI_RGB888,
|
||||
MIPI_RGB565,
|
||||
MIPI_RGB666_LP,
|
||||
MIPI_RGB666,
|
||||
MIPI_BGR888,
|
||||
MIPI_BGR565,
|
||||
MIPI_BGR666_LP,
|
||||
MIPI_BGR666,
|
||||
MIPI_YUYV,
|
||||
MIPI_UYVY,
|
||||
MIPI_YUV420_L,
|
||||
MIPI_YUV420,
|
||||
};
|
||||
|
||||
#define SH_MIPI_DSI_HSABM (1 << 0)
|
||||
#define SH_MIPI_DSI_HBPBM (1 << 1)
|
||||
#define SH_MIPI_DSI_HFPBM (1 << 2)
|
||||
#define SH_MIPI_DSI_BL2E (1 << 3)
|
||||
#define SH_MIPI_DSI_VSEE (1 << 4)
|
||||
#define SH_MIPI_DSI_HSEE (1 << 5)
|
||||
#define SH_MIPI_DSI_HSAE (1 << 6)
|
||||
|
||||
#define SH_MIPI_DSI_HSbyteCLK (1 << 24)
|
||||
#define SH_MIPI_DSI_HS6divCLK (1 << 25)
|
||||
#define SH_MIPI_DSI_HS4divCLK (1 << 26)
|
||||
|
||||
#define SH_MIPI_DSI_SYNC_PULSES_MODE (SH_MIPI_DSI_VSEE | \
|
||||
SH_MIPI_DSI_HSEE | \
|
||||
SH_MIPI_DSI_HSAE)
|
||||
#define SH_MIPI_DSI_SYNC_EVENTS_MODE (0)
|
||||
#define SH_MIPI_DSI_SYNC_BURST_MODE (SH_MIPI_DSI_BL2E)
|
||||
|
||||
struct sh_mipi_dsi_info {
|
||||
enum sh_mipi_dsi_data_fmt data_format;
|
||||
int channel;
|
||||
int lane;
|
||||
unsigned long flags;
|
||||
u32 clksrc;
|
||||
u32 phyctrl; /* for extra setting */
|
||||
unsigned int vsynw_offset;
|
||||
int (*set_dot_clock)(struct platform_device *pdev,
|
||||
void __iomem *base,
|
||||
int enable);
|
||||
};
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user