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arm64: sysreg: Generate C compiler warnings on {read,write}_sysreg_s arguments

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Evaluate the register before the asm section so that the C compiler
generates warnings when there is an issue with the register argument.

This will prevent possible future issues such as the one seen here [1]
where a missing bracket caused the shift and addition operators to be
evaluated in the wrong order, but no warning was emitted. The GNU
assembler has no warning for when expressions evaluate differently to C
due to different operator precedence, but the C compiler has some
warnings that may suggest something is wrong. For example in this case
the following warning would have been emitted:

  error: operator '>>' has lower precedence than '+'; '+' will be evaluated first [-Werror,-Wshift-op-parentheses]

There are currently no existing warnings that need to be fixed.

[1]: https://lore.kernel.org/linux-perf-users/20230728162011.GA22050@willie-the-truck/

Signed-off-by: James Clark <james.clark@arm.com>
Link: https://lore.kernel.org/r/20230815140639.614769-1-james.clark@arm.com
Signed-off-by: Will Deacon <will@kernel.org>
This commit is contained in:
James Clark 2023-08-15 15:06:39 +01:00 committed by Will Deacon
parent 5cd474e573
commit 18b8f57a7f
1 changed files with 6 additions and 0 deletions
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6
arch/arm64/include/asm/sysreg.h
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@ -803,15 +803,21 @@
/*
* For registers without architectural names, or simply unsupported by
* GAS.
*
* __check_r forces warnings to be generated by the compiler when
* evaluating r which wouldn't normally happen due to being passed to
* the assembler via __stringify(r).
*/
#define read_sysreg_s(r) ({ \
u64 __val; \
u32 __maybe_unused __check_r = (u32)(r); \
asm volatile(__mrs_s("%0", r) : "=r" (__val)); \
__val; \
})
#define write_sysreg_s(v, r) do { \
u64 __val = (u64)(v); \
u32 __maybe_unused __check_r = (u32)(r); \
asm volatile(__msr_s(r, "%x0") : : "rZ" (__val)); \
} while (0)