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igb: remove redundant PHY power down register write

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One of the registers used to power down the PHY was found to be wrong
(should be bit 2 not bit 1) on further inspection it was also found to
be redundant.

Signed-off-by: Todd Fujinaka <todd.fujinaka@intel.com>
Tested-by: Aaron Brown <aaron.f.brown@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
This commit is contained in:
Todd Fujinaka 2014-05-08 23:20:24 +00:00 committed by Jeff Kirsher
parent c6f3148c5b
commit 18cae6f7bb
2 changed files with 0 additions and 15 deletions
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14
drivers/net/ethernet/intel/igb/e1000_phy.c
View File

@ -2204,16 +2204,10 @@ s32 igb_phy_init_script_igp3(struct e1000_hw *hw)
void igb_power_up_phy_copper(struct e1000_hw *hw) void igb_power_up_phy_copper(struct e1000_hw *hw)
{ {
u16 mii_reg = 0; u16 mii_reg = 0;
u16 power_reg = 0;
/* The PHY will retain its settings across a power down/up cycle */ /* The PHY will retain its settings across a power down/up cycle */
hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
mii_reg &= ~MII_CR_POWER_DOWN; mii_reg &= ~MII_CR_POWER_DOWN;
if (hw->phy.type == e1000_phy_i210) {
hw->phy.ops.read_reg(hw, GS40G_COPPER_SPEC, &power_reg);
power_reg &= ~GS40G_CS_POWER_DOWN;
hw->phy.ops.write_reg(hw, GS40G_COPPER_SPEC, power_reg);
}
hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
} }
@ -2227,18 +2221,10 @@ void igb_power_up_phy_copper(struct e1000_hw *hw)
void igb_power_down_phy_copper(struct e1000_hw *hw) void igb_power_down_phy_copper(struct e1000_hw *hw)
{ {
u16 mii_reg = 0; u16 mii_reg = 0;
u16 power_reg = 0;
/* The PHY will retain its settings across a power down/up cycle */ /* The PHY will retain its settings across a power down/up cycle */
hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
mii_reg |= MII_CR_POWER_DOWN; mii_reg |= MII_CR_POWER_DOWN;
/* i210 Phy requires an additional bit for power up/down */
if (hw->phy.type == e1000_phy_i210) {
hw->phy.ops.read_reg(hw, GS40G_COPPER_SPEC, &power_reg);
power_reg |= GS40G_CS_POWER_DOWN;
hw->phy.ops.write_reg(hw, GS40G_COPPER_SPEC, power_reg);
}
hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
usleep_range(1000, 2000); usleep_range(1000, 2000);
} }

1
drivers/net/ethernet/intel/igb/e1000_phy.h
View File

@ -151,7 +151,6 @@ s32 igb_check_polarity_m88(struct e1000_hw *hw);
#define GS40G_MAC_LB 0x4140 #define GS40G_MAC_LB 0x4140
#define GS40G_MAC_SPEED_1G 0X0006 #define GS40G_MAC_SPEED_1G 0X0006
#define GS40G_COPPER_SPEC 0x0010 #define GS40G_COPPER_SPEC 0x0010
#define GS40G_CS_POWER_DOWN 0x0002
#define GS40G_LINE_LB 0x4000 #define GS40G_LINE_LB 0x4000
/* SFP modules ID memory locations */ /* SFP modules ID memory locations */