Merge branch 'pci/dpc' into next
* pci/dpc: PCI/DPC: Add local struct device pointers PCI/DPC: Add eDPC support
This commit is contained in:
Bjorn Helgaas
commit
18f20670e0
@ -16,17 +16,62 @@
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#include <linux/pcieport_if.h>
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#include "../pci.h"
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struct rp_pio_header_log_regs {
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u32 dw0;
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u32 dw1;
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u32 dw2;
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u32 dw3;
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};
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struct dpc_rp_pio_regs {
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u32 status;
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u32 mask;
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u32 severity;
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u32 syserror;
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u32 exception;
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struct rp_pio_header_log_regs header_log;
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u32 impspec_log;
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u32 tlp_prefix_log[4];
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u32 log_size;
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u16 first_error;
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};
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struct dpc_dev {
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struct pcie_device *dev;
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struct work_struct work;
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int cap_pos;
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bool rp;
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u32 rp_pio_status;
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};
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static const char * const rp_pio_error_string[] = {
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"Configuration Request received UR Completion", /* Bit Position 0 */
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"Configuration Request received CA Completion", /* Bit Position 1 */
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"Configuration Request Completion Timeout", /* Bit Position 2 */
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NULL,
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NULL,
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NULL,
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NULL,
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NULL,
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"I/O Request received UR Completion", /* Bit Position 8 */
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"I/O Request received CA Completion", /* Bit Position 9 */
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"I/O Request Completion Timeout", /* Bit Position 10 */
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NULL,
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NULL,
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NULL,
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NULL,
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NULL,
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"Memory Request received UR Completion", /* Bit Position 16 */
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"Memory Request received CA Completion", /* Bit Position 17 */
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"Memory Request Completion Timeout", /* Bit Position 18 */
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};
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static int dpc_wait_rp_inactive(struct dpc_dev *dpc)
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{
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unsigned long timeout = jiffies + HZ;
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struct pci_dev *pdev = dpc->dev->port;
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struct device *dev = &dpc->dev->device;
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u16 status;
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pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_STATUS, &status);
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@ -36,15 +81,17 @@ static int dpc_wait_rp_inactive(struct dpc_dev *dpc)
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pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_STATUS, &status);
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}
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if (status & PCI_EXP_DPC_RP_BUSY) {
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dev_warn(&pdev->dev, "DPC root port still busy\n");
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dev_warn(dev, "DPC root port still busy\n");
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return -EBUSY;
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}
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return 0;
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}
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static void dpc_wait_link_inactive(struct pci_dev *pdev)
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static void dpc_wait_link_inactive(struct dpc_dev *dpc)
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{
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unsigned long timeout = jiffies + HZ;
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struct pci_dev *pdev = dpc->dev->port;
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struct device *dev = &dpc->dev->device;
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u16 lnk_status;
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pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
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@ -54,7 +101,7 @@ static void dpc_wait_link_inactive(struct pci_dev *pdev)
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pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
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}
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if (lnk_status & PCI_EXP_LNKSTA_DLLLA)
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dev_warn(&pdev->dev, "Link state not disabled for DPC event\n");
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dev_warn(dev, "Link state not disabled for DPC event\n");
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}
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static void interrupt_event_handler(struct work_struct *work)
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@ -76,17 +123,132 @@ static void interrupt_event_handler(struct work_struct *work)
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}
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pci_unlock_rescan_remove();
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dpc_wait_link_inactive(pdev);
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dpc_wait_link_inactive(dpc);
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if (dpc->rp && dpc_wait_rp_inactive(dpc))
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return;
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if (dpc->rp && dpc->rp_pio_status) {
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pci_write_config_dword(pdev,
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dpc->cap_pos + PCI_EXP_DPC_RP_PIO_STATUS,
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dpc->rp_pio_status);
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dpc->rp_pio_status = 0;
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}
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pci_write_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_STATUS,
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PCI_EXP_DPC_STATUS_TRIGGER | PCI_EXP_DPC_STATUS_INTERRUPT);
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}
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static void dpc_rp_pio_print_tlp_header(struct device *dev,
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struct rp_pio_header_log_regs *t)
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{
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dev_err(dev, "TLP Header: %#010x %#010x %#010x %#010x\n",
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t->dw0, t->dw1, t->dw2, t->dw3);
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}
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static void dpc_rp_pio_print_error(struct dpc_dev *dpc,
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struct dpc_rp_pio_regs *rp_pio)
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{
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struct device *dev = &dpc->dev->device;
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int i;
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u32 status;
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dev_err(dev, "rp_pio_status: %#010x, rp_pio_mask: %#010x\n",
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rp_pio->status, rp_pio->mask);
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dev_err(dev, "RP PIO severity=%#010x, syserror=%#010x, exception=%#010x\n",
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rp_pio->severity, rp_pio->syserror, rp_pio->exception);
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status = (rp_pio->status & ~rp_pio->mask);
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for (i = 0; i < ARRAY_SIZE(rp_pio_error_string); i++) {
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if (!(status & (1 << i)))
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continue;
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dev_err(dev, "[%2d] %s%s\n", i, rp_pio_error_string[i],
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rp_pio->first_error == i ? " (First)" : "");
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}
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dpc_rp_pio_print_tlp_header(dev, &rp_pio->header_log);
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if (rp_pio->log_size == 4)
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return;
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dev_err(dev, "RP PIO ImpSpec Log %#010x\n", rp_pio->impspec_log);
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for (i = 0; i < rp_pio->log_size - 5; i++)
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dev_err(dev, "TLP Prefix Header: dw%d, %#010x\n", i,
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rp_pio->tlp_prefix_log[i]);
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}
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static void dpc_rp_pio_get_info(struct dpc_dev *dpc,
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struct dpc_rp_pio_regs *rp_pio)
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{
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struct pci_dev *pdev = dpc->dev->port;
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struct device *dev = &dpc->dev->device;
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int i;
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u16 cap;
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u16 status;
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pci_read_config_dword(pdev, dpc->cap_pos + PCI_EXP_DPC_RP_PIO_STATUS,
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&rp_pio->status);
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pci_read_config_dword(pdev, dpc->cap_pos + PCI_EXP_DPC_RP_PIO_MASK,
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&rp_pio->mask);
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pci_read_config_dword(pdev, dpc->cap_pos + PCI_EXP_DPC_RP_PIO_SEVERITY,
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&rp_pio->severity);
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pci_read_config_dword(pdev, dpc->cap_pos + PCI_EXP_DPC_RP_PIO_SYSERROR,
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&rp_pio->syserror);
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pci_read_config_dword(pdev, dpc->cap_pos + PCI_EXP_DPC_RP_PIO_EXCEPTION,
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&rp_pio->exception);
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/* Get First Error Pointer */
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pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_STATUS, &status);
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rp_pio->first_error = (status & 0x1f00) >> 8;
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pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CAP, &cap);
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rp_pio->log_size = (cap & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8;
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if (rp_pio->log_size < 4 || rp_pio->log_size > 9) {
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dev_err(dev, "RP PIO log size %u is invalid\n",
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rp_pio->log_size);
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return;
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}
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pci_read_config_dword(pdev,
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dpc->cap_pos + PCI_EXP_DPC_RP_PIO_HEADER_LOG,
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&rp_pio->header_log.dw0);
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pci_read_config_dword(pdev,
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dpc->cap_pos + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 4,
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&rp_pio->header_log.dw1);
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pci_read_config_dword(pdev,
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dpc->cap_pos + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 8,
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&rp_pio->header_log.dw2);
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pci_read_config_dword(pdev,
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dpc->cap_pos + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 12,
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&rp_pio->header_log.dw3);
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if (rp_pio->log_size == 4)
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return;
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pci_read_config_dword(pdev,
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dpc->cap_pos + PCI_EXP_DPC_RP_PIO_IMPSPEC_LOG,
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&rp_pio->impspec_log);
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for (i = 0; i < rp_pio->log_size - 5; i++)
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pci_read_config_dword(pdev,
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dpc->cap_pos + PCI_EXP_DPC_RP_PIO_TLPPREFIX_LOG,
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&rp_pio->tlp_prefix_log[i]);
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}
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static void dpc_process_rp_pio_error(struct dpc_dev *dpc)
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{
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struct dpc_rp_pio_regs rp_pio_regs;
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dpc_rp_pio_get_info(dpc, &rp_pio_regs);
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dpc_rp_pio_print_error(dpc, &rp_pio_regs);
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dpc->rp_pio_status = rp_pio_regs.status;
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}
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static irqreturn_t dpc_irq(int irq, void *context)
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{
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struct dpc_dev *dpc = (struct dpc_dev *)context;
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struct pci_dev *pdev = dpc->dev->port;
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struct device *dev = &dpc->dev->device;
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u16 status, source;
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pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_STATUS, &status);
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@ -95,20 +257,24 @@ static irqreturn_t dpc_irq(int irq, void *context)
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if (!status || status == (u16)(~0))
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return IRQ_NONE;
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dev_info(&dpc->dev->device, "DPC containment event, status:%#06x source:%#06x\n",
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dev_info(dev, "DPC containment event, status:%#06x source:%#06x\n",
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status, source);
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if (status & PCI_EXP_DPC_STATUS_TRIGGER) {
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u16 reason = (status >> 1) & 0x3;
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u16 ext_reason = (status >> 5) & 0x3;
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dev_warn(&dpc->dev->device, "DPC %s detected, remove downstream devices\n",
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dev_warn(dev, "DPC %s detected, remove downstream devices\n",
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(reason == 0) ? "unmasked uncorrectable error" :
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(reason == 1) ? "ERR_NONFATAL" :
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(reason == 2) ? "ERR_FATAL" :
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(ext_reason == 0) ? "RP PIO error" :
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(ext_reason == 1) ? "software trigger" :
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"reserved error");
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/* show RP PIO error detail information */
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if (reason == 3 && ext_reason == 0)
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dpc_process_rp_pio_error(dpc);
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schedule_work(&dpc->work);
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}
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return IRQ_HANDLED;
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@ -119,10 +285,11 @@ static int dpc_probe(struct pcie_device *dev)
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{
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struct dpc_dev *dpc;
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struct pci_dev *pdev = dev->port;
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struct device *device = &dev->device;
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int status;
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u16 ctl, cap;
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dpc = devm_kzalloc(&dev->device, sizeof(*dpc), GFP_KERNEL);
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dpc = devm_kzalloc(device, sizeof(*dpc), GFP_KERNEL);
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if (!dpc)
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return -ENOMEM;
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@ -131,10 +298,10 @@ static int dpc_probe(struct pcie_device *dev)
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INIT_WORK(&dpc->work, interrupt_event_handler);
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set_service_data(dev, dpc);
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status = devm_request_irq(&dev->device, dev->irq, dpc_irq, IRQF_SHARED,
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status = devm_request_irq(device, dev->irq, dpc_irq, IRQF_SHARED,
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"pcie-dpc", dpc);
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if (status) {
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dev_warn(&dev->device, "request IRQ%d failed: %d\n", dev->irq,
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dev_warn(device, "request IRQ%d failed: %d\n", dev->irq,
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status);
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return status;
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}
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@ -147,7 +314,7 @@ static int dpc_probe(struct pcie_device *dev)
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ctl = (ctl & 0xfff4) | PCI_EXP_DPC_CTL_EN_NONFATAL | PCI_EXP_DPC_CTL_INT_EN;
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pci_write_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CTL, ctl);
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dev_info(&dev->device, "DPC error containment capabilities: Int Msg #%d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n",
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dev_info(device, "DPC error containment capabilities: Int Msg #%d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n",
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cap & 0xf, FLAG(cap, PCI_EXP_DPC_CAP_RP_EXT),
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FLAG(cap, PCI_EXP_DPC_CAP_POISONED_TLP),
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FLAG(cap, PCI_EXP_DPC_CAP_SW_TRIGGER), (cap >> 8) & 0xf,
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@ -961,6 +961,7 @@
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#define PCI_EXP_DPC_CAP_RP_EXT 0x20 /* Root Port Extensions for DPC */
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#define PCI_EXP_DPC_CAP_POISONED_TLP 0x40 /* Poisoned TLP Egress Blocking Supported */
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#define PCI_EXP_DPC_CAP_SW_TRIGGER 0x80 /* Software Triggering Supported */
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#define PCI_EXP_DPC_RP_PIO_LOG_SIZE 0xF00 /* RP PIO log size */
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#define PCI_EXP_DPC_CAP_DL_ACTIVE 0x1000 /* ERR_COR signal on DL_Active supported */
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#define PCI_EXP_DPC_CTL 6 /* DPC control */
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@ -974,6 +975,15 @@
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#define PCI_EXP_DPC_SOURCE_ID 10 /* DPC Source Identifier */
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#define PCI_EXP_DPC_RP_PIO_STATUS 0x0C /* RP PIO Status */
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#define PCI_EXP_DPC_RP_PIO_MASK 0x10 /* RP PIO MASK */
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#define PCI_EXP_DPC_RP_PIO_SEVERITY 0x14 /* RP PIO Severity */
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#define PCI_EXP_DPC_RP_PIO_SYSERROR 0x18 /* RP PIO SysError */
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#define PCI_EXP_DPC_RP_PIO_EXCEPTION 0x1C /* RP PIO Exception */
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#define PCI_EXP_DPC_RP_PIO_HEADER_LOG 0x20 /* RP PIO Header Log */
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#define PCI_EXP_DPC_RP_PIO_IMPSPEC_LOG 0x30 /* RP PIO ImpSpec Log */
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#define PCI_EXP_DPC_RP_PIO_TLPPREFIX_LOG 0x34 /* RP PIO TLP Prefix Log */
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/* Precision Time Measurement */
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#define PCI_PTM_CAP 0x04 /* PTM Capability */
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#define PCI_PTM_CAP_REQ 0x00000001 /* Requester capable */
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