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clk: renesas: rcar-gen3: Update Z clock rate formula in comments

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The fixed divider in the calculation of the Z and Z2 clock rates was
generalized from a hardcoded value of two to a parameterized value, but
the comments were not updated accordingly.

Fixes: 20cc05ba04 ("clk: renesas: rcar-gen3: Parameterise Z and Z2 clock fixed divisor")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20210326120100.1577596-2-geert+renesas@glider.be
This commit is contained in:
Geert Uytterhoeven 2021-03-26 13:00:54 +01:00
parent 6efb943b86
commit 192c344e7c
1 changed files with 2 additions and 1 deletions
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3
drivers/clk/renesas/rcar-gen3-cpg.c
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@ -38,7 +38,8 @@
* Traits of this clock:
* prepare - clk_prepare only ensures that parents are prepared
* enable - clk_enable only ensures that parents are enabled
* rate - rate is adjustable. clk->rate = (parent->rate * mult / 32 ) / 2
* rate - rate is adjustable.
* clk->rate = (parent->rate * mult / 32 ) / fixed_div
* parent - fixed parent. No clk_set_parent support
*/
#define CPG_FRQCRB 0x00000004