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Merge branch 'rzg-clock-defs' into clk-renesas-for-v4.10

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Add r8a7743 and r8a7745 CPG Core Clock Definitions
This commit is contained in:
Geert Uytterhoeven 2016-11-07 15:15:33 +01:00
commit 1936be95e0
2 changed files with 87 additions and 0 deletions
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43
include/dt-bindings/clock/r8a7743-cpg-mssr.h Normal file
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/*
* Copyright (C) 2016 Cogent Embedded Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A7743_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A7743_CPG_MSSR_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* r8a7743 CPG Core Clocks */
#define R8A7743_CLK_Z 0
#define R8A7743_CLK_ZG 1
#define R8A7743_CLK_ZTR 2
#define R8A7743_CLK_ZTRD2 3
#define R8A7743_CLK_ZT 4
#define R8A7743_CLK_ZX 5
#define R8A7743_CLK_ZS 6
#define R8A7743_CLK_HP 7
#define R8A7743_CLK_B 9
#define R8A7743_CLK_LB 10
#define R8A7743_CLK_P 11
#define R8A7743_CLK_CL 12
#define R8A7743_CLK_M2 13
#define R8A7743_CLK_ZB3 15
#define R8A7743_CLK_ZB3D2 16
#define R8A7743_CLK_DDR 17
#define R8A7743_CLK_SDH 18
#define R8A7743_CLK_SD0 19
#define R8A7743_CLK_SD2 20
#define R8A7743_CLK_SD3 21
#define R8A7743_CLK_MMC0 22
#define R8A7743_CLK_MP 23
#define R8A7743_CLK_QSPI 26
#define R8A7743_CLK_CP 27
#define R8A7743_CLK_RCAN 28
#define R8A7743_CLK_R 29
#define R8A7743_CLK_OSC 30
#endif /* __DT_BINDINGS_CLOCK_R8A7743_CPG_MSSR_H__ */

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include/dt-bindings/clock/r8a7745-cpg-mssr.h Normal file
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/*
* Copyright (C) 2016 Cogent Embedded Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A7745_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A7745_CPG_MSSR_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* r8a7745 CPG Core Clocks */
#define R8A7745_CLK_Z2 0
#define R8A7745_CLK_ZG 1
#define R8A7745_CLK_ZTR 2
#define R8A7745_CLK_ZTRD2 3
#define R8A7745_CLK_ZT 4
#define R8A7745_CLK_ZX 5
#define R8A7745_CLK_ZS 6
#define R8A7745_CLK_HP 7
#define R8A7745_CLK_B 9
#define R8A7745_CLK_LB 10
#define R8A7745_CLK_P 11
#define R8A7745_CLK_CL 12
#define R8A7745_CLK_CP 13
#define R8A7745_CLK_M2 14
#define R8A7745_CLK_ZB3 16
#define R8A7745_CLK_ZB3D2 17
#define R8A7745_CLK_DDR 18
#define R8A7745_CLK_SDH 19
#define R8A7745_CLK_SD0 20
#define R8A7745_CLK_SD2 21
#define R8A7745_CLK_SD3 22
#define R8A7745_CLK_MMC0 23
#define R8A7745_CLK_MP 24
#define R8A7745_CLK_QSPI 25
#define R8A7745_CLK_CPEX 26
#define R8A7745_CLK_RCAN 27
#define R8A7745_CLK_R 28
#define R8A7745_CLK_OSC 29
#endif /* __DT_BINDINGS_CLOCK_R8A7745_CPG_MSSR_H__ */