Blackfin arch: update blackfin header files to latest one in VDSP.
a) add new processor BF52x/BF54x header files b) update blackfin BF533/BF537/BF561 header files to latest one in VDSP. c) scrub watchdog/rtc masks from headers as we dont need/want them (too generic and the drivers dont use them) Signed-off-by: Mike Frysinger <michael.frysinger@analog.com> Signed-off-by: Roy Huang <roy.huang@analog.com> Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Bryan Wu
Linus Torvalds
parent
c09c4e0065
commit
19381f024b
46
include/asm-blackfin/mach-bf527/cdefBF522.h
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include/asm-blackfin/mach-bf527/cdefBF522.h
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/*
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* File: include/asm-blackfin/mach-bf527/cdefbf522.h
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* Based on:
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* Author:
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*
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* Created:
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* Description: system mmr register map
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*
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* Rev:
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*
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* Modified:
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*
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*
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING.
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* If not, write to the Free Software Foundation,
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#ifndef _CDEF_BF522_H
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#define _CDEF_BF522_H
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/* include all Core registers and bit definitions */
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#include "defBF522.h"
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/* include core specific register pointer definitions */
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#include <asm/mach-common/cdef_LPBlackfin.h>
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/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF522 */
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/* include cdefBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
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#include "cdefBF52x_base.h"
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#endif /* _CDEF_BF522_H */
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461
include/asm-blackfin/mach-bf527/cdefBF525.h
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461
include/asm-blackfin/mach-bf527/cdefBF525.h
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/*
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* File: include/asm-blackfin/mach-bf527/cdefbf525.h
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* Based on:
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* Author:
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*
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* Created:
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* Description: system mmr register map
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*
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* Rev:
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*
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* Modified:
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*
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*
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING.
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* If not, write to the Free Software Foundation,
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#ifndef _CDEF_BF525_H
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#define _CDEF_BF525_H
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/* include all Core registers and bit definitions */
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#include "defBF525.h"
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/* include core specific register pointer definitions */
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#include <asm/mach-common/cdef_LPBlackfin.h>
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/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF525 */
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/* include cdefBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
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#include "cdefBF52x_base.h"
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/* The following are the #defines needed by ADSP-BF525 that are not in the common header */
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/* USB Control Registers */
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#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
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#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
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#define bfin_read_USB_POWER() bfin_read16(USB_POWER)
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#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
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#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX)
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#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
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#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX)
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#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
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#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE)
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#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
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#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE)
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#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
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#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB)
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#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
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#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE)
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#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
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#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME)
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#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
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#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
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#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
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#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE)
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#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
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#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
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#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
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#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
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#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
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/* USB Packet Control Registers */
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#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET)
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#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
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#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0)
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#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
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#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR)
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#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
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#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET)
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#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
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#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR)
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#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
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#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0)
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#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
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#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT)
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#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
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#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE)
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#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
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#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0)
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#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
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#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL)
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#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
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#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE)
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#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
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#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL)
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#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
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#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT)
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#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
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/* USB Endpoint FIFO Registers */
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#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO)
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#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
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#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO)
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#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
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#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO)
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#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
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#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO)
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#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
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#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO)
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#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
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#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO)
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#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
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#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO)
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#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
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#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO)
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#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
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/* USB OTG Control Registers */
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#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
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#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
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#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
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#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
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#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
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#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
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/* USB Phy Control Registers */
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#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO)
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#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
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#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN)
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#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
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#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1)
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#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
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#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1)
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#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
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#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1)
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#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
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/* (APHY_CNTRL is for ADI usage only) */
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#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL)
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#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
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/* (APHY_CALIB is for ADI usage only) */
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#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB)
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#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
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#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2)
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#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
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/* (PHY_TEST is for ADI usage only) */
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#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST)
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#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val)
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#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL)
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#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
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#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV)
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#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
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/* USB Endpoint 0 Control Registers */
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#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP)
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#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
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#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR)
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#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
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#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP)
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#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
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#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR)
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#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
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#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
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#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
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#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE)
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#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
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#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
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#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
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#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE)
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#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
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#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
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#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
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#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
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#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
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/* USB Endpoint 1 Control Registers */
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#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP)
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#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
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#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR)
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#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
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#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP)
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#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
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#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR)
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#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
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#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
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#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
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#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE)
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#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
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#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
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#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
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#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE)
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#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
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#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
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#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
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#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
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#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
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/* USB Endpoint 2 Control Registers */
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#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP)
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#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
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#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR)
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#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
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#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP)
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#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
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#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR)
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#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
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#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
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#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE)
|
||||
#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE)
|
||||
#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
|
||||
#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
|
||||
|
||||
/* USB Endpoint 3 Control Registers */
|
||||
|
||||
#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP)
|
||||
#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR)
|
||||
#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
|
||||
#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP)
|
||||
#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR)
|
||||
#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
|
||||
#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
|
||||
#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE)
|
||||
#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE)
|
||||
#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
|
||||
#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
|
||||
|
||||
/* USB Endpoint 4 Control Registers */
|
||||
|
||||
#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP)
|
||||
#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR)
|
||||
#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
|
||||
#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP)
|
||||
#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR)
|
||||
#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
|
||||
#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
|
||||
#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE)
|
||||
#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE)
|
||||
#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
|
||||
#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
|
||||
|
||||
/* USB Endpoint 5 Control Registers */
|
||||
|
||||
#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP)
|
||||
#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR)
|
||||
#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
|
||||
#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP)
|
||||
#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR)
|
||||
#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
|
||||
#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
|
||||
#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE)
|
||||
#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE)
|
||||
#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
|
||||
#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
|
||||
|
||||
/* USB Endpoint 6 Control Registers */
|
||||
|
||||
#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP)
|
||||
#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR)
|
||||
#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
|
||||
#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP)
|
||||
#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR)
|
||||
#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
|
||||
#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
|
||||
#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE)
|
||||
#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE)
|
||||
#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
|
||||
#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
|
||||
|
||||
/* USB Endpoint 7 Control Registers */
|
||||
|
||||
#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP)
|
||||
#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR)
|
||||
#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
|
||||
#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP)
|
||||
#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR)
|
||||
#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
|
||||
#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
|
||||
#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE)
|
||||
#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE)
|
||||
#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
|
||||
#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
|
||||
|
||||
#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT)
|
||||
#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
|
||||
|
||||
/* USB Channel 0 Config Registers */
|
||||
|
||||
#define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL)
|
||||
#define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val)
|
||||
#define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW)
|
||||
#define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val)
|
||||
#define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH)
|
||||
#define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val)
|
||||
#define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW)
|
||||
#define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val)
|
||||
#define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH)
|
||||
#define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val)
|
||||
|
||||
/* USB Channel 1 Config Registers */
|
||||
|
||||
#define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL)
|
||||
#define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val)
|
||||
#define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW)
|
||||
#define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val)
|
||||
#define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH)
|
||||
#define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val)
|
||||
#define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW)
|
||||
#define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val)
|
||||
#define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH)
|
||||
#define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val)
|
||||
|
||||
/* USB Channel 2 Config Registers */
|
||||
|
||||
#define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL)
|
||||
#define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val)
|
||||
#define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW)
|
||||
#define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val)
|
||||
#define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH)
|
||||
#define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val)
|
||||
#define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW)
|
||||
#define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val)
|
||||
#define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH)
|
||||
#define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val)
|
||||
|
||||
/* USB Channel 3 Config Registers */
|
||||
|
||||
#define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL)
|
||||
#define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val)
|
||||
#define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW)
|
||||
#define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val)
|
||||
#define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH)
|
||||
#define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val)
|
||||
#define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW)
|
||||
#define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val)
|
||||
#define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH)
|
||||
#define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val)
|
||||
|
||||
/* USB Channel 4 Config Registers */
|
||||
|
||||
#define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL)
|
||||
#define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val)
|
||||
#define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW)
|
||||
#define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val)
|
||||
#define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH)
|
||||
#define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val)
|
||||
#define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW)
|
||||
#define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val)
|
||||
#define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH)
|
||||
#define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val)
|
||||
|
||||
/* USB Channel 5 Config Registers */
|
||||
|
||||
#define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL)
|
||||
#define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val)
|
||||
#define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW)
|
||||
#define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val)
|
||||
#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH)
|
||||
#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val)
|
||||
#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW)
|
||||
#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val)
|
||||
#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH)
|
||||
#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val)
|
||||
|
||||
/* USB Channel 6 Config Registers */
|
||||
|
||||
#define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL)
|
||||
#define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val)
|
||||
#define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW)
|
||||
#define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val)
|
||||
#define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH)
|
||||
#define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val)
|
||||
#define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW)
|
||||
#define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val)
|
||||
#define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH)
|
||||
#define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val)
|
||||
|
||||
/* USB Channel 7 Config Registers */
|
||||
|
||||
#define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL)
|
||||
#define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val)
|
||||
#define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW)
|
||||
#define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val)
|
||||
#define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH)
|
||||
#define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val)
|
||||
#define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW)
|
||||
#define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val)
|
||||
#define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH)
|
||||
#define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val)
|
||||
|
||||
#endif /* _CDEF_BF525_H */
|
||||
626
include/asm-blackfin/mach-bf527/cdefBF527.h
Normal file
626
include/asm-blackfin/mach-bf527/cdefBF527.h
Normal file
@ -0,0 +1,626 @@
|
||||
/*
|
||||
* File: include/asm-blackfin/mach-bf527/cdefbf527.h
|
||||
* Based on:
|
||||
* Author:
|
||||
*
|
||||
* Created:
|
||||
* Description: system mmr register map
|
||||
*
|
||||
* Rev:
|
||||
*
|
||||
* Modified:
|
||||
*
|
||||
*
|
||||
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING.
|
||||
* If not, write to the Free Software Foundation,
|
||||
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
*/
|
||||
|
||||
#ifndef _CDEF_BF527_H
|
||||
#define _CDEF_BF527_H
|
||||
|
||||
/* include all Core registers and bit definitions */
|
||||
#include "defBF527.h"
|
||||
|
||||
/* include core specific register pointer definitions */
|
||||
#include <asm/mach-common/cdef_LPBlackfin.h>
|
||||
|
||||
/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF527 */
|
||||
|
||||
/* include cdefBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
|
||||
#include "cdefBF52x_base.h"
|
||||
|
||||
/* The following are the #defines needed by ADSP-BF527 that are not in the common header */
|
||||
|
||||
/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
|
||||
|
||||
#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE)
|
||||
#define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val)
|
||||
#define bfin_read_EMAC_ADDRLO() bfin_read32(EMAC_ADDRLO)
|
||||
#define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO, val)
|
||||
#define bfin_read_EMAC_ADDRHI() bfin_read32(EMAC_ADDRHI)
|
||||
#define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI, val)
|
||||
#define bfin_read_EMAC_HASHLO() bfin_read32(EMAC_HASHLO)
|
||||
#define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO, val)
|
||||
#define bfin_read_EMAC_HASHHI() bfin_read32(EMAC_HASHHI)
|
||||
#define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI, val)
|
||||
#define bfin_read_EMAC_STAADD() bfin_read32(EMAC_STAADD)
|
||||
#define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD, val)
|
||||
#define bfin_read_EMAC_STADAT() bfin_read32(EMAC_STADAT)
|
||||
#define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT, val)
|
||||
#define bfin_read_EMAC_FLC() bfin_read32(EMAC_FLC)
|
||||
#define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC, val)
|
||||
#define bfin_read_EMAC_VLAN1() bfin_read32(EMAC_VLAN1)
|
||||
#define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1, val)
|
||||
#define bfin_read_EMAC_VLAN2() bfin_read32(EMAC_VLAN2)
|
||||
#define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2, val)
|
||||
#define bfin_read_EMAC_WKUP_CTL() bfin_read32(EMAC_WKUP_CTL)
|
||||
#define bfin_write_EMAC_WKUP_CTL(val) bfin_write32(EMAC_WKUP_CTL, val)
|
||||
#define bfin_read_EMAC_WKUP_FFMSK0() bfin_read32(EMAC_WKUP_FFMSK0)
|
||||
#define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val)
|
||||
#define bfin_read_EMAC_WKUP_FFMSK1() bfin_read32(EMAC_WKUP_FFMSK1)
|
||||
#define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val)
|
||||
#define bfin_read_EMAC_WKUP_FFMSK2() bfin_read32(EMAC_WKUP_FFMSK2)
|
||||
#define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val)
|
||||
#define bfin_read_EMAC_WKUP_FFMSK3() bfin_read32(EMAC_WKUP_FFMSK3)
|
||||
#define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val)
|
||||
#define bfin_read_EMAC_WKUP_FFCMD() bfin_read32(EMAC_WKUP_FFCMD)
|
||||
#define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val)
|
||||
#define bfin_read_EMAC_WKUP_FFOFF() bfin_read32(EMAC_WKUP_FFOFF)
|
||||
#define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val)
|
||||
#define bfin_read_EMAC_WKUP_FFCRC0() bfin_read32(EMAC_WKUP_FFCRC0)
|
||||
#define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val)
|
||||
#define bfin_read_EMAC_WKUP_FFCRC1() bfin_read32(EMAC_WKUP_FFCRC1)
|
||||
#define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val)
|
||||
|
||||
#define bfin_read_EMAC_SYSCTL() bfin_read32(EMAC_SYSCTL)
|
||||
#define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val)
|
||||
#define bfin_read_EMAC_SYSTAT() bfin_read32(EMAC_SYSTAT)
|
||||
#define bfin_write_EMAC_SYSTAT(val) bfin_write32(EMAC_SYSTAT, val)
|
||||
#define bfin_read_EMAC_RX_STAT() bfin_read32(EMAC_RX_STAT)
|
||||
#define bfin_write_EMAC_RX_STAT(val) bfin_write32(EMAC_RX_STAT, val)
|
||||
#define bfin_read_EMAC_RX_STKY() bfin_read32(EMAC_RX_STKY)
|
||||
#define bfin_write_EMAC_RX_STKY(val) bfin_write32(EMAC_RX_STKY, val)
|
||||
#define bfin_read_EMAC_RX_IRQE() bfin_read32(EMAC_RX_IRQE)
|
||||
#define bfin_write_EMAC_RX_IRQE(val) bfin_write32(EMAC_RX_IRQE, val)
|
||||
#define bfin_read_EMAC_TX_STAT() bfin_read32(EMAC_TX_STAT)
|
||||
#define bfin_write_EMAC_TX_STAT(val) bfin_write32(EMAC_TX_STAT, val)
|
||||
#define bfin_read_EMAC_TX_STKY() bfin_read32(EMAC_TX_STKY)
|
||||
#define bfin_write_EMAC_TX_STKY(val) bfin_write32(EMAC_TX_STKY, val)
|
||||
#define bfin_read_EMAC_TX_IRQE() bfin_read32(EMAC_TX_IRQE)
|
||||
#define bfin_write_EMAC_TX_IRQE(val) bfin_write32(EMAC_TX_IRQE, val)
|
||||
|
||||
#define bfin_read_EMAC_MMC_CTL() bfin_read32(EMAC_MMC_CTL)
|
||||
#define bfin_write_EMAC_MMC_CTL(val) bfin_write32(EMAC_MMC_CTL, val)
|
||||
#define bfin_read_EMAC_MMC_RIRQS() bfin_read32(EMAC_MMC_RIRQS)
|
||||
#define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val)
|
||||
#define bfin_read_EMAC_MMC_RIRQE() bfin_read32(EMAC_MMC_RIRQE)
|
||||
#define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val)
|
||||
#define bfin_read_EMAC_MMC_TIRQS() bfin_read32(EMAC_MMC_TIRQS)
|
||||
#define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val)
|
||||
#define bfin_read_EMAC_MMC_TIRQE() bfin_read32(EMAC_MMC_TIRQE)
|
||||
#define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val)
|
||||
|
||||
#define bfin_read_EMAC_RXC_OK() bfin_read32(EMAC_RXC_OK)
|
||||
#define bfin_write_EMAC_RXC_OK(val) bfin_write32(EMAC_RXC_OK, val)
|
||||
#define bfin_read_EMAC_RXC_FCS() bfin_read32(EMAC_RXC_FCS)
|
||||
#define bfin_write_EMAC_RXC_FCS(val) bfin_write32(EMAC_RXC_FCS, val)
|
||||
#define bfin_read_EMAC_RXC_ALIGN() bfin_read32(EMAC_RXC_ALIGN)
|
||||
#define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val)
|
||||
#define bfin_read_EMAC_RXC_OCTET() bfin_read32(EMAC_RXC_OCTET)
|
||||
#define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val)
|
||||
#define bfin_read_EMAC_RXC_DMAOVF() bfin_read32(EMAC_RXC_DMAOVF)
|
||||
#define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val)
|
||||
#define bfin_read_EMAC_RXC_UNICST() bfin_read32(EMAC_RXC_UNICST)
|
||||
#define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val)
|
||||
#define bfin_read_EMAC_RXC_MULTI() bfin_read32(EMAC_RXC_MULTI)
|
||||
#define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val)
|
||||
#define bfin_read_EMAC_RXC_BROAD() bfin_read32(EMAC_RXC_BROAD)
|
||||
#define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val)
|
||||
#define bfin_read_EMAC_RXC_LNERRI() bfin_read32(EMAC_RXC_LNERRI)
|
||||
#define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val)
|
||||
#define bfin_read_EMAC_RXC_LNERRO() bfin_read32(EMAC_RXC_LNERRO)
|
||||
#define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val)
|
||||
#define bfin_read_EMAC_RXC_LONG() bfin_read32(EMAC_RXC_LONG)
|
||||
#define bfin_write_EMAC_RXC_LONG(val) bfin_write32(EMAC_RXC_LONG, val)
|
||||
#define bfin_read_EMAC_RXC_MACCTL() bfin_read32(EMAC_RXC_MACCTL)
|
||||
#define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val)
|
||||
#define bfin_read_EMAC_RXC_OPCODE() bfin_read32(EMAC_RXC_OPCODE)
|
||||
#define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val)
|
||||
#define bfin_read_EMAC_RXC_PAUSE() bfin_read32(EMAC_RXC_PAUSE)
|
||||
#define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val)
|
||||
#define bfin_read_EMAC_RXC_ALLFRM() bfin_read32(EMAC_RXC_ALLFRM)
|
||||
#define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val)
|
||||
#define bfin_read_EMAC_RXC_ALLOCT() bfin_read32(EMAC_RXC_ALLOCT)
|
||||
#define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val)
|
||||
#define bfin_read_EMAC_RXC_TYPED() bfin_read32(EMAC_RXC_TYPED)
|
||||
#define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val)
|
||||
#define bfin_read_EMAC_RXC_SHORT() bfin_read32(EMAC_RXC_SHORT)
|
||||
#define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val)
|
||||
#define bfin_read_EMAC_RXC_EQ64() bfin_read32(EMAC_RXC_EQ64)
|
||||
#define bfin_write_EMAC_RXC_EQ64(val) bfin_write32(EMAC_RXC_EQ64, val)
|
||||
#define bfin_read_EMAC_RXC_LT128() bfin_read32(EMAC_RXC_LT128)
|
||||
#define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val)
|
||||
#define bfin_read_EMAC_RXC_LT256() bfin_read32(EMAC_RXC_LT256)
|
||||
#define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val)
|
||||
#define bfin_read_EMAC_RXC_LT512() bfin_read32(EMAC_RXC_LT512)
|
||||
#define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val)
|
||||
#define bfin_read_EMAC_RXC_LT1024() bfin_read32(EMAC_RXC_LT1024)
|
||||
#define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val)
|
||||
#define bfin_read_EMAC_RXC_GE1024() bfin_read32(EMAC_RXC_GE1024)
|
||||
#define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val)
|
||||
|
||||
#define bfin_read_EMAC_TXC_OK() bfin_read32(EMAC_TXC_OK)
|
||||
#define bfin_write_EMAC_TXC_OK(val) bfin_write32(EMAC_TXC_OK, val)
|
||||
#define bfin_read_EMAC_TXC_1COL() bfin_read32(EMAC_TXC_1COL)
|
||||
#define bfin_write_EMAC_TXC_1COL(val) bfin_write32(EMAC_TXC_1COL, val)
|
||||
#define bfin_read_EMAC_TXC_GT1COL() bfin_read32(EMAC_TXC_GT1COL)
|
||||
#define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val)
|
||||
#define bfin_read_EMAC_TXC_OCTET() bfin_read32(EMAC_TXC_OCTET)
|
||||
#define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val)
|
||||
#define bfin_read_EMAC_TXC_DEFER() bfin_read32(EMAC_TXC_DEFER)
|
||||
#define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val)
|
||||
#define bfin_read_EMAC_TXC_LATECL() bfin_read32(EMAC_TXC_LATECL)
|
||||
#define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val)
|
||||
#define bfin_read_EMAC_TXC_XS_COL() bfin_read32(EMAC_TXC_XS_COL)
|
||||
#define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val)
|
||||
#define bfin_read_EMAC_TXC_DMAUND() bfin_read32(EMAC_TXC_DMAUND)
|
||||
#define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val)
|
||||
#define bfin_read_EMAC_TXC_CRSERR() bfin_read32(EMAC_TXC_CRSERR)
|
||||
#define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val)
|
||||
#define bfin_read_EMAC_TXC_UNICST() bfin_read32(EMAC_TXC_UNICST)
|
||||
#define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val)
|
||||
#define bfin_read_EMAC_TXC_MULTI() bfin_read32(EMAC_TXC_MULTI)
|
||||
#define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val)
|
||||
#define bfin_read_EMAC_TXC_BROAD() bfin_read32(EMAC_TXC_BROAD)
|
||||
#define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val)
|
||||
#define bfin_read_EMAC_TXC_XS_DFR() bfin_read32(EMAC_TXC_XS_DFR)
|
||||
#define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val)
|
||||
#define bfin_read_EMAC_TXC_MACCTL() bfin_read32(EMAC_TXC_MACCTL)
|
||||
#define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val)
|
||||
#define bfin_read_EMAC_TXC_ALLFRM() bfin_read32(EMAC_TXC_ALLFRM)
|
||||
#define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val)
|
||||
#define bfin_read_EMAC_TXC_ALLOCT() bfin_read32(EMAC_TXC_ALLOCT)
|
||||
#define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val)
|
||||
#define bfin_read_EMAC_TXC_EQ64() bfin_read32(EMAC_TXC_EQ64)
|
||||
#define bfin_write_EMAC_TXC_EQ64(val) bfin_write32(EMAC_TXC_EQ64, val)
|
||||
#define bfin_read_EMAC_TXC_LT128() bfin_read32(EMAC_TXC_LT128)
|
||||
#define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val)
|
||||
#define bfin_read_EMAC_TXC_LT256() bfin_read32(EMAC_TXC_LT256)
|
||||
#define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val)
|
||||
#define bfin_read_EMAC_TXC_LT512() bfin_read32(EMAC_TXC_LT512)
|
||||
#define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val)
|
||||
#define bfin_read_EMAC_TXC_LT1024() bfin_read32(EMAC_TXC_LT1024)
|
||||
#define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val)
|
||||
#define bfin_read_EMAC_TXC_GE1024() bfin_read32(EMAC_TXC_GE1024)
|
||||
#define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val)
|
||||
#define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT)
|
||||
#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val)
|
||||
|
||||
/* USB Control Registers */
|
||||
|
||||
#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
|
||||
#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
|
||||
#define bfin_read_USB_POWER() bfin_read16(USB_POWER)
|
||||
#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
|
||||
#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX)
|
||||
#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
|
||||
#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX)
|
||||
#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
|
||||
#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE)
|
||||
#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
|
||||
#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE)
|
||||
#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
|
||||
#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB)
|
||||
#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
|
||||
#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE)
|
||||
#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
|
||||
#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME)
|
||||
#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
|
||||
#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
|
||||
#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
|
||||
#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE)
|
||||
#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
|
||||
#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
|
||||
#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
|
||||
#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
|
||||
#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
|
||||
|
||||
/* USB Packet Control Registers */
|
||||
|
||||
#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET)
|
||||
#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
|
||||
#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0)
|
||||
#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
|
||||
#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR)
|
||||
#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
|
||||
#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET)
|
||||
#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
|
||||
#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR)
|
||||
#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
|
||||
#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0)
|
||||
#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
|
||||
#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT)
|
||||
#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
|
||||
#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE)
|
||||
#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
|
||||
#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0)
|
||||
#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
|
||||
#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL)
|
||||
#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
|
||||
#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE)
|
||||
#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
|
||||
#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL)
|
||||
#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
|
||||
#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT)
|
||||
#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
|
||||
|
||||
/* USB Endpoint FIFO Registers */
|
||||
|
||||
#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO)
|
||||
#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
|
||||
#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO)
|
||||
#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
|
||||
#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO)
|
||||
#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
|
||||
#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO)
|
||||
#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
|
||||
#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO)
|
||||
#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
|
||||
#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO)
|
||||
#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
|
||||
#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO)
|
||||
#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
|
||||
#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO)
|
||||
#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
|
||||
|
||||
/* USB OTG Control Registers */
|
||||
|
||||
#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
|
||||
#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
|
||||
#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
|
||||
#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
|
||||
#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
|
||||
#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
|
||||
|
||||
/* USB Phy Control Registers */
|
||||
|
||||
#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO)
|
||||
#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
|
||||
#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN)
|
||||
#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
|
||||
#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1)
|
||||
#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
|
||||
#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1)
|
||||
#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
|
||||
#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1)
|
||||
#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
|
||||
|
||||
/* (APHY_CNTRL is for ADI usage only) */
|
||||
|
||||
#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL)
|
||||
#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
|
||||
|
||||
/* (APHY_CALIB is for ADI usage only) */
|
||||
|
||||
#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB)
|
||||
#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
|
||||
|
||||
#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2)
|
||||
#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
|
||||
|
||||
/* (PHY_TEST is for ADI usage only) */
|
||||
|
||||
#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST)
|
||||
#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val)
|
||||
|
||||
#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL)
|
||||
#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
|
||||
#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV)
|
||||
#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
|
||||
|
||||
/* USB Endpoint 0 Control Registers */
|
||||
|
||||
#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP)
|
||||
#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR)
|
||||
#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
|
||||
#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP)
|
||||
#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR)
|
||||
#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
|
||||
#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
|
||||
#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE)
|
||||
#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE)
|
||||
#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
|
||||
#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
|
||||
|
||||
/* USB Endpoint 1 Control Registers */
|
||||
|
||||
#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP)
|
||||
#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR)
|
||||
#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
|
||||
#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP)
|
||||
#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR)
|
||||
#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
|
||||
#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
|
||||
#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE)
|
||||
#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE)
|
||||
#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
|
||||
#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
|
||||
|
||||
/* USB Endpoint 2 Control Registers */
|
||||
|
||||
#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP)
|
||||
#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR)
|
||||
#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
|
||||
#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP)
|
||||
#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR)
|
||||
#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
|
||||
#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
|
||||
#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE)
|
||||
#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE)
|
||||
#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
|
||||
#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
|
||||
|
||||
/* USB Endpoint 3 Control Registers */
|
||||
|
||||
#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP)
|
||||
#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR)
|
||||
#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
|
||||
#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP)
|
||||
#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR)
|
||||
#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
|
||||
#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
|
||||
#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE)
|
||||
#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE)
|
||||
#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
|
||||
#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
|
||||
|
||||
/* USB Endpoint 4 Control Registers */
|
||||
|
||||
#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP)
|
||||
#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR)
|
||||
#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
|
||||
#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP)
|
||||
#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR)
|
||||
#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
|
||||
#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
|
||||
#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE)
|
||||
#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE)
|
||||
#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
|
||||
#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
|
||||
|
||||
/* USB Endpoint 5 Control Registers */
|
||||
|
||||
#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP)
|
||||
#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR)
|
||||
#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
|
||||
#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP)
|
||||
#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR)
|
||||
#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
|
||||
#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
|
||||
#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE)
|
||||
#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE)
|
||||
#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
|
||||
#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
|
||||
|
||||
/* USB Endpoint 6 Control Registers */
|
||||
|
||||
#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP)
|
||||
#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR)
|
||||
#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
|
||||
#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP)
|
||||
#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR)
|
||||
#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
|
||||
#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
|
||||
#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE)
|
||||
#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE)
|
||||
#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
|
||||
#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
|
||||
|
||||
/* USB Endpoint 7 Control Registers */
|
||||
|
||||
#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP)
|
||||
#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR)
|
||||
#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
|
||||
#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP)
|
||||
#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR)
|
||||
#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
|
||||
#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
|
||||
#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE)
|
||||
#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE)
|
||||
#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
|
||||
#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
|
||||
|
||||
#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT)
|
||||
#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
|
||||
|
||||
/* USB Channel 0 Config Registers */
|
||||
|
||||
#define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL)
|
||||
#define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val)
|
||||
#define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW)
|
||||
#define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val)
|
||||
#define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH)
|
||||
#define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val)
|
||||
#define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW)
|
||||
#define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val)
|
||||
#define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH)
|
||||
#define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val)
|
||||
|
||||
/* USB Channel 1 Config Registers */
|
||||
|
||||
#define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL)
|
||||
#define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val)
|
||||
#define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW)
|
||||
#define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val)
|
||||
#define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH)
|
||||
#define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val)
|
||||
#define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW)
|
||||
#define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val)
|
||||
#define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH)
|
||||
#define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val)
|
||||
|
||||
/* USB Channel 2 Config Registers */
|
||||
|
||||
#define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL)
|
||||
#define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val)
|
||||
#define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW)
|
||||
#define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val)
|
||||
#define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH)
|
||||
#define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val)
|
||||
#define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW)
|
||||
#define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val)
|
||||
#define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH)
|
||||
#define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val)
|
||||
|
||||
/* USB Channel 3 Config Registers */
|
||||
|
||||
#define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL)
|
||||
#define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val)
|
||||
#define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW)
|
||||
#define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val)
|
||||
#define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH)
|
||||
#define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val)
|
||||
#define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW)
|
||||
#define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val)
|
||||
#define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH)
|
||||
#define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val)
|
||||
|
||||
/* USB Channel 4 Config Registers */
|
||||
|
||||
#define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL)
|
||||
#define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val)
|
||||
#define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW)
|
||||
#define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val)
|
||||
#define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH)
|
||||
#define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val)
|
||||
#define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW)
|
||||
#define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val)
|
||||
#define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH)
|
||||
#define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val)
|
||||
|
||||
/* USB Channel 5 Config Registers */
|
||||
|
||||
#define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL)
|
||||
#define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val)
|
||||
#define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW)
|
||||
#define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val)
|
||||
#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH)
|
||||
#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val)
|
||||
#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW)
|
||||
#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val)
|
||||
#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH)
|
||||
#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val)
|
||||
|
||||
/* USB Channel 6 Config Registers */
|
||||
|
||||
#define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL)
|
||||
#define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val)
|
||||
#define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW)
|
||||
#define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val)
|
||||
#define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH)
|
||||
#define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val)
|
||||
#define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW)
|
||||
#define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val)
|
||||
#define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH)
|
||||
#define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val)
|
||||
|
||||
/* USB Channel 7 Config Registers */
|
||||
|
||||
#define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL)
|
||||
#define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val)
|
||||
#define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW)
|
||||
#define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val)
|
||||
#define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH)
|
||||
#define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val)
|
||||
#define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW)
|
||||
#define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val)
|
||||
#define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH)
|
||||
#define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val)
|
||||
|
||||
#endif /* _CDEF_BF527_H */
|
||||
1187
include/asm-blackfin/mach-bf527/cdefBF52x_base.h
Normal file
1187
include/asm-blackfin/mach-bf527/cdefBF52x_base.h
Normal file
File diff suppressed because it is too large
Load Diff
42
include/asm-blackfin/mach-bf527/defBF522.h
Normal file
42
include/asm-blackfin/mach-bf527/defBF522.h
Normal file
@ -0,0 +1,42 @@
|
||||
/*
|
||||
* File: include/asm-blackfin/mach-bf527/defBF522.h
|
||||
* Based on:
|
||||
* Author:
|
||||
*
|
||||
* Created:
|
||||
* Description:
|
||||
*
|
||||
* Rev:
|
||||
*
|
||||
* Modified:
|
||||
*
|
||||
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING.
|
||||
* If not, write to the Free Software Foundation,
|
||||
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
*/
|
||||
|
||||
#ifndef _DEF_BF522_H
|
||||
#define _DEF_BF522_H
|
||||
|
||||
/* Include all Core registers and bit definitions */
|
||||
#include <asm/mach-common/def_LPBlackfin.h>
|
||||
|
||||
/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF522 */
|
||||
|
||||
/* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
|
||||
#include "defBF52x_base.h"
|
||||
|
||||
#endif /* _DEF_BF522_H */
|
||||
713
include/asm-blackfin/mach-bf527/defBF525.h
Normal file
713
include/asm-blackfin/mach-bf527/defBF525.h
Normal file
@ -0,0 +1,713 @@
|
||||
/*
|
||||
* File: include/asm-blackfin/mach-bf527/defBF525.h
|
||||
* Based on:
|
||||
* Author:
|
||||
*
|
||||
* Created:
|
||||
* Description:
|
||||
*
|
||||
* Rev:
|
||||
*
|
||||
* Modified:
|
||||
*
|
||||
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING.
|
||||
* If not, write to the Free Software Foundation,
|
||||
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
*/
|
||||
|
||||
#ifndef _DEF_BF525_H
|
||||
#define _DEF_BF525_H
|
||||
|
||||
/* Include all Core registers and bit definitions */
|
||||
#include <asm/mach-common/def_LPBlackfin.h>
|
||||
|
||||
/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF525 */
|
||||
|
||||
/* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
|
||||
#include "defBF52x_base.h"
|
||||
|
||||
/* The following are the #defines needed by ADSP-BF525 that are not in the common header */
|
||||
|
||||
/* USB Control Registers */
|
||||
|
||||
#define USB_FADDR 0xffc03800 /* Function address register */
|
||||
#define USB_POWER 0xffc03804 /* Power management register */
|
||||
#define USB_INTRTX 0xffc03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
|
||||
#define USB_INTRRX 0xffc0380c /* Interrupt register for Rx endpoints 1 to 7 */
|
||||
#define USB_INTRTXE 0xffc03810 /* Interrupt enable register for IntrTx */
|
||||
#define USB_INTRRXE 0xffc03814 /* Interrupt enable register for IntrRx */
|
||||
#define USB_INTRUSB 0xffc03818 /* Interrupt register for common USB interrupts */
|
||||
#define USB_INTRUSBE 0xffc0381c /* Interrupt enable register for IntrUSB */
|
||||
#define USB_FRAME 0xffc03820 /* USB frame number */
|
||||
#define USB_INDEX 0xffc03824 /* Index register for selecting the indexed endpoint registers */
|
||||
#define USB_TESTMODE 0xffc03828 /* Enabled USB 20 test modes */
|
||||
#define USB_GLOBINTR 0xffc0382c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
|
||||
#define USB_GLOBAL_CTL 0xffc03830 /* Global Clock Control for the core */
|
||||
|
||||
/* USB Packet Control Registers */
|
||||
|
||||
#define USB_TX_MAX_PACKET 0xffc03840 /* Maximum packet size for Host Tx endpoint */
|
||||
#define USB_CSR0 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
|
||||
#define USB_TXCSR 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
|
||||
#define USB_RX_MAX_PACKET 0xffc03848 /* Maximum packet size for Host Rx endpoint */
|
||||
#define USB_RXCSR 0xffc0384c /* Control Status register for Host Rx endpoint */
|
||||
#define USB_COUNT0 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
|
||||
#define USB_RXCOUNT 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
|
||||
#define USB_TXTYPE 0xffc03854 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
|
||||
#define USB_NAKLIMIT0 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
|
||||
#define USB_TXINTERVAL 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
|
||||
#define USB_RXTYPE 0xffc0385c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
|
||||
#define USB_RXINTERVAL 0xffc03860 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
|
||||
#define USB_TXCOUNT 0xffc03868 /* Number of bytes to be written to the selected endpoint Tx FIFO */
|
||||
|
||||
/* USB Endpoint FIFO Registers */
|
||||
|
||||
#define USB_EP0_FIFO 0xffc03880 /* Endpoint 0 FIFO */
|
||||
#define USB_EP1_FIFO 0xffc03888 /* Endpoint 1 FIFO */
|
||||
#define USB_EP2_FIFO 0xffc03890 /* Endpoint 2 FIFO */
|
||||
#define USB_EP3_FIFO 0xffc03898 /* Endpoint 3 FIFO */
|
||||
#define USB_EP4_FIFO 0xffc038a0 /* Endpoint 4 FIFO */
|
||||
#define USB_EP5_FIFO 0xffc038a8 /* Endpoint 5 FIFO */
|
||||
#define USB_EP6_FIFO 0xffc038b0 /* Endpoint 6 FIFO */
|
||||
#define USB_EP7_FIFO 0xffc038b8 /* Endpoint 7 FIFO */
|
||||
|
||||
/* USB OTG Control Registers */
|
||||
|
||||
#define USB_OTG_DEV_CTL 0xffc03900 /* OTG Device Control Register */
|
||||
#define USB_OTG_VBUS_IRQ 0xffc03904 /* OTG VBUS Control Interrupts */
|
||||
#define USB_OTG_VBUS_MASK 0xffc03908 /* VBUS Control Interrupt Enable */
|
||||
|
||||
/* USB Phy Control Registers */
|
||||
|
||||
#define USB_LINKINFO 0xffc03948 /* Enables programming of some PHY-side delays */
|
||||
#define USB_VPLEN 0xffc0394c /* Determines duration of VBUS pulse for VBUS charging */
|
||||
#define USB_HS_EOF1 0xffc03950 /* Time buffer for High-Speed transactions */
|
||||
#define USB_FS_EOF1 0xffc03954 /* Time buffer for Full-Speed transactions */
|
||||
#define USB_LS_EOF1 0xffc03958 /* Time buffer for Low-Speed transactions */
|
||||
|
||||
/* (APHY_CNTRL is for ADI usage only) */
|
||||
|
||||
#define USB_APHY_CNTRL 0xffc039e0 /* Register that increases visibility of Analog PHY */
|
||||
|
||||
/* (APHY_CALIB is for ADI usage only) */
|
||||
|
||||
#define USB_APHY_CALIB 0xffc039e4 /* Register used to set some calibration values */
|
||||
|
||||
#define USB_APHY_CNTRL2 0xffc039e8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
|
||||
|
||||
/* (PHY_TEST is for ADI usage only) */
|
||||
|
||||
#define USB_PHY_TEST 0xffc039ec /* Used for reducing simulation time and simplifies FIFO testability */
|
||||
|
||||
#define USB_PLLOSC_CTRL 0xffc039f0 /* Used to program different parameters for USB PLL and Oscillator */
|
||||
#define USB_SRP_CLKDIV 0xffc039f4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
|
||||
|
||||
/* USB Endpoint 0 Control Registers */
|
||||
|
||||
#define USB_EP_NI0_TXMAXP 0xffc03a00 /* Maximum packet size for Host Tx endpoint0 */
|
||||
#define USB_EP_NI0_TXCSR 0xffc03a04 /* Control Status register for endpoint 0 */
|
||||
#define USB_EP_NI0_RXMAXP 0xffc03a08 /* Maximum packet size for Host Rx endpoint0 */
|
||||
#define USB_EP_NI0_RXCSR 0xffc03a0c /* Control Status register for Host Rx endpoint0 */
|
||||
#define USB_EP_NI0_RXCOUNT 0xffc03a10 /* Number of bytes received in endpoint 0 FIFO */
|
||||
#define USB_EP_NI0_TXTYPE 0xffc03a14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
|
||||
#define USB_EP_NI0_TXINTERVAL 0xffc03a18 /* Sets the NAK response timeout on Endpoint 0 */
|
||||
#define USB_EP_NI0_RXTYPE 0xffc03a1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
|
||||
#define USB_EP_NI0_RXINTERVAL 0xffc03a20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
|
||||
#define USB_EP_NI0_TXCOUNT 0xffc03a28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
|
||||
|
||||
/* USB Endpoint 1 Control Registers */
|
||||
|
||||
#define USB_EP_NI1_TXMAXP 0xffc03a40 /* Maximum packet size for Host Tx endpoint1 */
|
||||
#define USB_EP_NI1_TXCSR 0xffc03a44 /* Control Status register for endpoint1 */
|
||||
#define USB_EP_NI1_RXMAXP 0xffc03a48 /* Maximum packet size for Host Rx endpoint1 */
|
||||
#define USB_EP_NI1_RXCSR 0xffc03a4c /* Control Status register for Host Rx endpoint1 */
|
||||
#define USB_EP_NI1_RXCOUNT 0xffc03a50 /* Number of bytes received in endpoint1 FIFO */
|
||||
#define USB_EP_NI1_TXTYPE 0xffc03a54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
|
||||
#define USB_EP_NI1_TXINTERVAL 0xffc03a58 /* Sets the NAK response timeout on Endpoint1 */
|
||||
#define USB_EP_NI1_RXTYPE 0xffc03a5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
|
||||
#define USB_EP_NI1_RXINTERVAL 0xffc03a60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
|
||||
#define USB_EP_NI1_TXCOUNT 0xffc03a68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
|
||||
|
||||
/* USB Endpoint 2 Control Registers */
|
||||
|
||||
#define USB_EP_NI2_TXMAXP 0xffc03a80 /* Maximum packet size for Host Tx endpoint2 */
|
||||
#define USB_EP_NI2_TXCSR 0xffc03a84 /* Control Status register for endpoint2 */
|
||||
#define USB_EP_NI2_RXMAXP 0xffc03a88 /* Maximum packet size for Host Rx endpoint2 */
|
||||
#define USB_EP_NI2_RXCSR 0xffc03a8c /* Control Status register for Host Rx endpoint2 */
|
||||
#define USB_EP_NI2_RXCOUNT 0xffc03a90 /* Number of bytes received in endpoint2 FIFO */
|
||||
#define USB_EP_NI2_TXTYPE 0xffc03a94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
|
||||
#define USB_EP_NI2_TXINTERVAL 0xffc03a98 /* Sets the NAK response timeout on Endpoint2 */
|
||||
#define USB_EP_NI2_RXTYPE 0xffc03a9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
|
||||
#define USB_EP_NI2_RXINTERVAL 0xffc03aa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
|
||||
#define USB_EP_NI2_TXCOUNT 0xffc03aa8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
|
||||
|
||||
/* USB Endpoint 3 Control Registers */
|
||||
|
||||
#define USB_EP_NI3_TXMAXP 0xffc03ac0 /* Maximum packet size for Host Tx endpoint3 */
|
||||
#define USB_EP_NI3_TXCSR 0xffc03ac4 /* Control Status register for endpoint3 */
|
||||
#define USB_EP_NI3_RXMAXP 0xffc03ac8 /* Maximum packet size for Host Rx endpoint3 */
|
||||
#define USB_EP_NI3_RXCSR 0xffc03acc /* Control Status register for Host Rx endpoint3 */
|
||||
#define USB_EP_NI3_RXCOUNT 0xffc03ad0 /* Number of bytes received in endpoint3 FIFO */
|
||||
#define USB_EP_NI3_TXTYPE 0xffc03ad4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
|
||||
#define USB_EP_NI3_TXINTERVAL 0xffc03ad8 /* Sets the NAK response timeout on Endpoint3 */
|
||||
#define USB_EP_NI3_RXTYPE 0xffc03adc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
|
||||
#define USB_EP_NI3_RXINTERVAL 0xffc03ae0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
|
||||
#define USB_EP_NI3_TXCOUNT 0xffc03ae8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
|
||||
|
||||
/* USB Endpoint 4 Control Registers */
|
||||
|
||||
#define USB_EP_NI4_TXMAXP 0xffc03b00 /* Maximum packet size for Host Tx endpoint4 */
|
||||
#define USB_EP_NI4_TXCSR 0xffc03b04 /* Control Status register for endpoint4 */
|
||||
#define USB_EP_NI4_RXMAXP 0xffc03b08 /* Maximum packet size for Host Rx endpoint4 */
|
||||
#define USB_EP_NI4_RXCSR 0xffc03b0c /* Control Status register for Host Rx endpoint4 */
|
||||
#define USB_EP_NI4_RXCOUNT 0xffc03b10 /* Number of bytes received in endpoint4 FIFO */
|
||||
#define USB_EP_NI4_TXTYPE 0xffc03b14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
|
||||
#define USB_EP_NI4_TXINTERVAL 0xffc03b18 /* Sets the NAK response timeout on Endpoint4 */
|
||||
#define USB_EP_NI4_RXTYPE 0xffc03b1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
|
||||
#define USB_EP_NI4_RXINTERVAL 0xffc03b20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
|
||||
#define USB_EP_NI4_TXCOUNT 0xffc03b28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
|
||||
|
||||
/* USB Endpoint 5 Control Registers */
|
||||
|
||||
#define USB_EP_NI5_TXMAXP 0xffc03b40 /* Maximum packet size for Host Tx endpoint5 */
|
||||
#define USB_EP_NI5_TXCSR 0xffc03b44 /* Control Status register for endpoint5 */
|
||||
#define USB_EP_NI5_RXMAXP 0xffc03b48 /* Maximum packet size for Host Rx endpoint5 */
|
||||
#define USB_EP_NI5_RXCSR 0xffc03b4c /* Control Status register for Host Rx endpoint5 */
|
||||
#define USB_EP_NI5_RXCOUNT 0xffc03b50 /* Number of bytes received in endpoint5 FIFO */
|
||||
#define USB_EP_NI5_TXTYPE 0xffc03b54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
|
||||
#define USB_EP_NI5_TXINTERVAL 0xffc03b58 /* Sets the NAK response timeout on Endpoint5 */
|
||||
#define USB_EP_NI5_RXTYPE 0xffc03b5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
|
||||
#define USB_EP_NI5_RXINTERVAL 0xffc03b60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
|
||||
#define USB_EP_NI5_TXCOUNT 0xffc03b68 /* Number of bytes to be written to the endpoint5 Tx FIFO */
|
||||
|
||||
/* USB Endpoint 6 Control Registers */
|
||||
|
||||
#define USB_EP_NI6_TXMAXP 0xffc03b80 /* Maximum packet size for Host Tx endpoint6 */
|
||||
#define USB_EP_NI6_TXCSR 0xffc03b84 /* Control Status register for endpoint6 */
|
||||
#define USB_EP_NI6_RXMAXP 0xffc03b88 /* Maximum packet size for Host Rx endpoint6 */
|
||||
#define USB_EP_NI6_RXCSR 0xffc03b8c /* Control Status register for Host Rx endpoint6 */
|
||||
#define USB_EP_NI6_RXCOUNT 0xffc03b90 /* Number of bytes received in endpoint6 FIFO */
|
||||
#define USB_EP_NI6_TXTYPE 0xffc03b94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
|
||||
#define USB_EP_NI6_TXINTERVAL 0xffc03b98 /* Sets the NAK response timeout on Endpoint6 */
|
||||
#define USB_EP_NI6_RXTYPE 0xffc03b9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
|
||||
#define USB_EP_NI6_RXINTERVAL 0xffc03ba0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
|
||||
#define USB_EP_NI6_TXCOUNT 0xffc03ba8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
|
||||
|
||||
/* USB Endpoint 7 Control Registers */
|
||||
|
||||
#define USB_EP_NI7_TXMAXP 0xffc03bc0 /* Maximum packet size for Host Tx endpoint7 */
|
||||
#define USB_EP_NI7_TXCSR 0xffc03bc4 /* Control Status register for endpoint7 */
|
||||
#define USB_EP_NI7_RXMAXP 0xffc03bc8 /* Maximum packet size for Host Rx endpoint7 */
|
||||
#define USB_EP_NI7_RXCSR 0xffc03bcc /* Control Status register for Host Rx endpoint7 */
|
||||
#define USB_EP_NI7_RXCOUNT 0xffc03bd0 /* Number of bytes received in endpoint7 FIFO */
|
||||
#define USB_EP_NI7_TXTYPE 0xffc03bd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
|
||||
#define USB_EP_NI7_TXINTERVAL 0xffc03bd8 /* Sets the NAK response timeout on Endpoint7 */
|
||||
#define USB_EP_NI7_RXTYPE 0xffc03bdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
|
||||
#define USB_EP_NI7_RXINTERVAL 0xffc03bf0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
|
||||
#define USB_EP_NI7_TXCOUNT 0xffc03bf8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
|
||||
|
||||
#define USB_DMA_INTERRUPT 0xffc03c00 /* Indicates pending interrupts for the DMA channels */
|
||||
|
||||
/* USB Channel 0 Config Registers */
|
||||
|
||||
#define USB_DMA0CONTROL 0xffc03c04 /* DMA master channel 0 configuration */
|
||||
#define USB_DMA0ADDRLOW 0xffc03c08 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
|
||||
#define USB_DMA0ADDRHIGH 0xffc03c0c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
|
||||
#define USB_DMA0COUNTLOW 0xffc03c10 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
|
||||
#define USB_DMA0COUNTHIGH 0xffc03c14 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
|
||||
|
||||
/* USB Channel 1 Config Registers */
|
||||
|
||||
#define USB_DMA1CONTROL 0xffc03c24 /* DMA master channel 1 configuration */
|
||||
#define USB_DMA1ADDRLOW 0xffc03c28 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
|
||||
#define USB_DMA1ADDRHIGH 0xffc03c2c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
|
||||
#define USB_DMA1COUNTLOW 0xffc03c30 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
|
||||
#define USB_DMA1COUNTHIGH 0xffc03c34 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
|
||||
|
||||
/* USB Channel 2 Config Registers */
|
||||
|
||||
#define USB_DMA2CONTROL 0xffc03c44 /* DMA master channel 2 configuration */
|
||||
#define USB_DMA2ADDRLOW 0xffc03c48 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
|
||||
#define USB_DMA2ADDRHIGH 0xffc03c4c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
|
||||
#define USB_DMA2COUNTLOW 0xffc03c50 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
|
||||
#define USB_DMA2COUNTHIGH 0xffc03c54 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
|
||||
|
||||
/* USB Channel 3 Config Registers */
|
||||
|
||||
#define USB_DMA3CONTROL 0xffc03c64 /* DMA master channel 3 configuration */
|
||||
#define USB_DMA3ADDRLOW 0xffc03c68 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
|
||||
#define USB_DMA3ADDRHIGH 0xffc03c6c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
|
||||
#define USB_DMA3COUNTLOW 0xffc03c70 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
|
||||
#define USB_DMA3COUNTHIGH 0xffc03c74 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
|
||||
|
||||
/* USB Channel 4 Config Registers */
|
||||
|
||||
#define USB_DMA4CONTROL 0xffc03c84 /* DMA master channel 4 configuration */
|
||||
#define USB_DMA4ADDRLOW 0xffc03c88 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
|
||||
#define USB_DMA4ADDRHIGH 0xffc03c8c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
|
||||
#define USB_DMA4COUNTLOW 0xffc03c90 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
|
||||
#define USB_DMA4COUNTHIGH 0xffc03c94 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
|
||||
|
||||
/* USB Channel 5 Config Registers */
|
||||
|
||||
#define USB_DMA5CONTROL 0xffc03ca4 /* DMA master channel 5 configuration */
|
||||
#define USB_DMA5ADDRLOW 0xffc03ca8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
|
||||
#define USB_DMA5ADDRHIGH 0xffc03cac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
|
||||
#define USB_DMA5COUNTLOW 0xffc03cb0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
|
||||
#define USB_DMA5COUNTHIGH 0xffc03cb4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
|
||||
|
||||
/* USB Channel 6 Config Registers */
|
||||
|
||||
#define USB_DMA6CONTROL 0xffc03cc4 /* DMA master channel 6 configuration */
|
||||
#define USB_DMA6ADDRLOW 0xffc03cc8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
|
||||
#define USB_DMA6ADDRHIGH 0xffc03ccc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
|
||||
#define USB_DMA6COUNTLOW 0xffc03cd0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
|
||||
#define USB_DMA6COUNTHIGH 0xffc03cd4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
|
||||
|
||||
/* USB Channel 7 Config Registers */
|
||||
|
||||
#define USB_DMA7CONTROL 0xffc03ce4 /* DMA master channel 7 configuration */
|
||||
#define USB_DMA7ADDRLOW 0xffc03ce8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
|
||||
#define USB_DMA7ADDRHIGH 0xffc03cec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
|
||||
#define USB_DMA7COUNTLOW 0xffc03cf0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
|
||||
#define USB_DMA7COUNTHIGH 0xffc03cf4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
|
||||
|
||||
/* Bit masks for USB_FADDR */
|
||||
|
||||
#define FUNCTION_ADDRESS 0x7f /* Function address */
|
||||
|
||||
/* Bit masks for USB_POWER */
|
||||
|
||||
#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
|
||||
#define nENABLE_SUSPENDM 0x0
|
||||
#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
|
||||
#define nSUSPEND_MODE 0x0
|
||||
#define RESUME_MODE 0x4 /* DMA Mode */
|
||||
#define nRESUME_MODE 0x0
|
||||
#define RESET 0x8 /* Reset indicator */
|
||||
#define nRESET 0x0
|
||||
#define HS_MODE 0x10 /* High Speed mode indicator */
|
||||
#define nHS_MODE 0x0
|
||||
#define HS_ENABLE 0x20 /* high Speed Enable */
|
||||
#define nHS_ENABLE 0x0
|
||||
#define SOFT_CONN 0x40 /* Soft connect */
|
||||
#define nSOFT_CONN 0x0
|
||||
#define ISO_UPDATE 0x80 /* Isochronous update */
|
||||
#define nISO_UPDATE 0x0
|
||||
|
||||
/* Bit masks for USB_INTRTX */
|
||||
|
||||
#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
|
||||
#define nEP0_TX 0x0
|
||||
#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
|
||||
#define nEP1_TX 0x0
|
||||
#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
|
||||
#define nEP2_TX 0x0
|
||||
#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
|
||||
#define nEP3_TX 0x0
|
||||
#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
|
||||
#define nEP4_TX 0x0
|
||||
#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
|
||||
#define nEP5_TX 0x0
|
||||
#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
|
||||
#define nEP6_TX 0x0
|
||||
#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
|
||||
#define nEP7_TX 0x0
|
||||
|
||||
/* Bit masks for USB_INTRRX */
|
||||
|
||||
#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
|
||||
#define nEP1_RX 0x0
|
||||
#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
|
||||
#define nEP2_RX 0x0
|
||||
#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
|
||||
#define nEP3_RX 0x0
|
||||
#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
|
||||
#define nEP4_RX 0x0
|
||||
#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
|
||||
#define nEP5_RX 0x0
|
||||
#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
|
||||
#define nEP6_RX 0x0
|
||||
#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
|
||||
#define nEP7_RX 0x0
|
||||
|
||||
/* Bit masks for USB_INTRTXE */
|
||||
|
||||
#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
|
||||
#define nEP0_TX_E 0x0
|
||||
#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
|
||||
#define nEP1_TX_E 0x0
|
||||
#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
|
||||
#define nEP2_TX_E 0x0
|
||||
#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
|
||||
#define nEP3_TX_E 0x0
|
||||
#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
|
||||
#define nEP4_TX_E 0x0
|
||||
#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
|
||||
#define nEP5_TX_E 0x0
|
||||
#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
|
||||
#define nEP6_TX_E 0x0
|
||||
#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
|
||||
#define nEP7_TX_E 0x0
|
||||
|
||||
/* Bit masks for USB_INTRRXE */
|
||||
|
||||
#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
|
||||
#define nEP1_RX_E 0x0
|
||||
#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
|
||||
#define nEP2_RX_E 0x0
|
||||
#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
|
||||
#define nEP3_RX_E 0x0
|
||||
#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
|
||||
#define nEP4_RX_E 0x0
|
||||
#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
|
||||
#define nEP5_RX_E 0x0
|
||||
#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
|
||||
#define nEP6_RX_E 0x0
|
||||
#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
|
||||
#define nEP7_RX_E 0x0
|
||||
|
||||
/* Bit masks for USB_INTRUSB */
|
||||
|
||||
#define SUSPEND_B 0x1 /* Suspend indicator */
|
||||
#define nSUSPEND_B 0x0
|
||||
#define RESUME_B 0x2 /* Resume indicator */
|
||||
#define nRESUME_B 0x0
|
||||
#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
|
||||
#define nRESET_OR_BABLE_B 0x0
|
||||
#define SOF_B 0x8 /* Start of frame */
|
||||
#define nSOF_B 0x0
|
||||
#define CONN_B 0x10 /* Connection indicator */
|
||||
#define nCONN_B 0x0
|
||||
#define DISCON_B 0x20 /* Disconnect indicator */
|
||||
#define nDISCON_B 0x0
|
||||
#define SESSION_REQ_B 0x40 /* Session Request */
|
||||
#define nSESSION_REQ_B 0x0
|
||||
#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
|
||||
#define nVBUS_ERROR_B 0x0
|
||||
|
||||
/* Bit masks for USB_INTRUSBE */
|
||||
|
||||
#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
|
||||
#define nSUSPEND_BE 0x0
|
||||
#define RESUME_BE 0x2 /* Resume indicator int enable */
|
||||
#define nRESUME_BE 0x0
|
||||
#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
|
||||
#define nRESET_OR_BABLE_BE 0x0
|
||||
#define SOF_BE 0x8 /* Start of frame int enable */
|
||||
#define nSOF_BE 0x0
|
||||
#define CONN_BE 0x10 /* Connection indicator int enable */
|
||||
#define nCONN_BE 0x0
|
||||
#define DISCON_BE 0x20 /* Disconnect indicator int enable */
|
||||
#define nDISCON_BE 0x0
|
||||
#define SESSION_REQ_BE 0x40 /* Session Request int enable */
|
||||
#define nSESSION_REQ_BE 0x0
|
||||
#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
|
||||
#define nVBUS_ERROR_BE 0x0
|
||||
|
||||
/* Bit masks for USB_FRAME */
|
||||
|
||||
#define FRAME_NUMBER 0x7ff /* Frame number */
|
||||
|
||||
/* Bit masks for USB_INDEX */
|
||||
|
||||
#define SELECTED_ENDPOINT 0xf /* selected endpoint */
|
||||
|
||||
/* Bit masks for USB_GLOBAL_CTL */
|
||||
|
||||
#define GLOBAL_ENA 0x1 /* enables USB module */
|
||||
#define nGLOBAL_ENA 0x0
|
||||
#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
|
||||
#define nEP1_TX_ENA 0x0
|
||||
#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
|
||||
#define nEP2_TX_ENA 0x0
|
||||
#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
|
||||
#define nEP3_TX_ENA 0x0
|
||||
#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
|
||||
#define nEP4_TX_ENA 0x0
|
||||
#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
|
||||
#define nEP5_TX_ENA 0x0
|
||||
#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
|
||||
#define nEP6_TX_ENA 0x0
|
||||
#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
|
||||
#define nEP7_TX_ENA 0x0
|
||||
#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
|
||||
#define nEP1_RX_ENA 0x0
|
||||
#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
|
||||
#define nEP2_RX_ENA 0x0
|
||||
#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
|
||||
#define nEP3_RX_ENA 0x0
|
||||
#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
|
||||
#define nEP4_RX_ENA 0x0
|
||||
#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
|
||||
#define nEP5_RX_ENA 0x0
|
||||
#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
|
||||
#define nEP6_RX_ENA 0x0
|
||||
#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
|
||||
#define nEP7_RX_ENA 0x0
|
||||
|
||||
/* Bit masks for USB_OTG_DEV_CTL */
|
||||
|
||||
#define SESSION 0x1 /* session indicator */
|
||||
#define nSESSION 0x0
|
||||
#define HOST_REQ 0x2 /* Host negotiation request */
|
||||
#define nHOST_REQ 0x0
|
||||
#define HOST_MODE 0x4 /* indicates USBDRC is a host */
|
||||
#define nHOST_MODE 0x0
|
||||
#define VBUS0 0x8 /* Vbus level indicator[0] */
|
||||
#define nVBUS0 0x0
|
||||
#define VBUS1 0x10 /* Vbus level indicator[1] */
|
||||
#define nVBUS1 0x0
|
||||
#define LSDEV 0x20 /* Low-speed indicator */
|
||||
#define nLSDEV 0x0
|
||||
#define FSDEV 0x40 /* Full or High-speed indicator */
|
||||
#define nFSDEV 0x0
|
||||
#define B_DEVICE 0x80 /* A' or 'B' device indicator */
|
||||
#define nB_DEVICE 0x0
|
||||
|
||||
/* Bit masks for USB_OTG_VBUS_IRQ */
|
||||
|
||||
#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
|
||||
#define nDRIVE_VBUS_ON 0x0
|
||||
#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
|
||||
#define nDRIVE_VBUS_OFF 0x0
|
||||
#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
|
||||
#define nCHRG_VBUS_START 0x0
|
||||
#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
|
||||
#define nCHRG_VBUS_END 0x0
|
||||
#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
|
||||
#define nDISCHRG_VBUS_START 0x0
|
||||
#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
|
||||
#define nDISCHRG_VBUS_END 0x0
|
||||
|
||||
/* Bit masks for USB_OTG_VBUS_MASK */
|
||||
|
||||
#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
|
||||
#define nDRIVE_VBUS_ON_ENA 0x0
|
||||
#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
|
||||
#define nDRIVE_VBUS_OFF_ENA 0x0
|
||||
#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
|
||||
#define nCHRG_VBUS_START_ENA 0x0
|
||||
#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
|
||||
#define nCHRG_VBUS_END_ENA 0x0
|
||||
#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
|
||||
#define nDISCHRG_VBUS_START_ENA 0x0
|
||||
#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
|
||||
#define nDISCHRG_VBUS_END_ENA 0x0
|
||||
|
||||
/* Bit masks for USB_CSR0 */
|
||||
|
||||
#define RXPKTRDY 0x1 /* data packet receive indicator */
|
||||
#define nRXPKTRDY 0x0
|
||||
#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
|
||||
#define nTXPKTRDY 0x0
|
||||
#define STALL_SENT 0x4 /* STALL handshake sent */
|
||||
#define nSTALL_SENT 0x0
|
||||
#define DATAEND 0x8 /* Data end indicator */
|
||||
#define nDATAEND 0x0
|
||||
#define SETUPEND 0x10 /* Setup end */
|
||||
#define nSETUPEND 0x0
|
||||
#define SENDSTALL 0x20 /* Send STALL handshake */
|
||||
#define nSENDSTALL 0x0
|
||||
#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
|
||||
#define nSERVICED_RXPKTRDY 0x0
|
||||
#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
|
||||
#define nSERVICED_SETUPEND 0x0
|
||||
#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
|
||||
#define nFLUSHFIFO 0x0
|
||||
#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
|
||||
#define nSTALL_RECEIVED_H 0x0
|
||||
#define SETUPPKT_H 0x8 /* send Setup token host mode */
|
||||
#define nSETUPPKT_H 0x0
|
||||
#define ERROR_H 0x10 /* timeout error indicator host mode */
|
||||
#define nERROR_H 0x0
|
||||
#define REQPKT_H 0x20 /* Request an IN transaction host mode */
|
||||
#define nREQPKT_H 0x0
|
||||
#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
|
||||
#define nSTATUSPKT_H 0x0
|
||||
#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
|
||||
#define nNAK_TIMEOUT_H 0x0
|
||||
|
||||
/* Bit masks for USB_COUNT0 */
|
||||
|
||||
#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
|
||||
|
||||
/* Bit masks for USB_NAKLIMIT0 */
|
||||
|
||||
#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
|
||||
|
||||
/* Bit masks for USB_TX_MAX_PACKET */
|
||||
|
||||
#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
|
||||
|
||||
/* Bit masks for USB_RX_MAX_PACKET */
|
||||
|
||||
#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
|
||||
|
||||
/* Bit masks for USB_TXCSR */
|
||||
|
||||
#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
|
||||
#define nTXPKTRDY_T 0x0
|
||||
#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
|
||||
#define nFIFO_NOT_EMPTY_T 0x0
|
||||
#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
|
||||
#define nUNDERRUN_T 0x0
|
||||
#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
|
||||
#define nFLUSHFIFO_T 0x0
|
||||
#define STALL_SEND_T 0x10 /* issue a Stall handshake */
|
||||
#define nSTALL_SEND_T 0x0
|
||||
#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
|
||||
#define nSTALL_SENT_T 0x0
|
||||
#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
|
||||
#define nCLEAR_DATATOGGLE_T 0x0
|
||||
#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
|
||||
#define nINCOMPTX_T 0x0
|
||||
#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
|
||||
#define nDMAREQMODE_T 0x0
|
||||
#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
|
||||
#define nFORCE_DATATOGGLE_T 0x0
|
||||
#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
|
||||
#define nDMAREQ_ENA_T 0x0
|
||||
#define ISO_T 0x4000 /* enable Isochronous transfers */
|
||||
#define nISO_T 0x0
|
||||
#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
|
||||
#define nAUTOSET_T 0x0
|
||||
#define ERROR_TH 0x4 /* error condition host mode */
|
||||
#define nERROR_TH 0x0
|
||||
#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
|
||||
#define nSTALL_RECEIVED_TH 0x0
|
||||
#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
|
||||
#define nNAK_TIMEOUT_TH 0x0
|
||||
|
||||
/* Bit masks for USB_TXCOUNT */
|
||||
|
||||
#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
|
||||
|
||||
/* Bit masks for USB_RXCSR */
|
||||
|
||||
#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
|
||||
#define nRXPKTRDY_R 0x0
|
||||
#define FIFO_FULL_R 0x2 /* FIFO not empty */
|
||||
#define nFIFO_FULL_R 0x0
|
||||
#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
|
||||
#define nOVERRUN_R 0x0
|
||||
#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
|
||||
#define nDATAERROR_R 0x0
|
||||
#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
|
||||
#define nFLUSHFIFO_R 0x0
|
||||
#define STALL_SEND_R 0x20 /* issue a Stall handshake */
|
||||
#define nSTALL_SEND_R 0x0
|
||||
#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
|
||||
#define nSTALL_SENT_R 0x0
|
||||
#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
|
||||
#define nCLEAR_DATATOGGLE_R 0x0
|
||||
#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
|
||||
#define nINCOMPRX_R 0x0
|
||||
#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
|
||||
#define nDMAREQMODE_R 0x0
|
||||
#define DISNYET_R 0x1000 /* disable Nyet handshakes */
|
||||
#define nDISNYET_R 0x0
|
||||
#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
|
||||
#define nDMAREQ_ENA_R 0x0
|
||||
#define ISO_R 0x4000 /* enable Isochronous transfers */
|
||||
#define nISO_R 0x0
|
||||
#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
|
||||
#define nAUTOCLEAR_R 0x0
|
||||
#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
|
||||
#define nERROR_RH 0x0
|
||||
#define REQPKT_RH 0x20 /* request an IN transaction host mode */
|
||||
#define nREQPKT_RH 0x0
|
||||
#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
|
||||
#define nSTALL_RECEIVED_RH 0x0
|
||||
#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
|
||||
#define nINCOMPRX_RH 0x0
|
||||
#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
|
||||
#define nDMAREQMODE_RH 0x0
|
||||
#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
|
||||
#define nAUTOREQ_RH 0x0
|
||||
|
||||
/* Bit masks for USB_RXCOUNT */
|
||||
|
||||
#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
|
||||
|
||||
/* Bit masks for USB_TXTYPE */
|
||||
|
||||
#define TARGET_EP_NO_T 0xf /* EP number */
|
||||
#define PROTOCOL_T 0xc /* transfer type */
|
||||
|
||||
/* Bit masks for USB_TXINTERVAL */
|
||||
|
||||
#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
|
||||
|
||||
/* Bit masks for USB_RXTYPE */
|
||||
|
||||
#define TARGET_EP_NO_R 0xf /* EP number */
|
||||
#define PROTOCOL_R 0xc /* transfer type */
|
||||
|
||||
/* Bit masks for USB_RXINTERVAL */
|
||||
|
||||
#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
|
||||
|
||||
/* Bit masks for USB_DMA_INTERRUPT */
|
||||
|
||||
#define DMA0_INT 0x1 /* DMA0 pending interrupt */
|
||||
#define nDMA0_INT 0x0
|
||||
#define DMA1_INT 0x2 /* DMA1 pending interrupt */
|
||||
#define nDMA1_INT 0x0
|
||||
#define DMA2_INT 0x4 /* DMA2 pending interrupt */
|
||||
#define nDMA2_INT 0x0
|
||||
#define DMA3_INT 0x8 /* DMA3 pending interrupt */
|
||||
#define nDMA3_INT 0x0
|
||||
#define DMA4_INT 0x10 /* DMA4 pending interrupt */
|
||||
#define nDMA4_INT 0x0
|
||||
#define DMA5_INT 0x20 /* DMA5 pending interrupt */
|
||||
#define nDMA5_INT 0x0
|
||||
#define DMA6_INT 0x40 /* DMA6 pending interrupt */
|
||||
#define nDMA6_INT 0x0
|
||||
#define DMA7_INT 0x80 /* DMA7 pending interrupt */
|
||||
#define nDMA7_INT 0x0
|
||||
|
||||
/* Bit masks for USB_DMAxCONTROL */
|
||||
|
||||
#define DMA_ENA 0x1 /* DMA enable */
|
||||
#define nDMA_ENA 0x0
|
||||
#define DIRECTION 0x2 /* direction of DMA transfer */
|
||||
#define nDIRECTION 0x0
|
||||
#define MODE 0x4 /* DMA Bus error */
|
||||
#define nMODE 0x0
|
||||
#define INT_ENA 0x8 /* Interrupt enable */
|
||||
#define nINT_ENA 0x0
|
||||
#define EPNUM 0xf0 /* EP number */
|
||||
#define BUSERROR 0x100 /* DMA Bus error */
|
||||
#define nBUSERROR 0x0
|
||||
|
||||
/* Bit masks for USB_DMAxADDRHIGH */
|
||||
|
||||
#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
|
||||
|
||||
/* Bit masks for USB_DMAxADDRLOW */
|
||||
|
||||
#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
|
||||
|
||||
/* Bit masks for USB_DMAxCOUNTHIGH */
|
||||
|
||||
#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
|
||||
|
||||
/* Bit masks for USB_DMAxCOUNTLOW */
|
||||
|
||||
#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
|
||||
|
||||
#endif /* _DEF_BF525_H */
|
||||
1089
include/asm-blackfin/mach-bf527/defBF527.h
Normal file
1089
include/asm-blackfin/mach-bf527/defBF527.h
Normal file
File diff suppressed because it is too large
Load Diff
2009
include/asm-blackfin/mach-bf527/defBF52x_base.h
Normal file
2009
include/asm-blackfin/mach-bf527/defBF52x_base.h
Normal file
File diff suppressed because it is too large
Load Diff
@ -51,10 +51,6 @@
|
||||
#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
|
||||
#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val)
|
||||
#define bfin_read_CHIPID() bfin_read32(CHIPID)
|
||||
#define bfin_read_SWRST() bfin_read16(SWRST)
|
||||
#define bfin_write_SWRST(val) bfin_write16(SWRST,val)
|
||||
#define bfin_read_SYSCR() bfin_read16(SYSCR)
|
||||
#define bfin_write_SYSCR(val) bfin_write16(SYSCR,val)
|
||||
#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
|
||||
#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
|
||||
#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
|
||||
@ -78,6 +74,10 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
|
||||
}
|
||||
|
||||
/* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */
|
||||
#define bfin_read_SWRST() bfin_read16(SWRST)
|
||||
#define bfin_write_SWRST(val) bfin_write16(SWRST,val)
|
||||
#define bfin_read_SYSCR() bfin_read16(SYSCR)
|
||||
#define bfin_write_SYSCR(val) bfin_write16(SYSCR,val)
|
||||
#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
|
||||
#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val)
|
||||
#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
|
||||
@ -117,6 +117,18 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
|
||||
#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
|
||||
#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN,val)
|
||||
|
||||
/* DMA Traffic controls */
|
||||
#define bfin_read_DMA_TCPER() bfin_read16(DMA_TCPER)
|
||||
#define bfin_write_DMA_TCPER(val) bfin_write16(DMA_TCPER,val)
|
||||
#define bfin_read_DMA_TCCNT() bfin_read16(DMA_TCCNT)
|
||||
#define bfin_write_DMA_TCCNT(val) bfin_write16(DMA_TCCNT,val)
|
||||
|
||||
/* Alternate deprecated register names (below) provided for backwards code compatibility */
|
||||
#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER)
|
||||
#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER,val)
|
||||
#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT)
|
||||
#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT,val)
|
||||
|
||||
/* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */
|
||||
#define bfin_read_FIO_DIR() bfin_read16(FIO_DIR)
|
||||
#define bfin_write_FIO_DIR(val) bfin_write16(FIO_DIR,val)
|
||||
@ -153,16 +165,6 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
|
||||
#define bfin_read_FIO_MASKB_T() bfin_read16(FIO_MASKB_T)
|
||||
#define bfin_write_FIO_MASKB_T(val) bfin_write16(FIO_MASKB_T,val)
|
||||
|
||||
/* DMA Traffic controls */
|
||||
#define bfin_read_DMA_TCPER() bfin_read16(DMA_TCPER)
|
||||
#define bfin_write_DMA_TCPER(val) bfin_write16(DMA_TCPER,val)
|
||||
#define bfin_read_DMA_TCCNT() bfin_read16(DMA_TCCNT)
|
||||
#define bfin_write_DMA_TCCNT(val) bfin_write16(DMA_TCCNT,val)
|
||||
#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER)
|
||||
#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER,val)
|
||||
#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT)
|
||||
#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT,val)
|
||||
|
||||
/* DMA Controller */
|
||||
#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
|
||||
#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG,val)
|
||||
|
||||
@ -46,11 +46,7 @@
|
||||
|
||||
#ifndef _DEF_BF532_H
|
||||
#define _DEF_BF532_H
|
||||
/*
|
||||
#if !defined(__ADSPLPBLACKFIN__)
|
||||
#warning defBF532.h should only be included for 532 compatible chips
|
||||
#endif
|
||||
*/
|
||||
|
||||
/* include all Core registers and bit definitions */
|
||||
#include <asm/mach-common/def_LPBlackfin.h>
|
||||
|
||||
@ -65,10 +61,10 @@
|
||||
#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */
|
||||
#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */
|
||||
#define CHIPID 0xFFC00014 /* Chip ID Register */
|
||||
#define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */
|
||||
#define SYSCR 0xFFC00104 /* System Configuration registe */
|
||||
|
||||
/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
|
||||
#define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */
|
||||
#define SYSCR 0xFFC00104 /* System Configuration registe */
|
||||
#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
|
||||
#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */
|
||||
#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
|
||||
@ -218,11 +214,13 @@
|
||||
#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
|
||||
|
||||
/* DMA Traffic controls */
|
||||
#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */
|
||||
#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */
|
||||
#define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
|
||||
#define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
|
||||
|
||||
/* Alternate deprecated register names (below) provided for backwards code compatibility */
|
||||
#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */
|
||||
#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */
|
||||
|
||||
/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
|
||||
#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
|
||||
#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
|
||||
@ -407,14 +405,25 @@
|
||||
/* ********************* PLL AND RESET MASKS ************************ */
|
||||
|
||||
/* PLL_CTL Masks */
|
||||
#define PLL_CLKIN 0x00000000 /* Pass CLKIN to PLL */
|
||||
#define PLL_CLKIN_DIV2 0x00000001 /* Pass CLKIN/2 to PLL */
|
||||
#define PLL_OFF 0x00000002 /* Shut off PLL clocks */
|
||||
#define STOPCK_OFF 0x00000008 /* Core clock off */
|
||||
#define PDWN 0x00000020 /* Put the PLL in a Deep Sleep state */
|
||||
#define BYPASS 0x00000100 /* Bypass the PLL */
|
||||
#define PLL_CLKIN 0x0000 /* Pass CLKIN to PLL */
|
||||
#define PLL_CLKIN_DIV2 0x0001 /* Pass CLKIN/2 to PLL */
|
||||
#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
|
||||
#define PLL_OFF 0x0002 /* Shut off PLL clocks */
|
||||
#define STOPCK_OFF 0x0008 /* Core clock off */
|
||||
#define STOPCK 0x0008 /* Core Clock Off */
|
||||
#define PDWN 0x0020 /* Put the PLL in a Deep Sleep state */
|
||||
#if !defined(__ADSPBF538__)
|
||||
/* this file is included in defBF538.h but IN_DELAY/OUT_DELAY are different */
|
||||
# define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */
|
||||
# define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */
|
||||
#endif
|
||||
#define BYPASS 0x0100 /* Bypass the PLL */
|
||||
/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */
|
||||
#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
|
||||
|
||||
/* PLL_DIV Masks */
|
||||
#define SSEL 0x000F /* System Select */
|
||||
#define CSEL 0x0030 /* Core Select */
|
||||
|
||||
#define SCLK_DIV(x) (x) /* SCLK = VCO / x */
|
||||
|
||||
@ -422,6 +431,8 @@
|
||||
#define CCLK_DIV2 0x00000010 /* CCLK = VCO / 2 */
|
||||
#define CCLK_DIV4 0x00000020 /* CCLK = VCO / 4 */
|
||||
#define CCLK_DIV8 0x00000030 /* CCLK = VCO / 8 */
|
||||
/* PLL_DIV Macros */
|
||||
#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
|
||||
|
||||
/* PLL_STAT Masks */
|
||||
#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
|
||||
@ -429,13 +440,47 @@
|
||||
#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
|
||||
#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
|
||||
|
||||
/* VR_CTL Masks */
|
||||
#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */
|
||||
#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
|
||||
#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
|
||||
#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
|
||||
#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
|
||||
|
||||
#define GAIN 0x000C /* Voltage Level Gain */
|
||||
#define GAIN_5 0x0000 /* GAIN = 5 */
|
||||
#define GAIN_10 0x0004 /* GAIN = 10 */
|
||||
#define GAIN_20 0x0008 /* GAIN = 20 */
|
||||
#define GAIN_50 0x000C /* GAIN = 50 */
|
||||
|
||||
#define VLEV 0x00F0 /* Internal Voltage Level */
|
||||
#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
|
||||
#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
|
||||
#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
|
||||
#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
|
||||
#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
|
||||
#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
|
||||
#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
|
||||
#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
|
||||
|
||||
#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
|
||||
#define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */
|
||||
|
||||
/* CHIPID Masks */
|
||||
#define CHIPID_VERSION 0xF0000000
|
||||
#define CHIPID_FAMILY 0x0FFFF000
|
||||
#define CHIPID_MANUFACTURE 0x00000FFE
|
||||
|
||||
/* SWRST Mask */
|
||||
#define SYSTEM_RESET 0x00000007 /* Initiates a system software reset */
|
||||
#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
|
||||
#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
|
||||
#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
|
||||
#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
|
||||
#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
|
||||
|
||||
/* SYSCR Masks */
|
||||
#define BMODE 0x0006 /* Boot Mode - Latched During HW Reset From Mode Pins */
|
||||
#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
|
||||
|
||||
/* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
|
||||
|
||||
@ -483,23 +528,6 @@
|
||||
#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */
|
||||
#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */
|
||||
|
||||
/* ********* WATCHDOG TIMER MASKS ********************8 */
|
||||
|
||||
/* Watchdog Timer WDOG_CTL Register */
|
||||
#define ICTL(x) ((x<<1) & 0x0006)
|
||||
#define ENABLE_RESET 0x00000000 /* Set Watchdog Timer to generate reset */
|
||||
#define ENABLE_NMI 0x00000002 /* Set Watchdog Timer to generate non-maskable interrupt */
|
||||
#define ENABLE_GPI 0x00000004 /* Set Watchdog Timer to generate general-purpose interrupt */
|
||||
#define DISABLE_EVT 0x00000006 /* Disable Watchdog Timer interrupts */
|
||||
|
||||
#define TMR_EN 0x0000
|
||||
#define TMR_DIS 0x0AD0
|
||||
#define TRO 0x8000
|
||||
|
||||
#define ICTL_P0 0x01
|
||||
#define ICTL_P1 0x02
|
||||
#define TRO_P 0x0F
|
||||
|
||||
/* ***************************** UART CONTROLLER MASKS ********************** */
|
||||
|
||||
/* UART_LCR Register */
|
||||
@ -583,6 +611,9 @@
|
||||
#define TSPEN 0x0001 /* TX enable */
|
||||
#define ITCLK 0x0002 /* Internal TX Clock Select */
|
||||
#define TDTYPE 0x000C /* TX Data Formatting Select */
|
||||
#define DTYPE_NORM 0x0000 /* Data Format Normal */
|
||||
#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
|
||||
#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
|
||||
#define TLSBIT 0x0010 /* TX Bit Order */
|
||||
#define ITFS 0x0200 /* Internal TX Frame Sync Select */
|
||||
#define TFSR 0x0400 /* TX Frame Sync Required Select */
|
||||
@ -592,7 +623,12 @@
|
||||
#define TCKFE 0x4000 /* TX Clock Falling Edge Select */
|
||||
|
||||
/* SPORTx_TCR2 Masks */
|
||||
#define SLEN 0x001F /*TX Word Length */
|
||||
#if defined(__ADSPBF531__) || defined(__ADSPBF532__) || \
|
||||
defined(__ADSPBF533__)
|
||||
# define SLEN 0x001F /*TX Word Length */
|
||||
#else
|
||||
# define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */
|
||||
#endif
|
||||
#define TXSE 0x0100 /*TX Secondary Enable */
|
||||
#define TSFSE 0x0200 /*TX Stereo Frame Sync Enable */
|
||||
#define TRFST 0x0400 /*TX Right-First Data Order */
|
||||
@ -601,8 +637,9 @@
|
||||
#define RSPEN 0x0001 /* RX enable */
|
||||
#define IRCLK 0x0002 /* Internal RX Clock Select */
|
||||
#define RDTYPE 0x000C /* RX Data Formatting Select */
|
||||
#define RULAW 0x0008 /* u-Law enable */
|
||||
#define RALAW 0x000C /* A-Law enable */
|
||||
#define DTYPE_NORM 0x0000 /* no companding */
|
||||
#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
|
||||
#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
|
||||
#define RLSBIT 0x0010 /* RX Bit Order */
|
||||
#define IRFS 0x0200 /* Internal RX Frame Sync Select */
|
||||
#define RFSR 0x0400 /* RX Frame Sync Required Select */
|
||||
@ -611,7 +648,7 @@
|
||||
#define RCKFE 0x4000 /* RX Clock Falling Edge Select */
|
||||
|
||||
/* SPORTx_RCR2 Masks */
|
||||
#define SLEN 0x001F /*RX Word Length */
|
||||
/* SLEN defined above */
|
||||
#define RXSE 0x0100 /*RX Secondary Enable */
|
||||
#define RSFSE 0x0200 /*RX Stereo Frame Sync Enable */
|
||||
#define RRFST 0x0400 /*Right-First Data Order */
|
||||
@ -628,14 +665,37 @@
|
||||
/*SPORTx_MCMC1 Masks */
|
||||
#define SP_WSIZE 0x0000F000 /*Multichannel Window Size Field */
|
||||
#define SP_WOFF 0x000003FF /*Multichannel Window Offset Field */
|
||||
/* SPORTx_MCMC1 Macros */
|
||||
#define SET_SP_WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */
|
||||
/* Only use SET_WSIZE Macro With Logic OR While Setting Lower Order Bits */
|
||||
#define SET_SP_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */
|
||||
|
||||
/*SPORTx_MCMC2 Masks */
|
||||
#define MCCRM 0x00000003 /*Multichannel Clock Recovery Mode */
|
||||
#define MCDTXPE 0x00000004 /*Multichannel DMA Transmit Packing */
|
||||
#define MCDRXPE 0x00000008 /*Multichannel DMA Receive Packing */
|
||||
#define MCMEN 0x00000010 /*Multichannel Frame Mode Enable */
|
||||
#define FSDR 0x00000080 /*Multichannel Frame Sync to Data Relationship */
|
||||
#define MFD 0x0000F000 /*Multichannel Frame Delay */
|
||||
#define MCCRM 0x00000003 /*Multichannel Clock Recovery Mode */
|
||||
#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
|
||||
#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
|
||||
#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
|
||||
#define MCDTXPE 0x00000004 /*Multichannel DMA Transmit Packing */
|
||||
#define MCDRXPE 0x00000008 /*Multichannel DMA Receive Packing */
|
||||
#define MCMEN 0x00000010 /*Multichannel Frame Mode Enable */
|
||||
#define FSDR 0x00000080 /*Multichannel Frame Sync to Data Relationship */
|
||||
#define MFD 0x0000F000 /*Multichannel Frame Delay */
|
||||
#define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */
|
||||
#define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */
|
||||
#define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */
|
||||
#define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */
|
||||
#define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */
|
||||
#define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */
|
||||
#define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */
|
||||
#define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */
|
||||
#define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */
|
||||
#define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */
|
||||
#define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */
|
||||
#define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */
|
||||
#define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */
|
||||
#define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */
|
||||
#define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */
|
||||
#define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */
|
||||
|
||||
/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */
|
||||
|
||||
@ -660,6 +720,8 @@
|
||||
#define DLEN_16 0x3800 /* Data Length = 16 Bits */
|
||||
#define DLEN(x) (((x-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */
|
||||
#define POL 0x0000C000 /* PPI Signal Polarities */
|
||||
#define POLC 0x4000 /* PPI Clock Polarity */
|
||||
#define POLS 0x8000 /* PPI Frame Sync Polarity */
|
||||
|
||||
/* PPI_STATUS Masks */
|
||||
#define FLD 0x00000400 /* Field Indicator */
|
||||
@ -729,6 +791,15 @@
|
||||
#define PCAPRD 0x00000800 /* DMA Read Operation Indicator */
|
||||
#define PMAP 0x00007000 /* DMA Peripheral Map Field */
|
||||
|
||||
#define PMAP_PPI 0x0000 /* PMAP PPI Port DMA */
|
||||
#define PMAP_SPORT0RX 0x1000 /* PMAP SPORT0 Receive DMA */
|
||||
#define PMAP_SPORT0TX 0x2000 /* PMAP SPORT0 Transmit DMA */
|
||||
#define PMAP_SPORT1RX 0x3000 /* PMAP SPORT1 Receive DMA */
|
||||
#define PMAP_SPORT1TX 0x4000 /* PMAP SPORT1 Transmit DMA */
|
||||
#define PMAP_SPI 0x5000 /* PMAP SPI DMA */
|
||||
#define PMAP_UARTRX 0x6000 /* PMAP UART Receive DMA */
|
||||
#define PMAP_UARTTX 0x7000 /* PMAP UART Transmit DMA */
|
||||
|
||||
/* ************* GENERAL PURPOSE TIMER MASKS ******************** */
|
||||
|
||||
/* PWM Timer bit definitions */
|
||||
@ -755,9 +826,9 @@
|
||||
#define TIMIL0 0x0001
|
||||
#define TIMIL1 0x0002
|
||||
#define TIMIL2 0x0004
|
||||
#define TOVL_ERR0 0x0010
|
||||
#define TOVL_ERR1 0x0020
|
||||
#define TOVL_ERR2 0x0040
|
||||
#define TOVF_ERR0 0x0010 /* Timer 0 Counter Overflow */
|
||||
#define TOVF_ERR1 0x0020 /* Timer 1 Counter Overflow */
|
||||
#define TOVF_ERR2 0x0040 /* Timer 2 Counter Overflow */
|
||||
#define TRUN0 0x1000
|
||||
#define TRUN1 0x2000
|
||||
#define TRUN2 0x4000
|
||||
@ -765,13 +836,21 @@
|
||||
#define TIMIL0_P 0x00
|
||||
#define TIMIL1_P 0x01
|
||||
#define TIMIL2_P 0x02
|
||||
#define TOVL_ERR0_P 0x04
|
||||
#define TOVL_ERR1_P 0x05
|
||||
#define TOVL_ERR2_P 0x06
|
||||
#define TOVF_ERR0_P 0x04
|
||||
#define TOVF_ERR1_P 0x05
|
||||
#define TOVF_ERR2_P 0x06
|
||||
#define TRUN0_P 0x0C
|
||||
#define TRUN1_P 0x0D
|
||||
#define TRUN2_P 0x0E
|
||||
|
||||
/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
|
||||
#define TOVL_ERR0 TOVF_ERR0
|
||||
#define TOVL_ERR1 TOVF_ERR1
|
||||
#define TOVL_ERR2 TOVF_ERR2
|
||||
#define TOVL_ERR0_P TOVF_ERR0_P
|
||||
#define TOVL_ERR1_P TOVF_ERR1_P
|
||||
#define TOVL_ERR2_P TOVF_ERR2_P
|
||||
|
||||
/* TIMERx_CONFIG Registers */
|
||||
#define PWM_OUT 0x0001
|
||||
#define WDTH_CAP 0x0002
|
||||
@ -841,6 +920,10 @@
|
||||
|
||||
/* SPI_CTL Masks */
|
||||
#define TIMOD 0x00000003 /* Transfer initiation mode and interrupt generation */
|
||||
#define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */
|
||||
#define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */
|
||||
#define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */
|
||||
#define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */
|
||||
#define SZ 0x00000004 /* Send Zero (=0) or last (=1) word when TDBR empty. */
|
||||
#define GM 0x00000008 /* When RDBR full, get more (=1) data or discard (=0) incoming Data */
|
||||
#define PSSE 0x00000010 /* Enable (=1) Slave-Select input for Master. */
|
||||
@ -894,10 +977,20 @@
|
||||
#define RXS 0x00000020 /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */
|
||||
#define TXCOL 0x00000040 /* When set (=1), corrupt data may have been transmitted */
|
||||
|
||||
/* SPIx_FLG Masks */
|
||||
#define FLG1E 0xFDFF /* Activates SPI_FLOUT1 */
|
||||
#define FLG2E 0xFBFF /* Activates SPI_FLOUT2 */
|
||||
#define FLG3E 0xF7FF /* Activates SPI_FLOUT3 */
|
||||
#define FLG4E 0xEFFF /* Activates SPI_FLOUT4 */
|
||||
#define FLG5E 0xDFFF /* Activates SPI_FLOUT5 */
|
||||
#define FLG6E 0xBFFF /* Activates SPI_FLOUT6 */
|
||||
#define FLG7E 0x7FFF /* Activates SPI_FLOUT7 */
|
||||
|
||||
/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */
|
||||
|
||||
/* AMGCTL Masks */
|
||||
#define AMCKEN 0x00000001 /* Enable CLKOUT */
|
||||
#define AMBEN_NONE 0x00000000 /* All Banks Disabled */
|
||||
#define AMBEN_B0 0x00000002 /* Enable Asynchronous Memory Bank 0 only */
|
||||
#define AMBEN_B0_B1 0x00000004 /* Enable Asynchronous Memory Banks 0 & 1 only */
|
||||
#define AMBEN_B0_B1_B2 0x00000006 /* Enable Asynchronous Memory Banks 0, 1, and 2 */
|
||||
@ -1097,6 +1190,9 @@
|
||||
#define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */
|
||||
#define PFE 0x00000010 /* Enable SDRAM prefetch */
|
||||
#define PFP 0x00000020 /* Prefetch has priority over AMC requests */
|
||||
#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
|
||||
#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
|
||||
#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
|
||||
#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
|
||||
#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
|
||||
#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
|
||||
@ -1158,18 +1254,5 @@
|
||||
#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */
|
||||
#define BGSTAT 0x00000020 /* Bus granted */
|
||||
|
||||
/*VR_CTL Masks*/
|
||||
#define WAKE 0x100
|
||||
#define VLEV_6 0x60
|
||||
#define VLEV_7 0x70
|
||||
#define VLEV_8 0x80
|
||||
#define VLEV_9 0x90
|
||||
#define VLEV_10 0xA0
|
||||
#define VLEV_11 0xB0
|
||||
#define VLEV_12 0xC0
|
||||
#define VLEV_13 0xD0
|
||||
#define VLEV_14 0xE0
|
||||
#define VLEV_15 0xF0
|
||||
#define FREQ_3 0x03
|
||||
|
||||
#endif /* _DEF_BF532_H */
|
||||
|
||||
@ -399,6 +399,12 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
|
||||
#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val)
|
||||
|
||||
/* DMA Traffic Control Registers */
|
||||
#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER)
|
||||
#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER,val)
|
||||
#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT)
|
||||
#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT,val)
|
||||
|
||||
/* Alternate deprecated register names (below) provided for backwards code compatibility */
|
||||
#define bfin_read_DMA_TCPER() bfin_read16(DMA_TCPER)
|
||||
#define bfin_write_DMA_TCPER(val) bfin_write16(DMA_TCPER,val)
|
||||
#define bfin_read_DMA_TCCNT() bfin_read16(DMA_TCCNT)
|
||||
@ -1075,8 +1081,6 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
|
||||
#define bfin_write_CAN_UCRC(val) bfin_write16(CAN_UCRC,val)
|
||||
#define bfin_read_CAN_UCCNF() bfin_read16(CAN_UCCNF)
|
||||
#define bfin_write_CAN_UCCNF(val) bfin_write16(CAN_UCCNF,val)
|
||||
#define bfin_read_CAN_SFCMVER2() bfin_read16(CAN_SFCMVER2)
|
||||
#define bfin_write_CAN_SFCMVER2(val) bfin_write16(CAN_SFCMVER2,val)
|
||||
|
||||
/* Mailbox Acceptance Masks */
|
||||
#define bfin_read_CAN_AM00L() bfin_read16(CAN_AM00L)
|
||||
|
||||
@ -216,8 +216,12 @@
|
||||
#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
|
||||
|
||||
/* DMA Traffic Control Registers */
|
||||
#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */
|
||||
#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */
|
||||
#define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
|
||||
#define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
|
||||
|
||||
/* Alternate deprecated register names (below) provided for backwards code compatibility */
|
||||
#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */
|
||||
#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */
|
||||
|
||||
/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
|
||||
#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
|
||||
@ -563,7 +567,7 @@
|
||||
#define CAN_GIF 0xFFC02A9C /* Global Interrupt Flag Register */
|
||||
#define CAN_CONTROL 0xFFC02AA0 /* Master Control Register */
|
||||
#define CAN_INTR 0xFFC02AA4 /* Interrupt Pending Register */
|
||||
#define CAN_SFCMVER 0xFFC02AA8 /* Version Code Register */
|
||||
|
||||
#define CAN_MBTD 0xFFC02AAC /* Mailbox Temporary Disable Feature */
|
||||
#define CAN_EWR 0xFFC02AB0 /* Programmable Warning Level */
|
||||
#define CAN_ESR 0xFFC02AB4 /* Error Status Register */
|
||||
@ -1026,10 +1030,11 @@
|
||||
#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
|
||||
|
||||
#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
|
||||
#define PHYWE 0x0200 /* Enable PHY Wakeup From Hibernate */
|
||||
#define CANWE 0x0400 /* Enable CAN Wakeup From Hibernate */
|
||||
#define PHYCLKOE 0x4000 /* PHY Clock Output Enable */
|
||||
#define CKELOW 0x8000 /* Enable Drive CKE Low During Reset */
|
||||
#define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */
|
||||
#define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */
|
||||
#define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */
|
||||
#define PHYCLKOE CLKBUFOE /* Alternative legacy name for the above */
|
||||
#define SCKELOW 0x8000 /* Enable Drive CKE Low During Reset */
|
||||
|
||||
/* PLL_STAT Masks */
|
||||
#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
|
||||
@ -1050,7 +1055,7 @@
|
||||
#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
|
||||
|
||||
/* SYSCR Masks */
|
||||
#define BMODE 0x0006 /* Boot Mode - Latched During HW Reset From Mode Pins */
|
||||
#define BMODE 0x0007 /* Boot Mode - Latched During HW Reset From Mode Pins */
|
||||
#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
|
||||
|
||||
/* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
|
||||
@ -1107,19 +1112,9 @@
|
||||
#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
|
||||
#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
|
||||
|
||||
/* *************** WATCHDOG TIMER MASKS *******************************************/
|
||||
/* WDOG_CTL Masks */
|
||||
#define WDOG_RESET 0x0000 /* Generate Reset Event */
|
||||
#define WDOG_NMI 0x0002 /* Generate Non-Maskable Interrupt (NMI) Event */
|
||||
#define WDOG_GPI 0x0004 /* Generate General Purpose (GP) Interrupt */
|
||||
#define WDOG_NONE 0x0006 /* Disable Watchdog Timer Interrupts */
|
||||
#define TMR_EN 0x0FF0 /* Watchdog Counter Enable */
|
||||
#define TMR_DIS 0x0AD0 /* Watchdog Counter Disable */
|
||||
#define TRO 0x8000 /* Watchdog Expired */
|
||||
|
||||
/* ************** UART CONTROLLER MASKS *************************/
|
||||
/* UARTx_LCR Masks */
|
||||
#define WLS(x) ((((x)&0x3)-5) & 0x03) /* Word Length Select */
|
||||
#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
|
||||
#define STB 0x04 /* Stop Bits */
|
||||
#define PEN 0x08 /* Parity Enable */
|
||||
#define EPS 0x10 /* Even Parity Select */
|
||||
@ -1128,8 +1123,8 @@
|
||||
#define DLAB 0x80 /* Divisor Latch Access */
|
||||
|
||||
/* UARTx_MCR Mask */
|
||||
#define LOOP 0x10 /* Loopback Mode Enable */
|
||||
|
||||
#define LOOP_ENA 0x10 /* Loopback Mode Enable */
|
||||
#define LOOP_ENA_P 0x04
|
||||
/* UARTx_LSR Masks */
|
||||
#define DR 0x01 /* Data Ready */
|
||||
#define OE 0x02 /* Overrun Error */
|
||||
@ -1229,10 +1224,10 @@
|
||||
#define TIMIL1 0x00000002 /* Timer 1 Interrupt */
|
||||
#define TIMIL2 0x00000004 /* Timer 2 Interrupt */
|
||||
#define TIMIL3 0x00000008 /* Timer 3 Interrupt */
|
||||
#define TOVL_ERR0 0x00000010 /* Timer 0 Counter Overflow */
|
||||
#define TOVL_ERR1 0x00000020 /* Timer 1 Counter Overflow */
|
||||
#define TOVL_ERR2 0x00000040 /* Timer 2 Counter Overflow */
|
||||
#define TOVL_ERR3 0x00000080 /* Timer 3 Counter Overflow */
|
||||
#define TOVF_ERR0 0x00000010 /* Timer 0 Counter Overflow */
|
||||
#define TOVF_ERR1 0x00000020 /* Timer 1 Counter Overflow */
|
||||
#define TOVF_ERR2 0x00000040 /* Timer 2 Counter Overflow */
|
||||
#define TOVF_ERR3 0x00000080 /* Timer 3 Counter Overflow */
|
||||
#define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */
|
||||
#define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */
|
||||
#define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */
|
||||
@ -1241,15 +1236,24 @@
|
||||
#define TIMIL5 0x00020000 /* Timer 5 Interrupt */
|
||||
#define TIMIL6 0x00040000 /* Timer 6 Interrupt */
|
||||
#define TIMIL7 0x00080000 /* Timer 7 Interrupt */
|
||||
#define TOVL_ERR4 0x00100000 /* Timer 4 Counter Overflow */
|
||||
#define TOVL_ERR5 0x00200000 /* Timer 5 Counter Overflow */
|
||||
#define TOVL_ERR6 0x00400000 /* Timer 6 Counter Overflow */
|
||||
#define TOVL_ERR7 0x00800000 /* Timer 7 Counter Overflow */
|
||||
#define TOVF_ERR4 0x00100000 /* Timer 4 Counter Overflow */
|
||||
#define TOVF_ERR5 0x00200000 /* Timer 5 Counter Overflow */
|
||||
#define TOVF_ERR6 0x00400000 /* Timer 6 Counter Overflow */
|
||||
#define TOVF_ERR7 0x00800000 /* Timer 7 Counter Overflow */
|
||||
#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */
|
||||
#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */
|
||||
#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */
|
||||
#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */
|
||||
|
||||
/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
|
||||
#define TOVL_ERR0 TOVF_ERR0
|
||||
#define TOVL_ERR1 TOVF_ERR1
|
||||
#define TOVL_ERR2 TOVF_ERR2
|
||||
#define TOVL_ERR3 TOVF_ERR3
|
||||
#define TOVL_ERR4 TOVF_ERR4
|
||||
#define TOVL_ERR5 TOVF_ERR5
|
||||
#define TOVL_ERR6 TOVF_ERR6
|
||||
#define TOVL_ERR7 TOVF_ERR7
|
||||
/* TIMERx_CONFIG Masks */
|
||||
#define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */
|
||||
#define WDTH_CAP 0x0002 /* Width Capture Input Mode */
|
||||
@ -1647,6 +1651,8 @@
|
||||
#define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */
|
||||
#define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */
|
||||
#define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */
|
||||
#define EBSZ_256 0x0008 /* SDRAM External Bank Size = 256MB */
|
||||
#define EBSZ_512 0x000A /* SDRAM External Bank Size = 512MB */
|
||||
#define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */
|
||||
#define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */
|
||||
#define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */
|
||||
@ -1859,8 +1865,10 @@
|
||||
#define TXECNT 0xFF00 /* Transmit Error Counter */
|
||||
|
||||
/* CAN_INTR Masks */
|
||||
#define MBRIF 0x0001 /* Mailbox Receive Interrupt */
|
||||
#define MBTIF 0x0002 /* Mailbox Transmit Interrupt */
|
||||
#define MBRIRQ 0x0001 /* Mailbox Receive Interrupt */
|
||||
#define MBRIF MBRIRQ /* legacy */
|
||||
#define MBTIRQ 0x0002 /* Mailbox Transmit Interrupt */
|
||||
#define MBTIF MBTIRQ /* legacy */
|
||||
#define GIRQ 0x0004 /* Global Interrupt */
|
||||
#define SMACK 0x0008 /* Sleep Mode Acknowledge */
|
||||
#define CANTX 0x0040 /* CAN TX Bus Value */
|
||||
@ -2445,8 +2453,8 @@
|
||||
#define PJCE_SPI 0x0004 /* Enable SPI_SSEL7 */
|
||||
|
||||
#define PFDE 0x0008 /* Port F DMA Request Enable */
|
||||
#define PGDE_UART 0x0000 /* Enable UART0 RX/TX */
|
||||
#define PGDE_DMA 0x0008 /* Enable DMAR1:0 */
|
||||
#define PFDE_UART 0x0000 /* Enable UART0 RX/TX */
|
||||
#define PFDE_DMA 0x0008 /* Enable DMAR1:0 */
|
||||
|
||||
#define PFTE 0x0010 /* Port F Timer Enable */
|
||||
#define PFTE_UART 0x0000 /* Enable UART1 RX/TX */
|
||||
@ -2498,4 +2506,20 @@
|
||||
#define OI 0x4000 /* Overflow Interrupt Generated */
|
||||
#define BDI 0x8000 /* Block Done Interrupt Generated */
|
||||
|
||||
/* entry addresses of the user-callable Boot ROM functions */
|
||||
|
||||
#define _BOOTROM_RESET 0xEF000000
|
||||
#define _BOOTROM_FINAL_INIT 0xEF000002
|
||||
#define _BOOTROM_DO_MEMORY_DMA 0xEF000006
|
||||
#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008
|
||||
#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A
|
||||
#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C
|
||||
#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
|
||||
#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
|
||||
#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
|
||||
|
||||
/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
|
||||
#define PGDE_UART PFDE_UART
|
||||
#define PGDE_DMA PFDE_DMA
|
||||
#define CKELOW SCKELOW
|
||||
#endif /* _DEF_BF534_H */
|
||||
|
||||
@ -32,12 +32,12 @@
|
||||
#ifndef _DEF_BF537_H
|
||||
#define _DEF_BF537_H
|
||||
|
||||
/*include all Core registers and bit definitions*/
|
||||
#include "defBF537.h"
|
||||
|
||||
/*include core specific register pointer definitions*/
|
||||
/* Include all Core registers and bit definitions*/
|
||||
#include <asm/mach-common/cdef_LPBlackfin.h>
|
||||
|
||||
/* Include all MMR and bit defines common to BF534 */
|
||||
#include "defBF534.h"
|
||||
|
||||
/************************************************************************************
|
||||
** Define EMAC Section Unique to BF536/BF537
|
||||
*************************************************************************************/
|
||||
|
||||
590
include/asm-blackfin/mach-bf548/cdefBF542.h
Normal file
590
include/asm-blackfin/mach-bf548/cdefBF542.h
Normal file
@ -0,0 +1,590 @@
|
||||
/*
|
||||
* File: include/asm-blackfin/mach-bf548/cdefBF542.h
|
||||
* Based on:
|
||||
* Author:
|
||||
*
|
||||
* Created:
|
||||
* Description:
|
||||
*
|
||||
* Rev:
|
||||
*
|
||||
* Modified:
|
||||
*
|
||||
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING.
|
||||
* If not, write to the Free Software Foundation,
|
||||
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
*/
|
||||
|
||||
#ifndef _CDEF_BF542_H
|
||||
#define _CDEF_BF542_H
|
||||
|
||||
/* include all Core registers and bit definitions */
|
||||
#include "defBF542.h"
|
||||
|
||||
/* include core sbfin_read_()ecific register pointer definitions */
|
||||
#include <asm/mach-common/cdef_LPBlackfin.h>
|
||||
|
||||
/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF542 */
|
||||
|
||||
/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
|
||||
#include "cdefBF54x_base.h"
|
||||
|
||||
/* The following are the #defines needed by ADSP-BF542 that are not in the common header */
|
||||
|
||||
/* ATAPI Registers */
|
||||
|
||||
#define bfin_read_ATAPI_CONTROL() bfin_read16(ATAPI_CONTROL)
|
||||
#define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val)
|
||||
#define bfin_read_ATAPI_STATUS() bfin_read16(ATAPI_STATUS)
|
||||
#define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val)
|
||||
#define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR)
|
||||
#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
|
||||
#define bfin_read_ATAPI_DEV_TXBUF() bfin_read16(ATAPI_DEV_TXBUF)
|
||||
#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val)
|
||||
#define bfin_read_ATAPI_DEV_RXBUF() bfin_read16(ATAPI_DEV_RXBUF)
|
||||
#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val)
|
||||
#define bfin_read_ATAPI_INT_MASK() bfin_read16(ATAPI_INT_MASK)
|
||||
#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val)
|
||||
#define bfin_read_ATAPI_INT_STATUS() bfin_read16(ATAPI_INT_STATUS)
|
||||
#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val)
|
||||
#define bfin_read_ATAPI_XFER_LEN() bfin_read16(ATAPI_XFER_LEN)
|
||||
#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val)
|
||||
#define bfin_read_ATAPI_LINE_STATUS() bfin_read16(ATAPI_LINE_STATUS)
|
||||
#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val)
|
||||
#define bfin_read_ATAPI_SM_STATE() bfin_read16(ATAPI_SM_STATE)
|
||||
#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val)
|
||||
#define bfin_read_ATAPI_TERMINATE() bfin_read16(ATAPI_TERMINATE)
|
||||
#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val)
|
||||
#define bfin_read_ATAPI_PIO_TFRCNT() bfin_read16(ATAPI_PIO_TFRCNT)
|
||||
#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val)
|
||||
#define bfin_read_ATAPI_DMA_TFRCNT() bfin_read16(ATAPI_DMA_TFRCNT)
|
||||
#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val)
|
||||
#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT)
|
||||
#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val)
|
||||
#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT)
|
||||
#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
|
||||
#define bfin_read_ATAPI_REG_TIM_0() bfin_read16(ATAPI_REG_TIM_0)
|
||||
#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val)
|
||||
#define bfin_read_ATAPI_PIO_TIM_0() bfin_read16(ATAPI_PIO_TIM_0)
|
||||
#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val)
|
||||
#define bfin_read_ATAPI_PIO_TIM_1() bfin_read16(ATAPI_PIO_TIM_1)
|
||||
#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val)
|
||||
#define bfin_read_ATAPI_MULTI_TIM_0() bfin_read16(ATAPI_MULTI_TIM_0)
|
||||
#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val)
|
||||
#define bfin_read_ATAPI_MULTI_TIM_1() bfin_read16(ATAPI_MULTI_TIM_1)
|
||||
#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val)
|
||||
#define bfin_read_ATAPI_MULTI_TIM_2() bfin_read16(ATAPI_MULTI_TIM_2)
|
||||
#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val)
|
||||
#define bfin_read_ATAPI_ULTRA_TIM_0() bfin_read16(ATAPI_ULTRA_TIM_0)
|
||||
#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val)
|
||||
#define bfin_read_ATAPI_ULTRA_TIM_1() bfin_read16(ATAPI_ULTRA_TIM_1)
|
||||
#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val)
|
||||
#define bfin_read_ATAPI_ULTRA_TIM_2() bfin_read16(ATAPI_ULTRA_TIM_2)
|
||||
#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val)
|
||||
#define bfin_read_ATAPI_ULTRA_TIM_3() bfin_read16(ATAPI_ULTRA_TIM_3)
|
||||
#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val)
|
||||
|
||||
/* SDH Registers */
|
||||
|
||||
#define bfin_read_SDH_PWR_CTL() bfin_read16(SDH_PWR_CTL)
|
||||
#define bfin_write_SDH_PWR_CTL(val) bfin_write16(SDH_PWR_CTL, val)
|
||||
#define bfin_read_SDH_CLK_CTL() bfin_read16(SDH_CLK_CTL)
|
||||
#define bfin_write_SDH_CLK_CTL(val) bfin_write16(SDH_CLK_CTL, val)
|
||||
#define bfin_read_SDH_ARGUMENT() bfin_read32(SDH_ARGUMENT)
|
||||
#define bfin_write_SDH_ARGUMENT(val) bfin_write32(SDH_ARGUMENT, val)
|
||||
#define bfin_read_SDH_COMMAND() bfin_read16(SDH_COMMAND)
|
||||
#define bfin_write_SDH_COMMAND(val) bfin_write16(SDH_COMMAND, val)
|
||||
#define bfin_read_SDH_RESP_CMD() bfin_read16(SDH_RESP_CMD)
|
||||
#define bfin_write_SDH_RESP_CMD(val) bfin_write16(SDH_RESP_CMD, val)
|
||||
#define bfin_read_SDH_RESPONSE0() bfin_read32(SDH_RESPONSE0)
|
||||
#define bfin_write_SDH_RESPONSE0(val) bfin_write32(SDH_RESPONSE0, val)
|
||||
#define bfin_read_SDH_RESPONSE1() bfin_read32(SDH_RESPONSE1)
|
||||
#define bfin_write_SDH_RESPONSE1(val) bfin_write32(SDH_RESPONSE1, val)
|
||||
#define bfin_read_SDH_RESPONSE2() bfin_read32(SDH_RESPONSE2)
|
||||
#define bfin_write_SDH_RESPONSE2(val) bfin_write32(SDH_RESPONSE2, val)
|
||||
#define bfin_read_SDH_RESPONSE3() bfin_read32(SDH_RESPONSE3)
|
||||
#define bfin_write_SDH_RESPONSE3(val) bfin_write32(SDH_RESPONSE3, val)
|
||||
#define bfin_read_SDH_DATA_TIMER() bfin_read32(SDH_DATA_TIMER)
|
||||
#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val)
|
||||
#define bfin_read_SDH_DATA_LGTH() bfin_read16(SDH_DATA_LGTH)
|
||||
#define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val)
|
||||
#define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL)
|
||||
#define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val)
|
||||
#define bfin_read_SDH_DATA_CNT() fin_read16(SDH_DATA_CNT)
|
||||
#define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val)
|
||||
#define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS)
|
||||
#define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val)
|
||||
#define bfin_read_SDH_STATUS_CLR() fin_read16(SDH_STATUS_CLR)
|
||||
#define bfin_write_SDH_STATUS_CLR(val) fin_write16(SDH_STATUS_CLR, val)
|
||||
#define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0)
|
||||
#define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val)
|
||||
#define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1)
|
||||
#define bfin_write_SDH_MASK1(val) bfin_write32(SDH_MASK1, val)
|
||||
#define bfin_read_SDH_FIFO_CNT() bfin_read16(SDH_FIFO_CNT)
|
||||
#define bfin_write_SDH_FIFO_CNT(val) bfin_write16(SDH_FIFO_CNT, val)
|
||||
#define bfin_read_SDH_FIFO() bfin_read32(SDH_FIFO)
|
||||
#define bfin_write_SDH_FIFO(val) bfin_write32(SDH_FIFO, val)
|
||||
#define bfin_read_SDH_E_STATUS() bfin_read16(SDH_E_STATUS)
|
||||
#define bfin_write_SDH_E_STATUS(val) bfin_write16(SDH_E_STATUS, val)
|
||||
#define bfin_read_SDH_E_MASK() bfin_read16(SDH_E_MASK)
|
||||
#define bfin_write_SDH_E_MASK(val) bfin_write16(SDH_E_MASK, val)
|
||||
#define bfin_read_SDH_CFG() bfin_read16(SDH_CFG)
|
||||
#define bfin_write_SDH_CFG(val) bfin_write16(SDH_CFG, val)
|
||||
#define bfin_read_SDH_RD_WAIT_EN() bfin_read16(SDH_RD_WAIT_EN)
|
||||
#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val)
|
||||
#define bfin_read_SDH_PID0() bfin_read16(SDH_PID0)
|
||||
#define bfin_write_SDH_PID0(val) bfin_write16(SDH_PID0, val)
|
||||
#define bfin_read_SDH_PID1() bfin_read16(SDH_PID1)
|
||||
#define bfin_write_SDH_PID1(val) bfin_write16(SDH_PID1, val)
|
||||
#define bfin_read_SDH_PID2() bfin_read16(SDH_PID2)
|
||||
#define bfin_write_SDH_PID2(val) bfin_write16(SDH_PID2, val)
|
||||
#define bfin_read_SDH_PID3() bfin_read16(SDH_PID3)
|
||||
#define bfin_write_SDH_PID3(val) bfin_write16(SDH_PID3, val)
|
||||
#define bfin_read_SDH_PID4() bfin_read16(SDH_PID4)
|
||||
#define bfin_write_SDH_PID4(val) bfin_write16(SDH_PID4, val)
|
||||
#define bfin_read_SDH_PID5() bfin_read16(SDH_PID5)
|
||||
#define bfin_write_SDH_PID5(val) bfin_write16(SDH_PID5, val)
|
||||
#define bfin_read_SDH_PID6() bfin_read16(SDH_PID6)
|
||||
#define bfin_write_SDH_PID6(val) bfin_write16(SDH_PID6, val)
|
||||
#define bfin_read_SDH_PID7() bfin_read16(SDH_PID7)
|
||||
#define bfin_write_SDH_PID7(val) bfin_write16(SDH_PID7, val)
|
||||
|
||||
/* USB Control Registers */
|
||||
|
||||
#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
|
||||
#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
|
||||
#define bfin_read_USB_POWER() bfin_read16(USB_POWER)
|
||||
#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
|
||||
#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX)
|
||||
#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
|
||||
#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX)
|
||||
#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
|
||||
#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE)
|
||||
#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
|
||||
#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE)
|
||||
#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
|
||||
#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB)
|
||||
#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
|
||||
#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE)
|
||||
#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
|
||||
#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME)
|
||||
#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
|
||||
#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
|
||||
#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
|
||||
#define bfin_read_USB_TESTMODE() fin_read16(USB_TESTMODE)
|
||||
#define bfin_write_USB_TESTMODE(val) fin_write16(USB_TESTMODE, val)
|
||||
#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
|
||||
#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
|
||||
#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
|
||||
#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
|
||||
|
||||
/* USB Packet Control Registers */
|
||||
|
||||
#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET)
|
||||
#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
|
||||
#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0)
|
||||
#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
|
||||
#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR)
|
||||
#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
|
||||
#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET)
|
||||
#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
|
||||
#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR)
|
||||
#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
|
||||
#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0)
|
||||
#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
|
||||
#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT)
|
||||
#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
|
||||
#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE)
|
||||
#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
|
||||
#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0)
|
||||
#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
|
||||
#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL)
|
||||
#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
|
||||
#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE)
|
||||
#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
|
||||
#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL)
|
||||
#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
|
||||
#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT)
|
||||
#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
|
||||
|
||||
/* USB Endbfin_read_()oint FIFO Registers */
|
||||
|
||||
#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO)
|
||||
#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
|
||||
#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO)
|
||||
#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
|
||||
#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO)
|
||||
#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
|
||||
#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO)
|
||||
#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
|
||||
#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO)
|
||||
#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
|
||||
#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO)
|
||||
#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
|
||||
#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO)
|
||||
#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
|
||||
#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO)
|
||||
#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
|
||||
|
||||
/* USB OTG Control Registers */
|
||||
|
||||
#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
|
||||
#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
|
||||
#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
|
||||
#define bfin_write_USB_OTG_VBUS_IRQ(val) fin_write16(USB_OTG_VBUS_IRQ, val)
|
||||
#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
|
||||
#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
|
||||
|
||||
/* USB Phy Control Registers */
|
||||
|
||||
#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO)
|
||||
#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
|
||||
#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN)
|
||||
#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
|
||||
#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1)
|
||||
#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
|
||||
#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1)
|
||||
#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
|
||||
#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1)
|
||||
#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
|
||||
|
||||
/* (APHY_CNTRL is for ADI usage only) */
|
||||
|
||||
#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL)
|
||||
#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
|
||||
|
||||
/* (APHY_CALIB is for ADI usage only) */
|
||||
|
||||
#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB)
|
||||
#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
|
||||
#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2)
|
||||
#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
|
||||
|
||||
/* (PHY_TEST is for ADI usage only) */
|
||||
|
||||
#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST)
|
||||
#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val)
|
||||
#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL)
|
||||
#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
|
||||
#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV)
|
||||
#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
|
||||
|
||||
/* USB Endbfin_read_()oint 0 Control Registers */
|
||||
|
||||
#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP)
|
||||
#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR)
|
||||
#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
|
||||
#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP)
|
||||
#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR)
|
||||
#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
|
||||
#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
|
||||
#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE)
|
||||
#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE)
|
||||
#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
|
||||
|
||||
/* USB Endbfin_read_()oint 1 Control Registers */
|
||||
|
||||
#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
|
||||
#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP)
|
||||
#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR)
|
||||
#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
|
||||
#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP)
|
||||
#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR)
|
||||
#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
|
||||
#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
|
||||
#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE)
|
||||
#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE)
|
||||
#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
|
||||
|
||||
/* USB Endbfin_read_()oint 2 Control Registers */
|
||||
|
||||
#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
|
||||
#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP)
|
||||
#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR)
|
||||
#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
|
||||
#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP)
|
||||
#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR)
|
||||
#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
|
||||
#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
|
||||
#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE)
|
||||
#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE)
|
||||
#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
|
||||
|
||||
/* USB Endbfin_read_()oint 3 Control Registers */
|
||||
|
||||
#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
|
||||
#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP)
|
||||
#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR)
|
||||
#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
|
||||
#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP)
|
||||
#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR)
|
||||
#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
|
||||
#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
|
||||
#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE)
|
||||
#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE)
|
||||
#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
|
||||
|
||||
/* USB Endbfin_read_()oint 4 Control Registers */
|
||||
|
||||
#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
|
||||
#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP)
|
||||
#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR)
|
||||
#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
|
||||
#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP)
|
||||
#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR)
|
||||
#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
|
||||
#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
|
||||
#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE)
|
||||
#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE)
|
||||
#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
|
||||
|
||||
/* USB Endbfin_read_()oint 5 Control Registers */
|
||||
|
||||
#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
|
||||
#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP)
|
||||
#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR)
|
||||
#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
|
||||
#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP)
|
||||
#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR)
|
||||
#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
|
||||
#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
|
||||
#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE)
|
||||
#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE)
|
||||
#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
|
||||
|
||||
/* USB Endbfin_read_()oint 6 Control Registers */
|
||||
|
||||
#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
|
||||
#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP)
|
||||
#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR)
|
||||
#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
|
||||
#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP)
|
||||
#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR)
|
||||
#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
|
||||
#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
|
||||
#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE)
|
||||
#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE)
|
||||
#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
|
||||
|
||||
/* USB Endbfin_read_()oint 7 Control Registers */
|
||||
|
||||
#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
|
||||
#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP)
|
||||
#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR)
|
||||
#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
|
||||
#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP)
|
||||
#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR)
|
||||
#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
|
||||
#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
|
||||
#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE)
|
||||
#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE)
|
||||
#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
|
||||
#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
|
||||
#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT)
|
||||
#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
|
||||
|
||||
/* USB Channel 0 Config Registers */
|
||||
|
||||
#define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL)
|
||||
#define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val)
|
||||
#define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW)
|
||||
#define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val)
|
||||
#define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH)
|
||||
#define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val)
|
||||
#define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW)
|
||||
#define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val)
|
||||
#define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH)
|
||||
#define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val)
|
||||
|
||||
/* USB Channel 1 Config Registers */
|
||||
|
||||
#define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL)
|
||||
#define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val)
|
||||
#define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW)
|
||||
#define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val)
|
||||
#define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH)
|
||||
#define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val)
|
||||
#define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW)
|
||||
#define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val)
|
||||
#define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH)
|
||||
#define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val)
|
||||
|
||||
/* USB Channel 2 Config Registers */
|
||||
|
||||
#define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL)
|
||||
#define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val)
|
||||
#define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW)
|
||||
#define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val)
|
||||
#define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH)
|
||||
#define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val)
|
||||
#define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW)
|
||||
#define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val)
|
||||
#define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH)
|
||||
#define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val)
|
||||
|
||||
/* USB Channel 3 Config Registers */
|
||||
|
||||
#define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL)
|
||||
#define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val)
|
||||
#define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW)
|
||||
#define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val)
|
||||
#define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH)
|
||||
#define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val)
|
||||
#define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW)
|
||||
#define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val)
|
||||
#define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH)
|
||||
#define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val)
|
||||
|
||||
/* USB Channel 4 Config Registers */
|
||||
|
||||
#define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL)
|
||||
#define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val)
|
||||
#define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW)
|
||||
#define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val)
|
||||
#define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH)
|
||||
#define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val)
|
||||
#define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW)
|
||||
#define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val)
|
||||
#define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH)
|
||||
#define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val)
|
||||
|
||||
/* USB Channel 5 Config Registers */
|
||||
|
||||
#define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL)
|
||||
#define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val)
|
||||
#define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW)
|
||||
#define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val)
|
||||
#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH)
|
||||
#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val)
|
||||
#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW)
|
||||
#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val)
|
||||
#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH)
|
||||
#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val)
|
||||
|
||||
/* USB Channel 6 Config Registers */
|
||||
|
||||
#define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL)
|
||||
#define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val)
|
||||
#define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW)
|
||||
#define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val)
|
||||
#define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH)
|
||||
#define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val)
|
||||
#define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW)
|
||||
#define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val)
|
||||
#define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH)
|
||||
#define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val)
|
||||
|
||||
/* USB Channel 7 Config Registers */
|
||||
|
||||
#define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL)
|
||||
#define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val)
|
||||
#define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW)
|
||||
#define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val)
|
||||
#define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH)
|
||||
#define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val)
|
||||
#define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW)
|
||||
#define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val)
|
||||
#define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH)
|
||||
#define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val)
|
||||
|
||||
/* Keybfin_read_()ad Registers */
|
||||
|
||||
#define bfin_read_KPAD_CTL() bfin_read16(KPAD_CTL)
|
||||
#define bfin_write_KPAD_CTL(val) bfin_write16(KPAD_CTL, val)
|
||||
#define bfin_read_KPAD_PRESCALE() bfin_read16(KPAD_PRESCALE)
|
||||
#define bfin_write_KPAD_PRESCALE(val) bfin_write16(KPAD_PRESCALE, val)
|
||||
#define bfin_read_KPAD_MSEL() bfin_read16(KPAD_MSEL)
|
||||
#define bfin_write_KPAD_MSEL(val) bfin_write16(KPAD_MSEL, val)
|
||||
#define bfin_read_KPAD_ROWCOL() bfin_read16(KPAD_ROWCOL)
|
||||
#define bfin_write_KPAD_ROWCOL(val) bfin_write16(KPAD_ROWCOL, val)
|
||||
#define bfin_read_KPAD_STAT() bfin_read16(KPAD_STAT)
|
||||
#define bfin_write_KPAD_STAT(val) bfin_write16(KPAD_STAT, val)
|
||||
#define bfin_read_KPAD_SOFTEVAL() bfin_read16(KPAD_SOFTEVAL)
|
||||
#define bfin_write_KPAD_SOFTEVAL(val) bfin_write16(KPAD_SOFTEVAL, val)
|
||||
|
||||
#endif /* _CDEF_BF542_H */
|
||||
978
include/asm-blackfin/mach-bf548/cdefBF544.h
Normal file
978
include/asm-blackfin/mach-bf548/cdefBF544.h
Normal file
@ -0,0 +1,978 @@
|
||||
/*
|
||||
* File: include/asm-blackfin/mach-bf548/cdefBF544.h
|
||||
* Based on:
|
||||
* Author:
|
||||
*
|
||||
* Created:
|
||||
* Description:
|
||||
*
|
||||
* Rev:
|
||||
*
|
||||
* Modified:
|
||||
*
|
||||
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING.
|
||||
* If not, write to the Free Software Foundation,
|
||||
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
*/
|
||||
|
||||
#ifndef _CDEF_BF544_H
|
||||
#define _CDEF_BF544_H
|
||||
|
||||
/* include all Core registers and bit definitions */
|
||||
#include "defBF544.h"
|
||||
|
||||
/* include core sbfin_read_()ecific register pointer definitions */
|
||||
#include <asm/mach-common/cdef_LPBlackfin.h>
|
||||
|
||||
/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF544 */
|
||||
|
||||
/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
|
||||
#include "cdefBF54x_base.h"
|
||||
|
||||
/* The following are the #defines needed by ADSP-BF544 that are not in the common header */
|
||||
|
||||
/* Timer Registers */
|
||||
|
||||
#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG)
|
||||
#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val)
|
||||
#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER)
|
||||
#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
|
||||
#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD)
|
||||
#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val)
|
||||
#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH)
|
||||
#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val)
|
||||
#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG)
|
||||
#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val)
|
||||
#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER)
|
||||
#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
|
||||
#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD)
|
||||
#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val)
|
||||
#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH)
|
||||
#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val)
|
||||
#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG)
|
||||
#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
|
||||
#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER)
|
||||
#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
|
||||
#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD)
|
||||
#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
|
||||
#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH)
|
||||
#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val)
|
||||
|
||||
/* Timer Groubfin_read_() of 3 */
|
||||
|
||||
#define bfin_read_TIMER_ENABLE1() bfin_read16(TIMER_ENABLE1)
|
||||
#define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val)
|
||||
#define bfin_read_TIMER_DISABLE1() bfin_read16(TIMER_DISABLE1)
|
||||
#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
|
||||
#define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1)
|
||||
#define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val)
|
||||
|
||||
/* EPPI0 Registers */
|
||||
|
||||
#define bfin_read_EPPI0_STATUS() bfin_read16(EPPI0_STATUS)
|
||||
#define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val)
|
||||
#define bfin_read_EPPI0_HCOUNT() bfin_read16(EPPI0_HCOUNT)
|
||||
#define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val)
|
||||
#define bfin_read_EPPI0_HDELAY() bfin_read16(EPPI0_HDELAY)
|
||||
#define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val)
|
||||
#define bfin_read_EPPI0_VCOUNT() bfin_read16(EPPI0_VCOUNT)
|
||||
#define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val)
|
||||
#define bfin_read_EPPI0_VDELAY() bfin_read16(EPPI0_VDELAY)
|
||||
#define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val)
|
||||
#define bfin_read_EPPI0_FRAME() bfin_read16(EPPI0_FRAME)
|
||||
#define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val)
|
||||
#define bfin_read_EPPI0_LINE() bfin_read16(EPPI0_LINE)
|
||||
#define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val)
|
||||
#define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV)
|
||||
#define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val)
|
||||
#define bfin_read_EPPI0_CONTROL() bfin_read32(EPPI0_CONTROL)
|
||||
#define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val)
|
||||
#define bfin_read_EPPI0_FS1W_HBL() bfin_read32(EPPI0_FS1W_HBL)
|
||||
#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val)
|
||||
#define bfin_read_EPPI0_FS1P_AVPL() bfin_read32(EPPI0_FS1P_AVPL)
|
||||
#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
|
||||
#define bfin_read_EPPI0_FS2W_LVB() bfin_read32(EPPI0_FS2W_LVB)
|
||||
#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val)
|
||||
#define bfin_read_EPPI0_FS2P_LAVF() bfin_read32(EPPI0_FS2P_LAVF)
|
||||
#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
|
||||
#define bfin_read_EPPI0_CLIP() bfin_read32(EPPI0_CLIP)
|
||||
#define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val)
|
||||
|
||||
/* Two Wire Interface Registers (TWI1) */
|
||||
|
||||
#define bfin_read_TWI1_CLKDIV() bfin_read16(TWI1_CLKDIV)
|
||||
#define bfin_write_TWI1_CLKDIV(val) bfin_write16(TWI1_CLKDIV, val)
|
||||
#define bfin_read_TWI1_CONTROL() bfin_read16(TWI1_CONTROL)
|
||||
#define bfin_write_TWI1_CONTROL(val) bfin_write16(TWI1_CONTROL, val)
|
||||
#define bfin_read_TWI1_SLAVE_CTRL() bfin_read16(TWI1_SLAVE_CTRL)
|
||||
#define bfin_write_TWI1_SLAVE_CTRL(val) bfin_write16(TWI1_SLAVE_CTRL, val)
|
||||
#define bfin_read_TWI1_SLAVE_STAT() bfin_read16(TWI1_SLAVE_STAT)
|
||||
#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val)
|
||||
#define bfin_read_TWI1_SLAVE_ADDR() bfin_read16(TWI1_SLAVE_ADDR)
|
||||
#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val)
|
||||
#define bfin_read_TWI1_MASTER_CTRL() bfin_read16(TWI1_MASTER_CTRL)
|
||||
#define bfin_write_TWI1_MASTER_CTRL(val) bfin_write16(TWI1_MASTER_CTRL, val)
|
||||
#define bfin_read_TWI1_MASTER_STAT() bfin_read16(TWI1_MASTER_STAT)
|
||||
#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val)
|
||||
#define bfin_read_TWI1_MASTER_ADDR() bfin_read16(TWI1_MASTER_ADDR)
|
||||
#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val)
|
||||
#define bfin_read_TWI1_INT_STAT() bfin_read16(TWI1_INT_STAT)
|
||||
#define bfin_write_TWI1_INT_STAT(val) bfin_write16(TWI1_INT_STAT, val)
|
||||
#define bfin_read_TWI1_INT_MASK() bfin_read16(TWI1_INT_MASK)
|
||||
#define bfin_write_TWI1_INT_MASK(val) bfin_write16(TWI1_INT_MASK, val)
|
||||
#define bfin_read_TWI1_FIFO_CTRL() bfin_read16(TWI1_FIFO_CTRL)
|
||||
#define bfin_write_TWI1_FIFO_CTRL(val) bfin_write16(TWI1_FIFO_CTRL, val)
|
||||
#define bfin_read_TWI1_FIFO_STAT() bfin_read16(TWI1_FIFO_STAT)
|
||||
#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val)
|
||||
#define bfin_read_TWI1_XMT_DATA8() bfin_read16(TWI1_XMT_DATA8)
|
||||
#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val)
|
||||
#define bfin_read_TWI1_XMT_DATA16() bfin_read16(TWI1_XMT_DATA16)
|
||||
#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val)
|
||||
#define bfin_read_TWI1_RCV_DATA8() bfin_read16(TWI1_RCV_DATA8)
|
||||
#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val)
|
||||
#define bfin_read_TWI1_RCV_DATA16() bfin_read16(TWI1_RCV_DATA16)
|
||||
#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val)
|
||||
|
||||
/* CAN Controller 1 Config 1 Registers */
|
||||
|
||||
#define bfin_read_CAN1_MC1() bfin_read16(CAN1_MC1)
|
||||
#define bfin_write_CAN1_MC1(val) bfin_write16(CAN1_MC1, val)
|
||||
#define bfin_read_CAN1_MD1() bfin_read16(CAN1_MD1)
|
||||
#define bfin_write_CAN1_MD1(val) bfin_write16(CAN1_MD1, val)
|
||||
#define bfin_read_CAN1_TRS1() bfin_read16(CAN1_TRS1)
|
||||
#define bfin_write_CAN1_TRS1(val) bfin_write16(CAN1_TRS1, val)
|
||||
#define bfin_read_CAN1_TRR1() bfin_read16(CAN1_TRR1)
|
||||
#define bfin_write_CAN1_TRR1(val) bfin_write16(CAN1_TRR1, val)
|
||||
#define bfin_read_CAN1_TA1() bfin_read16(CAN1_TA1)
|
||||
#define bfin_write_CAN1_TA1(val) bfin_write16(CAN1_TA1, val)
|
||||
#define bfin_read_CAN1_AA1() bfin_read16(CAN1_AA1)
|
||||
#define bfin_write_CAN1_AA1(val) bfin_write16(CAN1_AA1, val)
|
||||
#define bfin_read_CAN1_RMP1() bfin_read16(CAN1_RMP1)
|
||||
#define bfin_write_CAN1_RMP1(val) bfin_write16(CAN1_RMP1, val)
|
||||
#define bfin_read_CAN1_RML1() bfin_read16(CAN1_RML1)
|
||||
#define bfin_write_CAN1_RML1(val) bfin_write16(CAN1_RML1, val)
|
||||
#define bfin_read_CAN1_MBTIF1() bfin_read16(CAN1_MBTIF1)
|
||||
#define bfin_write_CAN1_MBTIF1(val) bfin_write16(CAN1_MBTIF1, val)
|
||||
#define bfin_read_CAN1_MBRIF1() bfin_read16(CAN1_MBRIF1)
|
||||
#define bfin_write_CAN1_MBRIF1(val) bfin_write16(CAN1_MBRIF1, val)
|
||||
#define bfin_read_CAN1_MBIM1() bfin_read16(CAN1_MBIM1)
|
||||
#define bfin_write_CAN1_MBIM1(val) bfin_write16(CAN1_MBIM1, val)
|
||||
#define bfin_read_CAN1_RFH1() bfin_read16(CAN1_RFH1)
|
||||
#define bfin_write_CAN1_RFH1(val) bfin_write16(CAN1_RFH1, val)
|
||||
#define bfin_read_CAN1_OPSS1() bfin_read16(CAN1_OPSS1)
|
||||
#define bfin_write_CAN1_OPSS1(val) bfin_write16(CAN1_OPSS1, val)
|
||||
|
||||
/* CAN Controller 1 Config 2 Registers */
|
||||
|
||||
#define bfin_read_CAN1_MC2() bfin_read16(CAN1_MC2)
|
||||
#define bfin_write_CAN1_MC2(val) bfin_write16(CAN1_MC2, val)
|
||||
#define bfin_read_CAN1_MD2() bfin_read16(CAN1_MD2)
|
||||
#define bfin_write_CAN1_MD2(val) bfin_write16(CAN1_MD2, val)
|
||||
#define bfin_read_CAN1_TRS2() bfin_read16(CAN1_TRS2)
|
||||
#define bfin_write_CAN1_TRS2(val) bfin_write16(CAN1_TRS2, val)
|
||||
#define bfin_read_CAN1_TRR2() bfin_read16(CAN1_TRR2)
|
||||
#define bfin_write_CAN1_TRR2(val) bfin_write16(CAN1_TRR2, val)
|
||||
#define bfin_read_CAN1_TA2() bfin_read16(CAN1_TA2)
|
||||
#define bfin_write_CAN1_TA2(val) bfin_write16(CAN1_TA2, val)
|
||||
#define bfin_read_CAN1_AA2() bfin_read16(CAN1_AA2)
|
||||
#define bfin_write_CAN1_AA2(val) bfin_write16(CAN1_AA2, val)
|
||||
#define bfin_read_CAN1_RMP2() bfin_read16(CAN1_RMP2)
|
||||
#define bfin_write_CAN1_RMP2(val) bfin_write16(CAN1_RMP2, val)
|
||||
#define bfin_read_CAN1_RML2() bfin_read16(CAN1_RML2)
|
||||
#define bfin_write_CAN1_RML2(val) bfin_write16(CAN1_RML2, val)
|
||||
#define bfin_read_CAN1_MBTIF2() bfin_read16(CAN1_MBTIF2)
|
||||
#define bfin_write_CAN1_MBTIF2(val) bfin_write16(CAN1_MBTIF2, val)
|
||||
#define bfin_read_CAN1_MBRIF2() bfin_read16(CAN1_MBRIF2)
|
||||
#define bfin_write_CAN1_MBRIF2(val) bfin_write16(CAN1_MBRIF2, val)
|
||||
#define bfin_read_CAN1_MBIM2() bfin_read16(CAN1_MBIM2)
|
||||
#define bfin_write_CAN1_MBIM2(val) bfin_write16(CAN1_MBIM2, val)
|
||||
#define bfin_read_CAN1_RFH2() bfin_read16(CAN1_RFH2)
|
||||
#define bfin_write_CAN1_RFH2(val) bfin_write16(CAN1_RFH2, val)
|
||||
#define bfin_read_CAN1_OPSS2() bfin_read16(CAN1_OPSS2)
|
||||
#define bfin_write_CAN1_OPSS2(val) bfin_write16(CAN1_OPSS2, val)
|
||||
|
||||
/* CAN Controller 1 Clock/Interrubfin_read_()t/Counter Registers */
|
||||
|
||||
#define bfin_read_CAN1_CLOCK() bfin_read16(CAN1_CLOCK)
|
||||
#define bfin_write_CAN1_CLOCK(val) bfin_write16(CAN1_CLOCK, val)
|
||||
#define bfin_read_CAN1_TIMING() bfin_read16(CAN1_TIMING)
|
||||
#define bfin_write_CAN1_TIMING(val) bfin_write16(CAN1_TIMING, val)
|
||||
#define bfin_read_CAN1_DEBUG() bfin_read16(CAN1_DEBUG)
|
||||
#define bfin_write_CAN1_DEBUG(val) bfin_write16(CAN1_DEBUG, val)
|
||||
#define bfin_read_CAN1_STATUS() bfin_read16(CAN1_STATUS)
|
||||
#define bfin_write_CAN1_STATUS(val) bfin_write16(CAN1_STATUS, val)
|
||||
#define bfin_read_CAN1_CEC() bfin_read16(CAN1_CEC)
|
||||
#define bfin_write_CAN1_CEC(val) bfin_write16(CAN1_CEC, val)
|
||||
#define bfin_read_CAN1_GIS() bfin_read16(CAN1_GIS)
|
||||
#define bfin_write_CAN1_GIS(val) bfin_write16(CAN1_GIS, val)
|
||||
#define bfin_read_CAN1_GIM() bfin_read16(CAN1_GIM)
|
||||
#define bfin_write_CAN1_GIM(val) bfin_write16(CAN1_GIM, val)
|
||||
#define bfin_read_CAN1_GIF() bfin_read16(CAN1_GIF)
|
||||
#define bfin_write_CAN1_GIF(val) bfin_write16(CAN1_GIF, val)
|
||||
#define bfin_read_CAN1_CONTROL() bfin_read16(CAN1_CONTROL)
|
||||
#define bfin_write_CAN1_CONTROL(val) bfin_write16(CAN1_CONTROL, val)
|
||||
#define bfin_read_CAN1_INTR() bfin_read16(CAN1_INTR)
|
||||
#define bfin_write_CAN1_INTR(val) bfin_write16(CAN1_INTR, val)
|
||||
#define bfin_read_CAN1_MBTD() bfin_read16(CAN1_MBTD)
|
||||
#define bfin_write_CAN1_MBTD(val) bfin_write16(CAN1_MBTD, val)
|
||||
#define bfin_read_CAN1_EWR() bfin_read16(CAN1_EWR)
|
||||
#define bfin_write_CAN1_EWR(val) bfin_write16(CAN1_EWR, val)
|
||||
#define bfin_read_CAN1_ESR() bfin_read16(CAN1_ESR)
|
||||
#define bfin_write_CAN1_ESR(val) bfin_write16(CAN1_ESR, val)
|
||||
#define bfin_read_CAN1_UCCNT() bfin_read16(CAN1_UCCNT)
|
||||
#define bfin_write_CAN1_UCCNT(val) bfin_write16(CAN1_UCCNT, val)
|
||||
#define bfin_read_CAN1_UCRC() bfin_read16(CAN1_UCRC)
|
||||
#define bfin_write_CAN1_UCRC(val) bfin_write16(CAN1_UCRC, val)
|
||||
#define bfin_read_CAN1_UCCNF() bfin_read16(CAN1_UCCNF)
|
||||
#define bfin_write_CAN1_UCCNF(val) bfin_write16(CAN1_UCCNF, val)
|
||||
|
||||
/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
|
||||
|
||||
#define bfin_read_CAN1_AM00L() bfin_read16(CAN1_AM00L)
|
||||
#define bfin_write_CAN1_AM00L(val) bfin_write16(CAN1_AM00L, val)
|
||||
#define bfin_read_CAN1_AM00H() bfin_read16(CAN1_AM00H)
|
||||
#define bfin_write_CAN1_AM00H(val) bfin_write16(CAN1_AM00H, val)
|
||||
#define bfin_read_CAN1_AM01L() bfin_read16(CAN1_AM01L)
|
||||
#define bfin_write_CAN1_AM01L(val) bfin_write16(CAN1_AM01L, val)
|
||||
#define bfin_read_CAN1_AM01H() bfin_read16(CAN1_AM01H)
|
||||
#define bfin_write_CAN1_AM01H(val) bfin_write16(CAN1_AM01H, val)
|
||||
#define bfin_read_CAN1_AM02L() bfin_read16(CAN1_AM02L)
|
||||
#define bfin_write_CAN1_AM02L(val) bfin_write16(CAN1_AM02L, val)
|
||||
#define bfin_read_CAN1_AM02H() bfin_read16(CAN1_AM02H)
|
||||
#define bfin_write_CAN1_AM02H(val) bfin_write16(CAN1_AM02H, val)
|
||||
#define bfin_read_CAN1_AM03L() bfin_read16(CAN1_AM03L)
|
||||
#define bfin_write_CAN1_AM03L(val) bfin_write16(CAN1_AM03L, val)
|
||||
#define bfin_read_CAN1_AM03H() bfin_read16(CAN1_AM03H)
|
||||
#define bfin_write_CAN1_AM03H(val) bfin_write16(CAN1_AM03H, val)
|
||||
#define bfin_read_CAN1_AM04L() bfin_read16(CAN1_AM04L)
|
||||
#define bfin_write_CAN1_AM04L(val) bfin_write16(CAN1_AM04L, val)
|
||||
#define bfin_read_CAN1_AM04H() bfin_read16(CAN1_AM04H)
|
||||
#define bfin_write_CAN1_AM04H(val) bfin_write16(CAN1_AM04H, val)
|
||||
#define bfin_read_CAN1_AM05L() bfin_read16(CAN1_AM05L)
|
||||
#define bfin_write_CAN1_AM05L(val) bfin_write16(CAN1_AM05L, val)
|
||||
#define bfin_read_CAN1_AM05H() bfin_read16(CAN1_AM05H)
|
||||
#define bfin_write_CAN1_AM05H(val) bfin_write16(CAN1_AM05H, val)
|
||||
#define bfin_read_CAN1_AM06L() bfin_read16(CAN1_AM06L)
|
||||
#define bfin_write_CAN1_AM06L(val) bfin_write16(CAN1_AM06L, val)
|
||||
#define bfin_read_CAN1_AM06H() bfin_read16(CAN1_AM06H)
|
||||
#define bfin_write_CAN1_AM06H(val) bfin_write16(CAN1_AM06H, val)
|
||||
#define bfin_read_CAN1_AM07L() bfin_read16(CAN1_AM07L)
|
||||
#define bfin_write_CAN1_AM07L(val) bfin_write16(CAN1_AM07L, val)
|
||||
#define bfin_read_CAN1_AM07H() bfin_read16(CAN1_AM07H)
|
||||
#define bfin_write_CAN1_AM07H(val) bfin_write16(CAN1_AM07H, val)
|
||||
#define bfin_read_CAN1_AM08L() bfin_read16(CAN1_AM08L)
|
||||
#define bfin_write_CAN1_AM08L(val) bfin_write16(CAN1_AM08L, val)
|
||||
#define bfin_read_CAN1_AM08H() bfin_read16(CAN1_AM08H)
|
||||
#define bfin_write_CAN1_AM08H(val) bfin_write16(CAN1_AM08H, val)
|
||||
#define bfin_read_CAN1_AM09L() bfin_read16(CAN1_AM09L)
|
||||
#define bfin_write_CAN1_AM09L(val) bfin_write16(CAN1_AM09L, val)
|
||||
#define bfin_read_CAN1_AM09H() bfin_read16(CAN1_AM09H)
|
||||
#define bfin_write_CAN1_AM09H(val) bfin_write16(CAN1_AM09H, val)
|
||||
#define bfin_read_CAN1_AM10L() bfin_read16(CAN1_AM10L)
|
||||
#define bfin_write_CAN1_AM10L(val) bfin_write16(CAN1_AM10L, val)
|
||||
#define bfin_read_CAN1_AM10H() bfin_read16(CAN1_AM10H)
|
||||
#define bfin_write_CAN1_AM10H(val) bfin_write16(CAN1_AM10H, val)
|
||||
#define bfin_read_CAN1_AM11L() bfin_read16(CAN1_AM11L)
|
||||
#define bfin_write_CAN1_AM11L(val) bfin_write16(CAN1_AM11L, val)
|
||||
#define bfin_read_CAN1_AM11H() bfin_read16(CAN1_AM11H)
|
||||
#define bfin_write_CAN1_AM11H(val) bfin_write16(CAN1_AM11H, val)
|
||||
#define bfin_read_CAN1_AM12L() bfin_read16(CAN1_AM12L)
|
||||
#define bfin_write_CAN1_AM12L(val) bfin_write16(CAN1_AM12L, val)
|
||||
#define bfin_read_CAN1_AM12H() bfin_read16(CAN1_AM12H)
|
||||
#define bfin_write_CAN1_AM12H(val) bfin_write16(CAN1_AM12H, val)
|
||||
#define bfin_read_CAN1_AM13L() bfin_read16(CAN1_AM13L)
|
||||
#define bfin_write_CAN1_AM13L(val) bfin_write16(CAN1_AM13L, val)
|
||||
#define bfin_read_CAN1_AM13H() bfin_read16(CAN1_AM13H)
|
||||
#define bfin_write_CAN1_AM13H(val) bfin_write16(CAN1_AM13H, val)
|
||||
#define bfin_read_CAN1_AM14L() bfin_read16(CAN1_AM14L)
|
||||
#define bfin_write_CAN1_AM14L(val) bfin_write16(CAN1_AM14L, val)
|
||||
#define bfin_read_CAN1_AM14H() bfin_read16(CAN1_AM14H)
|
||||
#define bfin_write_CAN1_AM14H(val) bfin_write16(CAN1_AM14H, val)
|
||||
#define bfin_read_CAN1_AM15L() bfin_read16(CAN1_AM15L)
|
||||
#define bfin_write_CAN1_AM15L(val) bfin_write16(CAN1_AM15L, val)
|
||||
#define bfin_read_CAN1_AM15H() bfin_read16(CAN1_AM15H)
|
||||
#define bfin_write_CAN1_AM15H(val) bfin_write16(CAN1_AM15H, val)
|
||||
|
||||
/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
|
||||
|
||||
#define bfin_read_CAN1_AM16L() bfin_read16(CAN1_AM16L)
|
||||
#define bfin_write_CAN1_AM16L(val) bfin_write16(CAN1_AM16L, val)
|
||||
#define bfin_read_CAN1_AM16H() bfin_read16(CAN1_AM16H)
|
||||
#define bfin_write_CAN1_AM16H(val) bfin_write16(CAN1_AM16H, val)
|
||||
#define bfin_read_CAN1_AM17L() bfin_read16(CAN1_AM17L)
|
||||
#define bfin_write_CAN1_AM17L(val) bfin_write16(CAN1_AM17L, val)
|
||||
#define bfin_read_CAN1_AM17H() bfin_read16(CAN1_AM17H)
|
||||
#define bfin_write_CAN1_AM17H(val) bfin_write16(CAN1_AM17H, val)
|
||||
#define bfin_read_CAN1_AM18L() bfin_read16(CAN1_AM18L)
|
||||
#define bfin_write_CAN1_AM18L(val) bfin_write16(CAN1_AM18L, val)
|
||||
#define bfin_read_CAN1_AM18H() bfin_read16(CAN1_AM18H)
|
||||
#define bfin_write_CAN1_AM18H(val) bfin_write16(CAN1_AM18H, val)
|
||||
#define bfin_read_CAN1_AM19L() bfin_read16(CAN1_AM19L)
|
||||
#define bfin_write_CAN1_AM19L(val) bfin_write16(CAN1_AM19L, val)
|
||||
#define bfin_read_CAN1_AM19H() bfin_read16(CAN1_AM19H)
|
||||
#define bfin_write_CAN1_AM19H(val) bfin_write16(CAN1_AM19H, val)
|
||||
#define bfin_read_CAN1_AM20L() bfin_read16(CAN1_AM20L)
|
||||
#define bfin_write_CAN1_AM20L(val) bfin_write16(CAN1_AM20L, val)
|
||||
#define bfin_read_CAN1_AM20H() bfin_read16(CAN1_AM20H)
|
||||
#define bfin_write_CAN1_AM20H(val) bfin_write16(CAN1_AM20H, val)
|
||||
#define bfin_read_CAN1_AM21L() bfin_read16(CAN1_AM21L)
|
||||
#define bfin_write_CAN1_AM21L(val) bfin_write16(CAN1_AM21L, val)
|
||||
#define bfin_read_CAN1_AM21H() bfin_read16(CAN1_AM21H)
|
||||
#define bfin_write_CAN1_AM21H(val) bfin_write16(CAN1_AM21H, val)
|
||||
#define bfin_read_CAN1_AM22L() bfin_read16(CAN1_AM22L)
|
||||
#define bfin_write_CAN1_AM22L(val) bfin_write16(CAN1_AM22L, val)
|
||||
#define bfin_read_CAN1_AM22H() bfin_read16(CAN1_AM22H)
|
||||
#define bfin_write_CAN1_AM22H(val) bfin_write16(CAN1_AM22H, val)
|
||||
#define bfin_read_CAN1_AM23L() bfin_read16(CAN1_AM23L)
|
||||
#define bfin_write_CAN1_AM23L(val) bfin_write16(CAN1_AM23L, val)
|
||||
#define bfin_read_CAN1_AM23H() bfin_read16(CAN1_AM23H)
|
||||
#define bfin_write_CAN1_AM23H(val) bfin_write16(CAN1_AM23H, val)
|
||||
#define bfin_read_CAN1_AM24L() bfin_read16(CAN1_AM24L)
|
||||
#define bfin_write_CAN1_AM24L(val) bfin_write16(CAN1_AM24L, val)
|
||||
#define bfin_read_CAN1_AM24H() bfin_read16(CAN1_AM24H)
|
||||
#define bfin_write_CAN1_AM24H(val) bfin_write16(CAN1_AM24H, val)
|
||||
#define bfin_read_CAN1_AM25L() bfin_read16(CAN1_AM25L)
|
||||
#define bfin_write_CAN1_AM25L(val) bfin_write16(CAN1_AM25L, val)
|
||||
#define bfin_read_CAN1_AM25H() bfin_read16(CAN1_AM25H)
|
||||
#define bfin_write_CAN1_AM25H(val) bfin_write16(CAN1_AM25H, val)
|
||||
#define bfin_read_CAN1_AM26L() bfin_read16(CAN1_AM26L)
|
||||
#define bfin_write_CAN1_AM26L(val) bfin_write16(CAN1_AM26L, val)
|
||||
#define bfin_read_CAN1_AM26H() bfin_read16(CAN1_AM26H)
|
||||
#define bfin_write_CAN1_AM26H(val) bfin_write16(CAN1_AM26H, val)
|
||||
#define bfin_read_CAN1_AM27L() bfin_read16(CAN1_AM27L)
|
||||
#define bfin_write_CAN1_AM27L(val) bfin_write16(CAN1_AM27L, val)
|
||||
#define bfin_read_CAN1_AM27H() bfin_read16(CAN1_AM27H)
|
||||
#define bfin_write_CAN1_AM27H(val) bfin_write16(CAN1_AM27H, val)
|
||||
#define bfin_read_CAN1_AM28L() bfin_read16(CAN1_AM28L)
|
||||
#define bfin_write_CAN1_AM28L(val) bfin_write16(CAN1_AM28L, val)
|
||||
#define bfin_read_CAN1_AM28H() bfin_read16(CAN1_AM28H)
|
||||
#define bfin_write_CAN1_AM28H(val) bfin_write16(CAN1_AM28H, val)
|
||||
#define bfin_read_CAN1_AM29L() bfin_read16(CAN1_AM29L)
|
||||
#define bfin_write_CAN1_AM29L(val) bfin_write16(CAN1_AM29L, val)
|
||||
#define bfin_read_CAN1_AM29H() bfin_read16(CAN1_AM29H)
|
||||
#define bfin_write_CAN1_AM29H(val) bfin_write16(CAN1_AM29H, val)
|
||||
#define bfin_read_CAN1_AM30L() bfin_read16(CAN1_AM30L)
|
||||
#define bfin_write_CAN1_AM30L(val) bfin_write16(CAN1_AM30L, val)
|
||||
#define bfin_read_CAN1_AM30H() bfin_read16(CAN1_AM30H)
|
||||
#define bfin_write_CAN1_AM30H(val) bfin_write16(CAN1_AM30H, val)
|
||||
#define bfin_read_CAN1_AM31L() bfin_read16(CAN1_AM31L)
|
||||
#define bfin_write_CAN1_AM31L(val) bfin_write16(CAN1_AM31L, val)
|
||||
#define bfin_read_CAN1_AM31H() bfin_read16(CAN1_AM31H)
|
||||
#define bfin_write_CAN1_AM31H(val) bfin_write16(CAN1_AM31H, val)
|
||||
|
||||
/* CAN Controller 1 Mailbox Data Registers */
|
||||
|
||||
#define bfin_read_CAN1_MB00_DATA0() bfin_read16(CAN1_MB00_DATA0)
|
||||
#define bfin_write_CAN1_MB00_DATA0(val) bfin_write16(CAN1_MB00_DATA0, val)
|
||||
#define bfin_read_CAN1_MB00_DATA1() bfin_read16(CAN1_MB00_DATA1)
|
||||
#define bfin_write_CAN1_MB00_DATA1(val) bfin_write16(CAN1_MB00_DATA1, val)
|
||||
#define bfin_read_CAN1_MB00_DATA2() bfin_read16(CAN1_MB00_DATA2)
|
||||
#define bfin_write_CAN1_MB00_DATA2(val) bfin_write16(CAN1_MB00_DATA2, val)
|
||||
#define bfin_read_CAN1_MB00_DATA3() bfin_read16(CAN1_MB00_DATA3)
|
||||
#define bfin_write_CAN1_MB00_DATA3(val) bfin_write16(CAN1_MB00_DATA3, val)
|
||||
#define bfin_read_CAN1_MB00_LENGTH() bfin_read16(CAN1_MB00_LENGTH)
|
||||
#define bfin_write_CAN1_MB00_LENGTH(val) bfin_write16(CAN1_MB00_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB00_TIMESTAMP() bfin_read16(CAN1_MB00_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB00_TIMESTAMP(val) bfin_write16(CAN1_MB00_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB00_ID0() bfin_read16(CAN1_MB00_ID0)
|
||||
#define bfin_write_CAN1_MB00_ID0(val) bfin_write16(CAN1_MB00_ID0, val)
|
||||
#define bfin_read_CAN1_MB00_ID1() bfin_read16(CAN1_MB00_ID1)
|
||||
#define bfin_write_CAN1_MB00_ID1(val) bfin_write16(CAN1_MB00_ID1, val)
|
||||
#define bfin_read_CAN1_MB01_DATA0() bfin_read16(CAN1_MB01_DATA0)
|
||||
#define bfin_write_CAN1_MB01_DATA0(val) bfin_write16(CAN1_MB01_DATA0, val)
|
||||
#define bfin_read_CAN1_MB01_DATA1() bfin_read16(CAN1_MB01_DATA1)
|
||||
#define bfin_write_CAN1_MB01_DATA1(val) bfin_write16(CAN1_MB01_DATA1, val)
|
||||
#define bfin_read_CAN1_MB01_DATA2() bfin_read16(CAN1_MB01_DATA2)
|
||||
#define bfin_write_CAN1_MB01_DATA2(val) bfin_write16(CAN1_MB01_DATA2, val)
|
||||
#define bfin_read_CAN1_MB01_DATA3() bfin_read16(CAN1_MB01_DATA3)
|
||||
#define bfin_write_CAN1_MB01_DATA3(val) bfin_write16(CAN1_MB01_DATA3, val)
|
||||
#define bfin_read_CAN1_MB01_LENGTH() bfin_read16(CAN1_MB01_LENGTH)
|
||||
#define bfin_write_CAN1_MB01_LENGTH(val) bfin_write16(CAN1_MB01_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB01_TIMESTAMP() bfin_read16(CAN1_MB01_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB01_TIMESTAMP(val) bfin_write16(CAN1_MB01_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB01_ID0() bfin_read16(CAN1_MB01_ID0)
|
||||
#define bfin_write_CAN1_MB01_ID0(val) bfin_write16(CAN1_MB01_ID0, val)
|
||||
#define bfin_read_CAN1_MB01_ID1() bfin_read16(CAN1_MB01_ID1)
|
||||
#define bfin_write_CAN1_MB01_ID1(val) bfin_write16(CAN1_MB01_ID1, val)
|
||||
#define bfin_read_CAN1_MB02_DATA0() bfin_read16(CAN1_MB02_DATA0)
|
||||
#define bfin_write_CAN1_MB02_DATA0(val) bfin_write16(CAN1_MB02_DATA0, val)
|
||||
#define bfin_read_CAN1_MB02_DATA1() bfin_read16(CAN1_MB02_DATA1)
|
||||
#define bfin_write_CAN1_MB02_DATA1(val) bfin_write16(CAN1_MB02_DATA1, val)
|
||||
#define bfin_read_CAN1_MB02_DATA2() bfin_read16(CAN1_MB02_DATA2)
|
||||
#define bfin_write_CAN1_MB02_DATA2(val) bfin_write16(CAN1_MB02_DATA2, val)
|
||||
#define bfin_read_CAN1_MB02_DATA3() bfin_read16(CAN1_MB02_DATA3)
|
||||
#define bfin_write_CAN1_MB02_DATA3(val) bfin_write16(CAN1_MB02_DATA3, val)
|
||||
#define bfin_read_CAN1_MB02_LENGTH() bfin_read16(CAN1_MB02_LENGTH)
|
||||
#define bfin_write_CAN1_MB02_LENGTH(val) bfin_write16(CAN1_MB02_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB02_TIMESTAMP() bfin_read16(CAN1_MB02_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB02_TIMESTAMP(val) bfin_write16(CAN1_MB02_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB02_ID0() bfin_read16(CAN1_MB02_ID0)
|
||||
#define bfin_write_CAN1_MB02_ID0(val) bfin_write16(CAN1_MB02_ID0, val)
|
||||
#define bfin_read_CAN1_MB02_ID1() bfin_read16(CAN1_MB02_ID1)
|
||||
#define bfin_write_CAN1_MB02_ID1(val) bfin_write16(CAN1_MB02_ID1, val)
|
||||
#define bfin_read_CAN1_MB03_DATA0() bfin_read16(CAN1_MB03_DATA0)
|
||||
#define bfin_write_CAN1_MB03_DATA0(val) bfin_write16(CAN1_MB03_DATA0, val)
|
||||
#define bfin_read_CAN1_MB03_DATA1() bfin_read16(CAN1_MB03_DATA1)
|
||||
#define bfin_write_CAN1_MB03_DATA1(val) bfin_write16(CAN1_MB03_DATA1, val)
|
||||
#define bfin_read_CAN1_MB03_DATA2() bfin_read16(CAN1_MB03_DATA2)
|
||||
#define bfin_write_CAN1_MB03_DATA2(val) bfin_write16(CAN1_MB03_DATA2, val)
|
||||
#define bfin_read_CAN1_MB03_DATA3() bfin_read16(CAN1_MB03_DATA3)
|
||||
#define bfin_write_CAN1_MB03_DATA3(val) bfin_write16(CAN1_MB03_DATA3, val)
|
||||
#define bfin_read_CAN1_MB03_LENGTH() bfin_read16(CAN1_MB03_LENGTH)
|
||||
#define bfin_write_CAN1_MB03_LENGTH(val) bfin_write16(CAN1_MB03_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB03_TIMESTAMP() bfin_read16(CAN1_MB03_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB03_TIMESTAMP(val) bfin_write16(CAN1_MB03_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB03_ID0() bfin_read16(CAN1_MB03_ID0)
|
||||
#define bfin_write_CAN1_MB03_ID0(val) bfin_write16(CAN1_MB03_ID0, val)
|
||||
#define bfin_read_CAN1_MB03_ID1() bfin_read16(CAN1_MB03_ID1)
|
||||
#define bfin_write_CAN1_MB03_ID1(val) bfin_write16(CAN1_MB03_ID1, val)
|
||||
#define bfin_read_CAN1_MB04_DATA0() bfin_read16(CAN1_MB04_DATA0)
|
||||
#define bfin_write_CAN1_MB04_DATA0(val) bfin_write16(CAN1_MB04_DATA0, val)
|
||||
#define bfin_read_CAN1_MB04_DATA1() bfin_read16(CAN1_MB04_DATA1)
|
||||
#define bfin_write_CAN1_MB04_DATA1(val) bfin_write16(CAN1_MB04_DATA1, val)
|
||||
#define bfin_read_CAN1_MB04_DATA2() bfin_read16(CAN1_MB04_DATA2)
|
||||
#define bfin_write_CAN1_MB04_DATA2(val) bfin_write16(CAN1_MB04_DATA2, val)
|
||||
#define bfin_read_CAN1_MB04_DATA3() bfin_read16(CAN1_MB04_DATA3)
|
||||
#define bfin_write_CAN1_MB04_DATA3(val) bfin_write16(CAN1_MB04_DATA3, val)
|
||||
#define bfin_read_CAN1_MB04_LENGTH() bfin_read16(CAN1_MB04_LENGTH)
|
||||
#define bfin_write_CAN1_MB04_LENGTH(val) bfin_write16(CAN1_MB04_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB04_TIMESTAMP() bfin_read16(CAN1_MB04_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB04_TIMESTAMP(val) bfin_write16(CAN1_MB04_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB04_ID0() bfin_read16(CAN1_MB04_ID0)
|
||||
#define bfin_write_CAN1_MB04_ID0(val) bfin_write16(CAN1_MB04_ID0, val)
|
||||
#define bfin_read_CAN1_MB04_ID1() bfin_read16(CAN1_MB04_ID1)
|
||||
#define bfin_write_CAN1_MB04_ID1(val) bfin_write16(CAN1_MB04_ID1, val)
|
||||
#define bfin_read_CAN1_MB05_DATA0() bfin_read16(CAN1_MB05_DATA0)
|
||||
#define bfin_write_CAN1_MB05_DATA0(val) bfin_write16(CAN1_MB05_DATA0, val)
|
||||
#define bfin_read_CAN1_MB05_DATA1() bfin_read16(CAN1_MB05_DATA1)
|
||||
#define bfin_write_CAN1_MB05_DATA1(val) bfin_write16(CAN1_MB05_DATA1, val)
|
||||
#define bfin_read_CAN1_MB05_DATA2() bfin_read16(CAN1_MB05_DATA2)
|
||||
#define bfin_write_CAN1_MB05_DATA2(val) bfin_write16(CAN1_MB05_DATA2, val)
|
||||
#define bfin_read_CAN1_MB05_DATA3() bfin_read16(CAN1_MB05_DATA3)
|
||||
#define bfin_write_CAN1_MB05_DATA3(val) bfin_write16(CAN1_MB05_DATA3, val)
|
||||
#define bfin_read_CAN1_MB05_LENGTH() bfin_read16(CAN1_MB05_LENGTH)
|
||||
#define bfin_write_CAN1_MB05_LENGTH(val) bfin_write16(CAN1_MB05_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB05_TIMESTAMP() bfin_read16(CAN1_MB05_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB05_TIMESTAMP(val) bfin_write16(CAN1_MB05_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB05_ID0() bfin_read16(CAN1_MB05_ID0)
|
||||
#define bfin_write_CAN1_MB05_ID0(val) bfin_write16(CAN1_MB05_ID0, val)
|
||||
#define bfin_read_CAN1_MB05_ID1() bfin_read16(CAN1_MB05_ID1)
|
||||
#define bfin_write_CAN1_MB05_ID1(val) bfin_write16(CAN1_MB05_ID1, val)
|
||||
#define bfin_read_CAN1_MB06_DATA0() bfin_read16(CAN1_MB06_DATA0)
|
||||
#define bfin_write_CAN1_MB06_DATA0(val) bfin_write16(CAN1_MB06_DATA0, val)
|
||||
#define bfin_read_CAN1_MB06_DATA1() bfin_read16(CAN1_MB06_DATA1)
|
||||
#define bfin_write_CAN1_MB06_DATA1(val) bfin_write16(CAN1_MB06_DATA1, val)
|
||||
#define bfin_read_CAN1_MB06_DATA2() bfin_read16(CAN1_MB06_DATA2)
|
||||
#define bfin_write_CAN1_MB06_DATA2(val) bfin_write16(CAN1_MB06_DATA2, val)
|
||||
#define bfin_read_CAN1_MB06_DATA3() bfin_read16(CAN1_MB06_DATA3)
|
||||
#define bfin_write_CAN1_MB06_DATA3(val) bfin_write16(CAN1_MB06_DATA3, val)
|
||||
#define bfin_read_CAN1_MB06_LENGTH() bfin_read16(CAN1_MB06_LENGTH)
|
||||
#define bfin_write_CAN1_MB06_LENGTH(val) bfin_write16(CAN1_MB06_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB06_TIMESTAMP() bfin_read16(CAN1_MB06_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB06_TIMESTAMP(val) bfin_write16(CAN1_MB06_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB06_ID0() bfin_read16(CAN1_MB06_ID0)
|
||||
#define bfin_write_CAN1_MB06_ID0(val) bfin_write16(CAN1_MB06_ID0, val)
|
||||
#define bfin_read_CAN1_MB06_ID1() bfin_read16(CAN1_MB06_ID1)
|
||||
#define bfin_write_CAN1_MB06_ID1(val) bfin_write16(CAN1_MB06_ID1, val)
|
||||
#define bfin_read_CAN1_MB07_DATA0() bfin_read16(CAN1_MB07_DATA0)
|
||||
#define bfin_write_CAN1_MB07_DATA0(val) bfin_write16(CAN1_MB07_DATA0, val)
|
||||
#define bfin_read_CAN1_MB07_DATA1() bfin_read16(CAN1_MB07_DATA1)
|
||||
#define bfin_write_CAN1_MB07_DATA1(val) bfin_write16(CAN1_MB07_DATA1, val)
|
||||
#define bfin_read_CAN1_MB07_DATA2() bfin_read16(CAN1_MB07_DATA2)
|
||||
#define bfin_write_CAN1_MB07_DATA2(val) bfin_write16(CAN1_MB07_DATA2, val)
|
||||
#define bfin_read_CAN1_MB07_DATA3() bfin_read16(CAN1_MB07_DATA3)
|
||||
#define bfin_write_CAN1_MB07_DATA3(val) bfin_write16(CAN1_MB07_DATA3, val)
|
||||
#define bfin_read_CAN1_MB07_LENGTH() bfin_read16(CAN1_MB07_LENGTH)
|
||||
#define bfin_write_CAN1_MB07_LENGTH(val) bfin_write16(CAN1_MB07_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB07_TIMESTAMP() bfin_read16(CAN1_MB07_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB07_TIMESTAMP(val) bfin_write16(CAN1_MB07_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB07_ID0() bfin_read16(CAN1_MB07_ID0)
|
||||
#define bfin_write_CAN1_MB07_ID0(val) bfin_write16(CAN1_MB07_ID0, val)
|
||||
#define bfin_read_CAN1_MB07_ID1() bfin_read16(CAN1_MB07_ID1)
|
||||
#define bfin_write_CAN1_MB07_ID1(val) bfin_write16(CAN1_MB07_ID1, val)
|
||||
#define bfin_read_CAN1_MB08_DATA0() bfin_read16(CAN1_MB08_DATA0)
|
||||
#define bfin_write_CAN1_MB08_DATA0(val) bfin_write16(CAN1_MB08_DATA0, val)
|
||||
#define bfin_read_CAN1_MB08_DATA1() bfin_read16(CAN1_MB08_DATA1)
|
||||
#define bfin_write_CAN1_MB08_DATA1(val) bfin_write16(CAN1_MB08_DATA1, val)
|
||||
#define bfin_read_CAN1_MB08_DATA2() bfin_read16(CAN1_MB08_DATA2)
|
||||
#define bfin_write_CAN1_MB08_DATA2(val) bfin_write16(CAN1_MB08_DATA2, val)
|
||||
#define bfin_read_CAN1_MB08_DATA3() bfin_read16(CAN1_MB08_DATA3)
|
||||
#define bfin_write_CAN1_MB08_DATA3(val) bfin_write16(CAN1_MB08_DATA3, val)
|
||||
#define bfin_read_CAN1_MB08_LENGTH() bfin_read16(CAN1_MB08_LENGTH)
|
||||
#define bfin_write_CAN1_MB08_LENGTH(val) bfin_write16(CAN1_MB08_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB08_TIMESTAMP() bfin_read16(CAN1_MB08_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB08_TIMESTAMP(val) bfin_write16(CAN1_MB08_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB08_ID0() bfin_read16(CAN1_MB08_ID0)
|
||||
#define bfin_write_CAN1_MB08_ID0(val) bfin_write16(CAN1_MB08_ID0, val)
|
||||
#define bfin_read_CAN1_MB08_ID1() bfin_read16(CAN1_MB08_ID1)
|
||||
#define bfin_write_CAN1_MB08_ID1(val) bfin_write16(CAN1_MB08_ID1, val)
|
||||
#define bfin_read_CAN1_MB09_DATA0() bfin_read16(CAN1_MB09_DATA0)
|
||||
#define bfin_write_CAN1_MB09_DATA0(val) bfin_write16(CAN1_MB09_DATA0, val)
|
||||
#define bfin_read_CAN1_MB09_DATA1() bfin_read16(CAN1_MB09_DATA1)
|
||||
#define bfin_write_CAN1_MB09_DATA1(val) bfin_write16(CAN1_MB09_DATA1, val)
|
||||
#define bfin_read_CAN1_MB09_DATA2() bfin_read16(CAN1_MB09_DATA2)
|
||||
#define bfin_write_CAN1_MB09_DATA2(val) bfin_write16(CAN1_MB09_DATA2, val)
|
||||
#define bfin_read_CAN1_MB09_DATA3() bfin_read16(CAN1_MB09_DATA3)
|
||||
#define bfin_write_CAN1_MB09_DATA3(val) bfin_write16(CAN1_MB09_DATA3, val)
|
||||
#define bfin_read_CAN1_MB09_LENGTH() bfin_read16(CAN1_MB09_LENGTH)
|
||||
#define bfin_write_CAN1_MB09_LENGTH(val) bfin_write16(CAN1_MB09_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB09_TIMESTAMP() bfin_read16(CAN1_MB09_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB09_TIMESTAMP(val) bfin_write16(CAN1_MB09_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB09_ID0() bfin_read16(CAN1_MB09_ID0)
|
||||
#define bfin_write_CAN1_MB09_ID0(val) bfin_write16(CAN1_MB09_ID0, val)
|
||||
#define bfin_read_CAN1_MB09_ID1() bfin_read16(CAN1_MB09_ID1)
|
||||
#define bfin_write_CAN1_MB09_ID1(val) bfin_write16(CAN1_MB09_ID1, val)
|
||||
#define bfin_read_CAN1_MB10_DATA0() bfin_read16(CAN1_MB10_DATA0)
|
||||
#define bfin_write_CAN1_MB10_DATA0(val) bfin_write16(CAN1_MB10_DATA0, val)
|
||||
#define bfin_read_CAN1_MB10_DATA1() bfin_read16(CAN1_MB10_DATA1)
|
||||
#define bfin_write_CAN1_MB10_DATA1(val) bfin_write16(CAN1_MB10_DATA1, val)
|
||||
#define bfin_read_CAN1_MB10_DATA2() bfin_read16(CAN1_MB10_DATA2)
|
||||
#define bfin_write_CAN1_MB10_DATA2(val) bfin_write16(CAN1_MB10_DATA2, val)
|
||||
#define bfin_read_CAN1_MB10_DATA3() bfin_read16(CAN1_MB10_DATA3)
|
||||
#define bfin_write_CAN1_MB10_DATA3(val) bfin_write16(CAN1_MB10_DATA3, val)
|
||||
#define bfin_read_CAN1_MB10_LENGTH() bfin_read16(CAN1_MB10_LENGTH)
|
||||
#define bfin_write_CAN1_MB10_LENGTH(val) bfin_write16(CAN1_MB10_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB10_TIMESTAMP() bfin_read16(CAN1_MB10_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB10_TIMESTAMP(val) bfin_write16(CAN1_MB10_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB10_ID0() bfin_read16(CAN1_MB10_ID0)
|
||||
#define bfin_write_CAN1_MB10_ID0(val) bfin_write16(CAN1_MB10_ID0, val)
|
||||
#define bfin_read_CAN1_MB10_ID1() bfin_read16(CAN1_MB10_ID1)
|
||||
#define bfin_write_CAN1_MB10_ID1(val) bfin_write16(CAN1_MB10_ID1, val)
|
||||
#define bfin_read_CAN1_MB11_DATA0() bfin_read16(CAN1_MB11_DATA0)
|
||||
#define bfin_write_CAN1_MB11_DATA0(val) bfin_write16(CAN1_MB11_DATA0, val)
|
||||
#define bfin_read_CAN1_MB11_DATA1() bfin_read16(CAN1_MB11_DATA1)
|
||||
#define bfin_write_CAN1_MB11_DATA1(val) bfin_write16(CAN1_MB11_DATA1, val)
|
||||
#define bfin_read_CAN1_MB11_DATA2() bfin_read16(CAN1_MB11_DATA2)
|
||||
#define bfin_write_CAN1_MB11_DATA2(val) bfin_write16(CAN1_MB11_DATA2, val)
|
||||
#define bfin_read_CAN1_MB11_DATA3() bfin_read16(CAN1_MB11_DATA3)
|
||||
#define bfin_write_CAN1_MB11_DATA3(val) bfin_write16(CAN1_MB11_DATA3, val)
|
||||
#define bfin_read_CAN1_MB11_LENGTH() bfin_read16(CAN1_MB11_LENGTH)
|
||||
#define bfin_write_CAN1_MB11_LENGTH(val) bfin_write16(CAN1_MB11_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB11_TIMESTAMP() bfin_read16(CAN1_MB11_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB11_TIMESTAMP(val) bfin_write16(CAN1_MB11_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB11_ID0() bfin_read16(CAN1_MB11_ID0)
|
||||
#define bfin_write_CAN1_MB11_ID0(val) bfin_write16(CAN1_MB11_ID0, val)
|
||||
#define bfin_read_CAN1_MB11_ID1() bfin_read16(CAN1_MB11_ID1)
|
||||
#define bfin_write_CAN1_MB11_ID1(val) bfin_write16(CAN1_MB11_ID1, val)
|
||||
#define bfin_read_CAN1_MB12_DATA0() bfin_read16(CAN1_MB12_DATA0)
|
||||
#define bfin_write_CAN1_MB12_DATA0(val) bfin_write16(CAN1_MB12_DATA0, val)
|
||||
#define bfin_read_CAN1_MB12_DATA1() bfin_read16(CAN1_MB12_DATA1)
|
||||
#define bfin_write_CAN1_MB12_DATA1(val) bfin_write16(CAN1_MB12_DATA1, val)
|
||||
#define bfin_read_CAN1_MB12_DATA2() bfin_read16(CAN1_MB12_DATA2)
|
||||
#define bfin_write_CAN1_MB12_DATA2(val) bfin_write16(CAN1_MB12_DATA2, val)
|
||||
#define bfin_read_CAN1_MB12_DATA3() bfin_read16(CAN1_MB12_DATA3)
|
||||
#define bfin_write_CAN1_MB12_DATA3(val) bfin_write16(CAN1_MB12_DATA3, val)
|
||||
#define bfin_read_CAN1_MB12_LENGTH() bfin_read16(CAN1_MB12_LENGTH)
|
||||
#define bfin_write_CAN1_MB12_LENGTH(val) bfin_write16(CAN1_MB12_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB12_TIMESTAMP() bfin_read16(CAN1_MB12_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB12_TIMESTAMP(val) bfin_write16(CAN1_MB12_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB12_ID0() bfin_read16(CAN1_MB12_ID0)
|
||||
#define bfin_write_CAN1_MB12_ID0(val) bfin_write16(CAN1_MB12_ID0, val)
|
||||
#define bfin_read_CAN1_MB12_ID1() bfin_read16(CAN1_MB12_ID1)
|
||||
#define bfin_write_CAN1_MB12_ID1(val) bfin_write16(CAN1_MB12_ID1, val)
|
||||
#define bfin_read_CAN1_MB13_DATA0() bfin_read16(CAN1_MB13_DATA0)
|
||||
#define bfin_write_CAN1_MB13_DATA0(val) bfin_write16(CAN1_MB13_DATA0, val)
|
||||
#define bfin_read_CAN1_MB13_DATA1() bfin_read16(CAN1_MB13_DATA1)
|
||||
#define bfin_write_CAN1_MB13_DATA1(val) bfin_write16(CAN1_MB13_DATA1, val)
|
||||
#define bfin_read_CAN1_MB13_DATA2() bfin_read16(CAN1_MB13_DATA2)
|
||||
#define bfin_write_CAN1_MB13_DATA2(val) bfin_write16(CAN1_MB13_DATA2, val)
|
||||
#define bfin_read_CAN1_MB13_DATA3() bfin_read16(CAN1_MB13_DATA3)
|
||||
#define bfin_write_CAN1_MB13_DATA3(val) bfin_write16(CAN1_MB13_DATA3, val)
|
||||
#define bfin_read_CAN1_MB13_LENGTH() bfin_read16(CAN1_MB13_LENGTH)
|
||||
#define bfin_write_CAN1_MB13_LENGTH(val) bfin_write16(CAN1_MB13_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB13_TIMESTAMP() bfin_read16(CAN1_MB13_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB13_TIMESTAMP(val) bfin_write16(CAN1_MB13_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB13_ID0() bfin_read16(CAN1_MB13_ID0)
|
||||
#define bfin_write_CAN1_MB13_ID0(val) bfin_write16(CAN1_MB13_ID0, val)
|
||||
#define bfin_read_CAN1_MB13_ID1() bfin_read16(CAN1_MB13_ID1)
|
||||
#define bfin_write_CAN1_MB13_ID1(val) bfin_write16(CAN1_MB13_ID1, val)
|
||||
#define bfin_read_CAN1_MB14_DATA0() bfin_read16(CAN1_MB14_DATA0)
|
||||
#define bfin_write_CAN1_MB14_DATA0(val) bfin_write16(CAN1_MB14_DATA0, val)
|
||||
#define bfin_read_CAN1_MB14_DATA1() bfin_read16(CAN1_MB14_DATA1)
|
||||
#define bfin_write_CAN1_MB14_DATA1(val) bfin_write16(CAN1_MB14_DATA1, val)
|
||||
#define bfin_read_CAN1_MB14_DATA2() bfin_read16(CAN1_MB14_DATA2)
|
||||
#define bfin_write_CAN1_MB14_DATA2(val) bfin_write16(CAN1_MB14_DATA2, val)
|
||||
#define bfin_read_CAN1_MB14_DATA3() bfin_read16(CAN1_MB14_DATA3)
|
||||
#define bfin_write_CAN1_MB14_DATA3(val) bfin_write16(CAN1_MB14_DATA3, val)
|
||||
#define bfin_read_CAN1_MB14_LENGTH() bfin_read16(CAN1_MB14_LENGTH)
|
||||
#define bfin_write_CAN1_MB14_LENGTH(val) bfin_write16(CAN1_MB14_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB14_TIMESTAMP() bfin_read16(CAN1_MB14_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB14_TIMESTAMP(val) bfin_write16(CAN1_MB14_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB14_ID0() bfin_read16(CAN1_MB14_ID0)
|
||||
#define bfin_write_CAN1_MB14_ID0(val) bfin_write16(CAN1_MB14_ID0, val)
|
||||
#define bfin_read_CAN1_MB14_ID1() bfin_read16(CAN1_MB14_ID1)
|
||||
#define bfin_write_CAN1_MB14_ID1(val) bfin_write16(CAN1_MB14_ID1, val)
|
||||
#define bfin_read_CAN1_MB15_DATA0() bfin_read16(CAN1_MB15_DATA0)
|
||||
#define bfin_write_CAN1_MB15_DATA0(val) bfin_write16(CAN1_MB15_DATA0, val)
|
||||
#define bfin_read_CAN1_MB15_DATA1() bfin_read16(CAN1_MB15_DATA1)
|
||||
#define bfin_write_CAN1_MB15_DATA1(val) bfin_write16(CAN1_MB15_DATA1, val)
|
||||
#define bfin_read_CAN1_MB15_DATA2() bfin_read16(CAN1_MB15_DATA2)
|
||||
#define bfin_write_CAN1_MB15_DATA2(val) bfin_write16(CAN1_MB15_DATA2, val)
|
||||
#define bfin_read_CAN1_MB15_DATA3() bfin_read16(CAN1_MB15_DATA3)
|
||||
#define bfin_write_CAN1_MB15_DATA3(val) bfin_write16(CAN1_MB15_DATA3, val)
|
||||
#define bfin_read_CAN1_MB15_LENGTH() bfin_read16(CAN1_MB15_LENGTH)
|
||||
#define bfin_write_CAN1_MB15_LENGTH(val) bfin_write16(CAN1_MB15_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB15_TIMESTAMP() bfin_read16(CAN1_MB15_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB15_TIMESTAMP(val) bfin_write16(CAN1_MB15_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB15_ID0() bfin_read16(CAN1_MB15_ID0)
|
||||
#define bfin_write_CAN1_MB15_ID0(val) bfin_write16(CAN1_MB15_ID0, val)
|
||||
#define bfin_read_CAN1_MB15_ID1() bfin_read16(CAN1_MB15_ID1)
|
||||
#define bfin_write_CAN1_MB15_ID1(val) bfin_write16(CAN1_MB15_ID1, val)
|
||||
|
||||
/* CAN Controller 1 Mailbox Data Registers */
|
||||
|
||||
#define bfin_read_CAN1_MB16_DATA0() bfin_read16(CAN1_MB16_DATA0)
|
||||
#define bfin_write_CAN1_MB16_DATA0(val) bfin_write16(CAN1_MB16_DATA0, val)
|
||||
#define bfin_read_CAN1_MB16_DATA1() bfin_read16(CAN1_MB16_DATA1)
|
||||
#define bfin_write_CAN1_MB16_DATA1(val) bfin_write16(CAN1_MB16_DATA1, val)
|
||||
#define bfin_read_CAN1_MB16_DATA2() bfin_read16(CAN1_MB16_DATA2)
|
||||
#define bfin_write_CAN1_MB16_DATA2(val) bfin_write16(CAN1_MB16_DATA2, val)
|
||||
#define bfin_read_CAN1_MB16_DATA3() bfin_read16(CAN1_MB16_DATA3)
|
||||
#define bfin_write_CAN1_MB16_DATA3(val) bfin_write16(CAN1_MB16_DATA3, val)
|
||||
#define bfin_read_CAN1_MB16_LENGTH() bfin_read16(CAN1_MB16_LENGTH)
|
||||
#define bfin_write_CAN1_MB16_LENGTH(val) bfin_write16(CAN1_MB16_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB16_TIMESTAMP() bfin_read16(CAN1_MB16_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB16_TIMESTAMP(val) bfin_write16(CAN1_MB16_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB16_ID0() bfin_read16(CAN1_MB16_ID0)
|
||||
#define bfin_write_CAN1_MB16_ID0(val) bfin_write16(CAN1_MB16_ID0, val)
|
||||
#define bfin_read_CAN1_MB16_ID1() bfin_read16(CAN1_MB16_ID1)
|
||||
#define bfin_write_CAN1_MB16_ID1(val) bfin_write16(CAN1_MB16_ID1, val)
|
||||
#define bfin_read_CAN1_MB17_DATA0() bfin_read16(CAN1_MB17_DATA0)
|
||||
#define bfin_write_CAN1_MB17_DATA0(val) bfin_write16(CAN1_MB17_DATA0, val)
|
||||
#define bfin_read_CAN1_MB17_DATA1() bfin_read16(CAN1_MB17_DATA1)
|
||||
#define bfin_write_CAN1_MB17_DATA1(val) bfin_write16(CAN1_MB17_DATA1, val)
|
||||
#define bfin_read_CAN1_MB17_DATA2() bfin_read16(CAN1_MB17_DATA2)
|
||||
#define bfin_write_CAN1_MB17_DATA2(val) bfin_write16(CAN1_MB17_DATA2, val)
|
||||
#define bfin_read_CAN1_MB17_DATA3() bfin_read16(CAN1_MB17_DATA3)
|
||||
#define bfin_write_CAN1_MB17_DATA3(val) bfin_write16(CAN1_MB17_DATA3, val)
|
||||
#define bfin_read_CAN1_MB17_LENGTH() bfin_read16(CAN1_MB17_LENGTH)
|
||||
#define bfin_write_CAN1_MB17_LENGTH(val) bfin_write16(CAN1_MB17_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB17_TIMESTAMP() bfin_read16(CAN1_MB17_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB17_TIMESTAMP(val) bfin_write16(CAN1_MB17_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB17_ID0() bfin_read16(CAN1_MB17_ID0)
|
||||
#define bfin_write_CAN1_MB17_ID0(val) bfin_write16(CAN1_MB17_ID0, val)
|
||||
#define bfin_read_CAN1_MB17_ID1() bfin_read16(CAN1_MB17_ID1)
|
||||
#define bfin_write_CAN1_MB17_ID1(val) bfin_write16(CAN1_MB17_ID1, val)
|
||||
#define bfin_read_CAN1_MB18_DATA0() bfin_read16(CAN1_MB18_DATA0)
|
||||
#define bfin_write_CAN1_MB18_DATA0(val) bfin_write16(CAN1_MB18_DATA0, val)
|
||||
#define bfin_read_CAN1_MB18_DATA1() bfin_read16(CAN1_MB18_DATA1)
|
||||
#define bfin_write_CAN1_MB18_DATA1(val) bfin_write16(CAN1_MB18_DATA1, val)
|
||||
#define bfin_read_CAN1_MB18_DATA2() bfin_read16(CAN1_MB18_DATA2)
|
||||
#define bfin_write_CAN1_MB18_DATA2(val) bfin_write16(CAN1_MB18_DATA2, val)
|
||||
#define bfin_read_CAN1_MB18_DATA3() bfin_read16(CAN1_MB18_DATA3)
|
||||
#define bfin_write_CAN1_MB18_DATA3(val) bfin_write16(CAN1_MB18_DATA3, val)
|
||||
#define bfin_read_CAN1_MB18_LENGTH() bfin_read16(CAN1_MB18_LENGTH)
|
||||
#define bfin_write_CAN1_MB18_LENGTH(val) bfin_write16(CAN1_MB18_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB18_TIMESTAMP() bfin_read16(CAN1_MB18_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB18_TIMESTAMP(val) bfin_write16(CAN1_MB18_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB18_ID0() bfin_read16(CAN1_MB18_ID0)
|
||||
#define bfin_write_CAN1_MB18_ID0(val) bfin_write16(CAN1_MB18_ID0, val)
|
||||
#define bfin_read_CAN1_MB18_ID1() bfin_read16(CAN1_MB18_ID1)
|
||||
#define bfin_write_CAN1_MB18_ID1(val) bfin_write16(CAN1_MB18_ID1, val)
|
||||
#define bfin_read_CAN1_MB19_DATA0() bfin_read16(CAN1_MB19_DATA0)
|
||||
#define bfin_write_CAN1_MB19_DATA0(val) bfin_write16(CAN1_MB19_DATA0, val)
|
||||
#define bfin_read_CAN1_MB19_DATA1() bfin_read16(CAN1_MB19_DATA1)
|
||||
#define bfin_write_CAN1_MB19_DATA1(val) bfin_write16(CAN1_MB19_DATA1, val)
|
||||
#define bfin_read_CAN1_MB19_DATA2() bfin_read16(CAN1_MB19_DATA2)
|
||||
#define bfin_write_CAN1_MB19_DATA2(val) bfin_write16(CAN1_MB19_DATA2, val)
|
||||
#define bfin_read_CAN1_MB19_DATA3() bfin_read16(CAN1_MB19_DATA3)
|
||||
#define bfin_write_CAN1_MB19_DATA3(val) bfin_write16(CAN1_MB19_DATA3, val)
|
||||
#define bfin_read_CAN1_MB19_LENGTH() bfin_read16(CAN1_MB19_LENGTH)
|
||||
#define bfin_write_CAN1_MB19_LENGTH(val) bfin_write16(CAN1_MB19_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB19_TIMESTAMP() bfin_read16(CAN1_MB19_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB19_TIMESTAMP(val) bfin_write16(CAN1_MB19_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB19_ID0() bfin_read16(CAN1_MB19_ID0)
|
||||
#define bfin_write_CAN1_MB19_ID0(val) bfin_write16(CAN1_MB19_ID0, val)
|
||||
#define bfin_read_CAN1_MB19_ID1() bfin_read16(CAN1_MB19_ID1)
|
||||
#define bfin_write_CAN1_MB19_ID1(val) bfin_write16(CAN1_MB19_ID1, val)
|
||||
#define bfin_read_CAN1_MB20_DATA0() bfin_read16(CAN1_MB20_DATA0)
|
||||
#define bfin_write_CAN1_MB20_DATA0(val) bfin_write16(CAN1_MB20_DATA0, val)
|
||||
#define bfin_read_CAN1_MB20_DATA1() bfin_read16(CAN1_MB20_DATA1)
|
||||
#define bfin_write_CAN1_MB20_DATA1(val) bfin_write16(CAN1_MB20_DATA1, val)
|
||||
#define bfin_read_CAN1_MB20_DATA2() bfin_read16(CAN1_MB20_DATA2)
|
||||
#define bfin_write_CAN1_MB20_DATA2(val) bfin_write16(CAN1_MB20_DATA2, val)
|
||||
#define bfin_read_CAN1_MB20_DATA3() bfin_read16(CAN1_MB20_DATA3)
|
||||
#define bfin_write_CAN1_MB20_DATA3(val) bfin_write16(CAN1_MB20_DATA3, val)
|
||||
#define bfin_read_CAN1_MB20_LENGTH() bfin_read16(CAN1_MB20_LENGTH)
|
||||
#define bfin_write_CAN1_MB20_LENGTH(val) bfin_write16(CAN1_MB20_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB20_TIMESTAMP() bfin_read16(CAN1_MB20_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB20_TIMESTAMP(val) bfin_write16(CAN1_MB20_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB20_ID0() bfin_read16(CAN1_MB20_ID0)
|
||||
#define bfin_write_CAN1_MB20_ID0(val) bfin_write16(CAN1_MB20_ID0, val)
|
||||
#define bfin_read_CAN1_MB20_ID1() bfin_read16(CAN1_MB20_ID1)
|
||||
#define bfin_write_CAN1_MB20_ID1(val) bfin_write16(CAN1_MB20_ID1, val)
|
||||
#define bfin_read_CAN1_MB21_DATA0() bfin_read16(CAN1_MB21_DATA0)
|
||||
#define bfin_write_CAN1_MB21_DATA0(val) bfin_write16(CAN1_MB21_DATA0, val)
|
||||
#define bfin_read_CAN1_MB21_DATA1() bfin_read16(CAN1_MB21_DATA1)
|
||||
#define bfin_write_CAN1_MB21_DATA1(val) bfin_write16(CAN1_MB21_DATA1, val)
|
||||
#define bfin_read_CAN1_MB21_DATA2() bfin_read16(CAN1_MB21_DATA2)
|
||||
#define bfin_write_CAN1_MB21_DATA2(val) bfin_write16(CAN1_MB21_DATA2, val)
|
||||
#define bfin_read_CAN1_MB21_DATA3() bfin_read16(CAN1_MB21_DATA3)
|
||||
#define bfin_write_CAN1_MB21_DATA3(val) bfin_write16(CAN1_MB21_DATA3, val)
|
||||
#define bfin_read_CAN1_MB21_LENGTH() bfin_read16(CAN1_MB21_LENGTH)
|
||||
#define bfin_write_CAN1_MB21_LENGTH(val) bfin_write16(CAN1_MB21_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB21_TIMESTAMP() bfin_read16(CAN1_MB21_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB21_TIMESTAMP(val) bfin_write16(CAN1_MB21_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB21_ID0() bfin_read16(CAN1_MB21_ID0)
|
||||
#define bfin_write_CAN1_MB21_ID0(val) bfin_write16(CAN1_MB21_ID0, val)
|
||||
#define bfin_read_CAN1_MB21_ID1() bfin_read16(CAN1_MB21_ID1)
|
||||
#define bfin_write_CAN1_MB21_ID1(val) bfin_write16(CAN1_MB21_ID1, val)
|
||||
#define bfin_read_CAN1_MB22_DATA0() bfin_read16(CAN1_MB22_DATA0)
|
||||
#define bfin_write_CAN1_MB22_DATA0(val) bfin_write16(CAN1_MB22_DATA0, val)
|
||||
#define bfin_read_CAN1_MB22_DATA1() bfin_read16(CAN1_MB22_DATA1)
|
||||
#define bfin_write_CAN1_MB22_DATA1(val) bfin_write16(CAN1_MB22_DATA1, val)
|
||||
#define bfin_read_CAN1_MB22_DATA2() bfin_read16(CAN1_MB22_DATA2)
|
||||
#define bfin_write_CAN1_MB22_DATA2(val) bfin_write16(CAN1_MB22_DATA2, val)
|
||||
#define bfin_read_CAN1_MB22_DATA3() bfin_read16(CAN1_MB22_DATA3)
|
||||
#define bfin_write_CAN1_MB22_DATA3(val) bfin_write16(CAN1_MB22_DATA3, val)
|
||||
#define bfin_read_CAN1_MB22_LENGTH() bfin_read16(CAN1_MB22_LENGTH)
|
||||
#define bfin_write_CAN1_MB22_LENGTH(val) bfin_write16(CAN1_MB22_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB22_TIMESTAMP() bfin_read16(CAN1_MB22_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB22_TIMESTAMP(val) bfin_write16(CAN1_MB22_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB22_ID0() bfin_read16(CAN1_MB22_ID0)
|
||||
#define bfin_write_CAN1_MB22_ID0(val) bfin_write16(CAN1_MB22_ID0, val)
|
||||
#define bfin_read_CAN1_MB22_ID1() bfin_read16(CAN1_MB22_ID1)
|
||||
#define bfin_write_CAN1_MB22_ID1(val) bfin_write16(CAN1_MB22_ID1, val)
|
||||
#define bfin_read_CAN1_MB23_DATA0() bfin_read16(CAN1_MB23_DATA0)
|
||||
#define bfin_write_CAN1_MB23_DATA0(val) bfin_write16(CAN1_MB23_DATA0, val)
|
||||
#define bfin_read_CAN1_MB23_DATA1() bfin_read16(CAN1_MB23_DATA1)
|
||||
#define bfin_write_CAN1_MB23_DATA1(val) bfin_write16(CAN1_MB23_DATA1, val)
|
||||
#define bfin_read_CAN1_MB23_DATA2() bfin_read16(CAN1_MB23_DATA2)
|
||||
#define bfin_write_CAN1_MB23_DATA2(val) bfin_write16(CAN1_MB23_DATA2, val)
|
||||
#define bfin_read_CAN1_MB23_DATA3() bfin_read16(CAN1_MB23_DATA3)
|
||||
#define bfin_write_CAN1_MB23_DATA3(val) bfin_write16(CAN1_MB23_DATA3, val)
|
||||
#define bfin_read_CAN1_MB23_LENGTH() bfin_read16(CAN1_MB23_LENGTH)
|
||||
#define bfin_write_CAN1_MB23_LENGTH(val) bfin_write16(CAN1_MB23_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB23_TIMESTAMP() bfin_read16(CAN1_MB23_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB23_TIMESTAMP(val) bfin_write16(CAN1_MB23_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB23_ID0() bfin_read16(CAN1_MB23_ID0)
|
||||
#define bfin_write_CAN1_MB23_ID0(val) bfin_write16(CAN1_MB23_ID0, val)
|
||||
#define bfin_read_CAN1_MB23_ID1() bfin_read16(CAN1_MB23_ID1)
|
||||
#define bfin_write_CAN1_MB23_ID1(val) bfin_write16(CAN1_MB23_ID1, val)
|
||||
#define bfin_read_CAN1_MB24_DATA0() bfin_read16(CAN1_MB24_DATA0)
|
||||
#define bfin_write_CAN1_MB24_DATA0(val) bfin_write16(CAN1_MB24_DATA0, val)
|
||||
#define bfin_read_CAN1_MB24_DATA1() bfin_read16(CAN1_MB24_DATA1)
|
||||
#define bfin_write_CAN1_MB24_DATA1(val) bfin_write16(CAN1_MB24_DATA1, val)
|
||||
#define bfin_read_CAN1_MB24_DATA2() bfin_read16(CAN1_MB24_DATA2)
|
||||
#define bfin_write_CAN1_MB24_DATA2(val) bfin_write16(CAN1_MB24_DATA2, val)
|
||||
#define bfin_read_CAN1_MB24_DATA3() bfin_read16(CAN1_MB24_DATA3)
|
||||
#define bfin_write_CAN1_MB24_DATA3(val) bfin_write16(CAN1_MB24_DATA3, val)
|
||||
#define bfin_read_CAN1_MB24_LENGTH() bfin_read16(CAN1_MB24_LENGTH)
|
||||
#define bfin_write_CAN1_MB24_LENGTH(val) bfin_write16(CAN1_MB24_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB24_TIMESTAMP() bfin_read16(CAN1_MB24_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB24_TIMESTAMP(val) bfin_write16(CAN1_MB24_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB24_ID0() bfin_read16(CAN1_MB24_ID0)
|
||||
#define bfin_write_CAN1_MB24_ID0(val) bfin_write16(CAN1_MB24_ID0, val)
|
||||
#define bfin_read_CAN1_MB24_ID1() bfin_read16(CAN1_MB24_ID1)
|
||||
#define bfin_write_CAN1_MB24_ID1(val) bfin_write16(CAN1_MB24_ID1, val)
|
||||
#define bfin_read_CAN1_MB25_DATA0() bfin_read16(CAN1_MB25_DATA0)
|
||||
#define bfin_write_CAN1_MB25_DATA0(val) bfin_write16(CAN1_MB25_DATA0, val)
|
||||
#define bfin_read_CAN1_MB25_DATA1() bfin_read16(CAN1_MB25_DATA1)
|
||||
#define bfin_write_CAN1_MB25_DATA1(val) bfin_write16(CAN1_MB25_DATA1, val)
|
||||
#define bfin_read_CAN1_MB25_DATA2() bfin_read16(CAN1_MB25_DATA2)
|
||||
#define bfin_write_CAN1_MB25_DATA2(val) bfin_write16(CAN1_MB25_DATA2, val)
|
||||
#define bfin_read_CAN1_MB25_DATA3() bfin_read16(CAN1_MB25_DATA3)
|
||||
#define bfin_write_CAN1_MB25_DATA3(val) bfin_write16(CAN1_MB25_DATA3, val)
|
||||
#define bfin_read_CAN1_MB25_LENGTH() bfin_read16(CAN1_MB25_LENGTH)
|
||||
#define bfin_write_CAN1_MB25_LENGTH(val) bfin_write16(CAN1_MB25_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB25_TIMESTAMP() bfin_read16(CAN1_MB25_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB25_TIMESTAMP(val) bfin_write16(CAN1_MB25_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB25_ID0() bfin_read16(CAN1_MB25_ID0)
|
||||
#define bfin_write_CAN1_MB25_ID0(val) bfin_write16(CAN1_MB25_ID0, val)
|
||||
#define bfin_read_CAN1_MB25_ID1() bfin_read16(CAN1_MB25_ID1)
|
||||
#define bfin_write_CAN1_MB25_ID1(val) bfin_write16(CAN1_MB25_ID1, val)
|
||||
#define bfin_read_CAN1_MB26_DATA0() bfin_read16(CAN1_MB26_DATA0)
|
||||
#define bfin_write_CAN1_MB26_DATA0(val) bfin_write16(CAN1_MB26_DATA0, val)
|
||||
#define bfin_read_CAN1_MB26_DATA1() bfin_read16(CAN1_MB26_DATA1)
|
||||
#define bfin_write_CAN1_MB26_DATA1(val) bfin_write16(CAN1_MB26_DATA1, val)
|
||||
#define bfin_read_CAN1_MB26_DATA2() bfin_read16(CAN1_MB26_DATA2)
|
||||
#define bfin_write_CAN1_MB26_DATA2(val) bfin_write16(CAN1_MB26_DATA2, val)
|
||||
#define bfin_read_CAN1_MB26_DATA3() bfin_read16(CAN1_MB26_DATA3)
|
||||
#define bfin_write_CAN1_MB26_DATA3(val) bfin_write16(CAN1_MB26_DATA3, val)
|
||||
#define bfin_read_CAN1_MB26_LENGTH() bfin_read16(CAN1_MB26_LENGTH)
|
||||
#define bfin_write_CAN1_MB26_LENGTH(val) bfin_write16(CAN1_MB26_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB26_TIMESTAMP() bfin_read16(CAN1_MB26_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB26_TIMESTAMP(val) bfin_write16(CAN1_MB26_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB26_ID0() bfin_read16(CAN1_MB26_ID0)
|
||||
#define bfin_write_CAN1_MB26_ID0(val) bfin_write16(CAN1_MB26_ID0, val)
|
||||
#define bfin_read_CAN1_MB26_ID1() bfin_read16(CAN1_MB26_ID1)
|
||||
#define bfin_write_CAN1_MB26_ID1(val) bfin_write16(CAN1_MB26_ID1, val)
|
||||
#define bfin_read_CAN1_MB27_DATA0() bfin_read16(CAN1_MB27_DATA0)
|
||||
#define bfin_write_CAN1_MB27_DATA0(val) bfin_write16(CAN1_MB27_DATA0, val)
|
||||
#define bfin_read_CAN1_MB27_DATA1() bfin_read16(CAN1_MB27_DATA1)
|
||||
#define bfin_write_CAN1_MB27_DATA1(val) bfin_write16(CAN1_MB27_DATA1, val)
|
||||
#define bfin_read_CAN1_MB27_DATA2() bfin_read16(CAN1_MB27_DATA2)
|
||||
#define bfin_write_CAN1_MB27_DATA2(val) bfin_write16(CAN1_MB27_DATA2, val)
|
||||
#define bfin_read_CAN1_MB27_DATA3() bfin_read16(CAN1_MB27_DATA3)
|
||||
#define bfin_write_CAN1_MB27_DATA3(val) bfin_write16(CAN1_MB27_DATA3, val)
|
||||
#define bfin_read_CAN1_MB27_LENGTH() bfin_read16(CAN1_MB27_LENGTH)
|
||||
#define bfin_write_CAN1_MB27_LENGTH(val) bfin_write16(CAN1_MB27_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB27_TIMESTAMP() bfin_read16(CAN1_MB27_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB27_TIMESTAMP(val) bfin_write16(CAN1_MB27_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB27_ID0() bfin_read16(CAN1_MB27_ID0)
|
||||
#define bfin_write_CAN1_MB27_ID0(val) bfin_write16(CAN1_MB27_ID0, val)
|
||||
#define bfin_read_CAN1_MB27_ID1() bfin_read16(CAN1_MB27_ID1)
|
||||
#define bfin_write_CAN1_MB27_ID1(val) bfin_write16(CAN1_MB27_ID1, val)
|
||||
#define bfin_read_CAN1_MB28_DATA0() bfin_read16(CAN1_MB28_DATA0)
|
||||
#define bfin_write_CAN1_MB28_DATA0(val) bfin_write16(CAN1_MB28_DATA0, val)
|
||||
#define bfin_read_CAN1_MB28_DATA1() bfin_read16(CAN1_MB28_DATA1)
|
||||
#define bfin_write_CAN1_MB28_DATA1(val) bfin_write16(CAN1_MB28_DATA1, val)
|
||||
#define bfin_read_CAN1_MB28_DATA2() bfin_read16(CAN1_MB28_DATA2)
|
||||
#define bfin_write_CAN1_MB28_DATA2(val) bfin_write16(CAN1_MB28_DATA2, val)
|
||||
#define bfin_read_CAN1_MB28_DATA3() bfin_read16(CAN1_MB28_DATA3)
|
||||
#define bfin_write_CAN1_MB28_DATA3(val) bfin_write16(CAN1_MB28_DATA3, val)
|
||||
#define bfin_read_CAN1_MB28_LENGTH() bfin_read16(CAN1_MB28_LENGTH)
|
||||
#define bfin_write_CAN1_MB28_LENGTH(val) bfin_write16(CAN1_MB28_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB28_TIMESTAMP() bfin_read16(CAN1_MB28_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB28_TIMESTAMP(val) bfin_write16(CAN1_MB28_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB28_ID0() bfin_read16(CAN1_MB28_ID0)
|
||||
#define bfin_write_CAN1_MB28_ID0(val) bfin_write16(CAN1_MB28_ID0, val)
|
||||
#define bfin_read_CAN1_MB28_ID1() bfin_read16(CAN1_MB28_ID1)
|
||||
#define bfin_write_CAN1_MB28_ID1(val) bfin_write16(CAN1_MB28_ID1, val)
|
||||
#define bfin_read_CAN1_MB29_DATA0() bfin_read16(CAN1_MB29_DATA0)
|
||||
#define bfin_write_CAN1_MB29_DATA0(val) bfin_write16(CAN1_MB29_DATA0, val)
|
||||
#define bfin_read_CAN1_MB29_DATA1() bfin_read16(CAN1_MB29_DATA1)
|
||||
#define bfin_write_CAN1_MB29_DATA1(val) bfin_write16(CAN1_MB29_DATA1, val)
|
||||
#define bfin_read_CAN1_MB29_DATA2() bfin_read16(CAN1_MB29_DATA2)
|
||||
#define bfin_write_CAN1_MB29_DATA2(val) bfin_write16(CAN1_MB29_DATA2, val)
|
||||
#define bfin_read_CAN1_MB29_DATA3() bfin_read16(CAN1_MB29_DATA3)
|
||||
#define bfin_write_CAN1_MB29_DATA3(val) bfin_write16(CAN1_MB29_DATA3, val)
|
||||
#define bfin_read_CAN1_MB29_LENGTH() bfin_read16(CAN1_MB29_LENGTH)
|
||||
#define bfin_write_CAN1_MB29_LENGTH(val) bfin_write16(CAN1_MB29_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB29_TIMESTAMP() bfin_read16(CAN1_MB29_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB29_TIMESTAMP(val) bfin_write16(CAN1_MB29_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB29_ID0() bfin_read16(CAN1_MB29_ID0)
|
||||
#define bfin_write_CAN1_MB29_ID0(val) bfin_write16(CAN1_MB29_ID0, val)
|
||||
#define bfin_read_CAN1_MB29_ID1() bfin_read16(CAN1_MB29_ID1)
|
||||
#define bfin_write_CAN1_MB29_ID1(val) bfin_write16(CAN1_MB29_ID1, val)
|
||||
#define bfin_read_CAN1_MB30_DATA0() bfin_read16(CAN1_MB30_DATA0)
|
||||
#define bfin_write_CAN1_MB30_DATA0(val) bfin_write16(CAN1_MB30_DATA0, val)
|
||||
#define bfin_read_CAN1_MB30_DATA1() bfin_read16(CAN1_MB30_DATA1)
|
||||
#define bfin_write_CAN1_MB30_DATA1(val) bfin_write16(CAN1_MB30_DATA1, val)
|
||||
#define bfin_read_CAN1_MB30_DATA2() bfin_read16(CAN1_MB30_DATA2)
|
||||
#define bfin_write_CAN1_MB30_DATA2(val) bfin_write16(CAN1_MB30_DATA2, val)
|
||||
#define bfin_read_CAN1_MB30_DATA3() bfin_read16(CAN1_MB30_DATA3)
|
||||
#define bfin_write_CAN1_MB30_DATA3(val) bfin_write16(CAN1_MB30_DATA3, val)
|
||||
#define bfin_read_CAN1_MB30_LENGTH() bfin_read16(CAN1_MB30_LENGTH)
|
||||
#define bfin_write_CAN1_MB30_LENGTH(val) bfin_write16(CAN1_MB30_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB30_TIMESTAMP() bfin_read16(CAN1_MB30_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB30_TIMESTAMP(val) bfin_write16(CAN1_MB30_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB30_ID0() bfin_read16(CAN1_MB30_ID0)
|
||||
#define bfin_write_CAN1_MB30_ID0(val) bfin_write16(CAN1_MB30_ID0, val)
|
||||
#define bfin_read_CAN1_MB30_ID1() bfin_read16(CAN1_MB30_ID1)
|
||||
#define bfin_write_CAN1_MB30_ID1(val) bfin_write16(CAN1_MB30_ID1, val)
|
||||
#define bfin_read_CAN1_MB31_DATA0() bfin_read16(CAN1_MB31_DATA0)
|
||||
#define bfin_write_CAN1_MB31_DATA0(val) bfin_write16(CAN1_MB31_DATA0, val)
|
||||
#define bfin_read_CAN1_MB31_DATA1() bfin_read16(CAN1_MB31_DATA1)
|
||||
#define bfin_write_CAN1_MB31_DATA1(val) bfin_write16(CAN1_MB31_DATA1, val)
|
||||
#define bfin_read_CAN1_MB31_DATA2() bfin_read16(CAN1_MB31_DATA2)
|
||||
#define bfin_write_CAN1_MB31_DATA2(val) bfin_write16(CAN1_MB31_DATA2, val)
|
||||
#define bfin_read_CAN1_MB31_DATA3() bfin_read16(CAN1_MB31_DATA3)
|
||||
#define bfin_write_CAN1_MB31_DATA3(val) bfin_write16(CAN1_MB31_DATA3, val)
|
||||
#define bfin_read_CAN1_MB31_LENGTH() bfin_read16(CAN1_MB31_LENGTH)
|
||||
#define bfin_write_CAN1_MB31_LENGTH(val) bfin_write16(CAN1_MB31_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB31_TIMESTAMP() bfin_read16(CAN1_MB31_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB31_TIMESTAMP(val) bfin_write16(CAN1_MB31_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB31_ID0() bfin_read16(CAN1_MB31_ID0)
|
||||
#define bfin_write_CAN1_MB31_ID0(val) bfin_write16(CAN1_MB31_ID0, val)
|
||||
#define bfin_read_CAN1_MB31_ID1() bfin_read16(CAN1_MB31_ID1)
|
||||
#define bfin_write_CAN1_MB31_ID1(val) bfin_write16(CAN1_MB31_ID1, val)
|
||||
|
||||
/* HOST Port Registers */
|
||||
|
||||
#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL)
|
||||
#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
|
||||
#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS)
|
||||
#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
|
||||
#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT)
|
||||
#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
|
||||
|
||||
/* Pixel Combfin_read_()ositor (PIXC) Registers */
|
||||
|
||||
#define bfin_read_PIXC_CTL() bfin_read16(PIXC_CTL)
|
||||
#define bfin_write_PIXC_CTL(val) bfin_write16(PIXC_CTL, val)
|
||||
#define bfin_read_PIXC_PPL() bfin_read16(PIXC_PPL)
|
||||
#define bfin_write_PIXC_PPL(val) bfin_write16(PIXC_PPL, val)
|
||||
#define bfin_read_PIXC_LPF() bfin_read16(PIXC_LPF)
|
||||
#define bfin_write_PIXC_LPF(val) bfin_write16(PIXC_LPF, val)
|
||||
#define bfin_read_PIXC_AHSTART() bfin_read16(PIXC_AHSTART)
|
||||
#define bfin_write_PIXC_AHSTART(val) bfin_write16(PIXC_AHSTART, val)
|
||||
#define bfin_read_PIXC_AHEND() bfin_read16(PIXC_AHEND)
|
||||
#define bfin_write_PIXC_AHEND(val) bfin_write16(PIXC_AHEND, val)
|
||||
#define bfin_read_PIXC_AVSTART() bfin_read16(PIXC_AVSTART)
|
||||
#define bfin_write_PIXC_AVSTART(val) bfin_write16(PIXC_AVSTART, val)
|
||||
#define bfin_read_PIXC_AVEND() bfin_read16(PIXC_AVEND)
|
||||
#define bfin_write_PIXC_AVEND(val) bfin_write16(PIXC_AVEND, val)
|
||||
#define bfin_read_PIXC_ATRANSP() bfin_read16(PIXC_ATRANSP)
|
||||
#define bfin_write_PIXC_ATRANSP(val) bfin_write16(PIXC_ATRANSP, val)
|
||||
#define bfin_read_PIXC_BHSTART() bfin_read16(PIXC_BHSTART)
|
||||
#define bfin_write_PIXC_BHSTART(val) bfin_write16(PIXC_BHSTART, val)
|
||||
#define bfin_read_PIXC_BHEND() bfin_read16(PIXC_BHEND)
|
||||
#define bfin_write_PIXC_BHEND(val) bfin_write16(PIXC_BHEND, val)
|
||||
#define bfin_read_PIXC_BVSTART() bfin_read16(PIXC_BVSTART)
|
||||
#define bfin_write_PIXC_BVSTART(val) bfin_write16(PIXC_BVSTART, val)
|
||||
#define bfin_read_PIXC_BVEND() bfin_read16(PIXC_BVEND)
|
||||
#define bfin_write_PIXC_BVEND(val) bfin_write16(PIXC_BVEND, val)
|
||||
#define bfin_read_PIXC_BTRANSP() bfin_read16(PIXC_BTRANSP)
|
||||
#define bfin_write_PIXC_BTRANSP(val) bfin_write16(PIXC_BTRANSP, val)
|
||||
#define bfin_read_PIXC_INTRSTAT() bfin_read16(PIXC_INTRSTAT)
|
||||
#define bfin_write_PIXC_INTRSTAT(val) bfin_write16(PIXC_INTRSTAT, val)
|
||||
#define bfin_read_PIXC_RYCON() bfin_read32(PIXC_RYCON)
|
||||
#define bfin_write_PIXC_RYCON(val) bfin_write32(PIXC_RYCON, val)
|
||||
#define bfin_read_PIXC_GUCON() bfin_read32(PIXC_GUCON)
|
||||
#define bfin_write_PIXC_GUCON(val) bfin_write32(PIXC_GUCON, val)
|
||||
#define bfin_read_PIXC_BVCON() bfin_read32(PIXC_BVCON)
|
||||
#define bfin_write_PIXC_BVCON(val) bfin_write32(PIXC_BVCON, val)
|
||||
#define bfin_read_PIXC_CCBIAS() bfin_read32(PIXC_CCBIAS)
|
||||
#define bfin_write_PIXC_CCBIAS(val) bfin_write32(PIXC_CCBIAS, val)
|
||||
#define bfin_read_PIXC_TC() bfin_read32(PIXC_TC)
|
||||
#define bfin_write_PIXC_TC(val) bfin_write32(PIXC_TC, val)
|
||||
|
||||
/* Handshake MDMA 0 Registers */
|
||||
|
||||
#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
|
||||
#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
|
||||
#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
|
||||
#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
|
||||
#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
|
||||
#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
|
||||
#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
|
||||
#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
|
||||
#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
|
||||
#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
|
||||
#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
|
||||
#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
|
||||
#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
|
||||
#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
|
||||
|
||||
/* Handshake MDMA 1 Registers */
|
||||
|
||||
#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
|
||||
#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
|
||||
#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
|
||||
#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
|
||||
#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
|
||||
#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
|
||||
#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
|
||||
#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
|
||||
#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
|
||||
#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
|
||||
#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
|
||||
#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
|
||||
#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
|
||||
#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
|
||||
|
||||
#endif /* _CDEF_BF544_H */
|
||||
1610
include/asm-blackfin/mach-bf548/cdefBF548.h
Normal file
1610
include/asm-blackfin/mach-bf548/cdefBF548.h
Normal file
File diff suppressed because it is too large
Load Diff
1896
include/asm-blackfin/mach-bf548/cdefBF549.h
Normal file
1896
include/asm-blackfin/mach-bf548/cdefBF549.h
Normal file
File diff suppressed because it is too large
Load Diff
2722
include/asm-blackfin/mach-bf548/cdefBF54x_base.h
Normal file
2722
include/asm-blackfin/mach-bf548/cdefBF54x_base.h
Normal file
File diff suppressed because it is too large
Load Diff
1206
include/asm-blackfin/mach-bf548/defBF542.h
Normal file
1206
include/asm-blackfin/mach-bf548/defBF542.h
Normal file
File diff suppressed because it is too large
Load Diff
766
include/asm-blackfin/mach-bf548/defBF544.h
Normal file
766
include/asm-blackfin/mach-bf548/defBF544.h
Normal file
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|
||||
/*
|
||||
* File: include/asm-blackfin/mach-bf548/defBF544.h
|
||||
* Based on:
|
||||
* Author:
|
||||
*
|
||||
* Created:
|
||||
* Description:
|
||||
*
|
||||
* Rev:
|
||||
*
|
||||
* Modified:
|
||||
*
|
||||
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING.
|
||||
* If not, write to the Free Software Foundation,
|
||||
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
*/
|
||||
|
||||
#ifndef _DEF_BF544_H
|
||||
#define _DEF_BF544_H
|
||||
|
||||
/* Include all Core registers and bit definitions */
|
||||
#include <asm/mach-common/def_LPBlackfin.h>
|
||||
|
||||
/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF544 */
|
||||
|
||||
/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
|
||||
#include "defBF54x_base.h"
|
||||
|
||||
/* The following are the #defines needed by ADSP-BF544 that are not in the common header */
|
||||
|
||||
/* Timer Registers */
|
||||
|
||||
#define TIMER8_CONFIG 0xffc00600 /* Timer 8 Configuration Register */
|
||||
#define TIMER8_COUNTER 0xffc00604 /* Timer 8 Counter Register */
|
||||
#define TIMER8_PERIOD 0xffc00608 /* Timer 8 Period Register */
|
||||
#define TIMER8_WIDTH 0xffc0060c /* Timer 8 Width Register */
|
||||
#define TIMER9_CONFIG 0xffc00610 /* Timer 9 Configuration Register */
|
||||
#define TIMER9_COUNTER 0xffc00614 /* Timer 9 Counter Register */
|
||||
#define TIMER9_PERIOD 0xffc00618 /* Timer 9 Period Register */
|
||||
#define TIMER9_WIDTH 0xffc0061c /* Timer 9 Width Register */
|
||||
#define TIMER10_CONFIG 0xffc00620 /* Timer 10 Configuration Register */
|
||||
#define TIMER10_COUNTER 0xffc00624 /* Timer 10 Counter Register */
|
||||
#define TIMER10_PERIOD 0xffc00628 /* Timer 10 Period Register */
|
||||
#define TIMER10_WIDTH 0xffc0062c /* Timer 10 Width Register */
|
||||
|
||||
/* Timer Group of 3 Registers */
|
||||
|
||||
#define TIMER_ENABLE1 0xffc00640 /* Timer Group of 3 Enable Register */
|
||||
#define TIMER_DISABLE1 0xffc00644 /* Timer Group of 3 Disable Register */
|
||||
#define TIMER_STATUS1 0xffc00648 /* Timer Group of 3 Status Register */
|
||||
|
||||
/* EPPI0 Registers */
|
||||
|
||||
#define EPPI0_STATUS 0xffc01000 /* EPPI0 Status Register */
|
||||
#define EPPI0_HCOUNT 0xffc01004 /* EPPI0 Horizontal Transfer Count Register */
|
||||
#define EPPI0_HDELAY 0xffc01008 /* EPPI0 Horizontal Delay Count Register */
|
||||
#define EPPI0_VCOUNT 0xffc0100c /* EPPI0 Vertical Transfer Count Register */
|
||||
#define EPPI0_VDELAY 0xffc01010 /* EPPI0 Vertical Delay Count Register */
|
||||
#define EPPI0_FRAME 0xffc01014 /* EPPI0 Lines per Frame Register */
|
||||
#define EPPI0_LINE 0xffc01018 /* EPPI0 Samples per Line Register */
|
||||
#define EPPI0_CLKDIV 0xffc0101c /* EPPI0 Clock Divide Register */
|
||||
#define EPPI0_CONTROL 0xffc01020 /* EPPI0 Control Register */
|
||||
#define EPPI0_FS1W_HBL 0xffc01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
|
||||
#define EPPI0_FS1P_AVPL 0xffc01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
|
||||
#define EPPI0_FS2W_LVB 0xffc0102c /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
|
||||
#define EPPI0_FS2P_LAVF 0xffc01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
|
||||
#define EPPI0_CLIP 0xffc01034 /* EPPI0 Clipping Register */
|
||||
|
||||
/* Two Wire Interface Registers (TWI1) */
|
||||
|
||||
#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */
|
||||
#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */
|
||||
#define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */
|
||||
#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */
|
||||
#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */
|
||||
#define TWI1_MASTER_CTRL 0xffc02214 /* TWI Master Mode Control Register */
|
||||
#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */
|
||||
#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */
|
||||
#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */
|
||||
#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */
|
||||
#define TWI1_FIFO_CTRL 0xffc02228 /* TWI FIFO Control Register */
|
||||
#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */
|
||||
#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */
|
||||
#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */
|
||||
#define TWI1_RCV_DATA8 0xffc02288 /* TWI FIFO Receive Data Single Byte Register */
|
||||
#define TWI1_RCV_DATA16 0xffc0228c /* TWI FIFO Receive Data Double Byte Register */
|
||||
|
||||
/* CAN Controller 1 Config 1 Registers */
|
||||
|
||||
#define CAN1_MC1 0xffc03200 /* CAN Controller 1 Mailbox Configuration Register 1 */
|
||||
#define CAN1_MD1 0xffc03204 /* CAN Controller 1 Mailbox Direction Register 1 */
|
||||
#define CAN1_TRS1 0xffc03208 /* CAN Controller 1 Transmit Request Set Register 1 */
|
||||
#define CAN1_TRR1 0xffc0320c /* CAN Controller 1 Transmit Request Reset Register 1 */
|
||||
#define CAN1_TA1 0xffc03210 /* CAN Controller 1 Transmit Acknowledge Register 1 */
|
||||
#define CAN1_AA1 0xffc03214 /* CAN Controller 1 Abort Acknowledge Register 1 */
|
||||
#define CAN1_RMP1 0xffc03218 /* CAN Controller 1 Receive Message Pending Register 1 */
|
||||
#define CAN1_RML1 0xffc0321c /* CAN Controller 1 Receive Message Lost Register 1 */
|
||||
#define CAN1_MBTIF1 0xffc03220 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
|
||||
#define CAN1_MBRIF1 0xffc03224 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
|
||||
#define CAN1_MBIM1 0xffc03228 /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
|
||||
#define CAN1_RFH1 0xffc0322c /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
|
||||
#define CAN1_OPSS1 0xffc03230 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
|
||||
|
||||
/* CAN Controller 1 Config 2 Registers */
|
||||
|
||||
#define CAN1_MC2 0xffc03240 /* CAN Controller 1 Mailbox Configuration Register 2 */
|
||||
#define CAN1_MD2 0xffc03244 /* CAN Controller 1 Mailbox Direction Register 2 */
|
||||
#define CAN1_TRS2 0xffc03248 /* CAN Controller 1 Transmit Request Set Register 2 */
|
||||
#define CAN1_TRR2 0xffc0324c /* CAN Controller 1 Transmit Request Reset Register 2 */
|
||||
#define CAN1_TA2 0xffc03250 /* CAN Controller 1 Transmit Acknowledge Register 2 */
|
||||
#define CAN1_AA2 0xffc03254 /* CAN Controller 1 Abort Acknowledge Register 2 */
|
||||
#define CAN1_RMP2 0xffc03258 /* CAN Controller 1 Receive Message Pending Register 2 */
|
||||
#define CAN1_RML2 0xffc0325c /* CAN Controller 1 Receive Message Lost Register 2 */
|
||||
#define CAN1_MBTIF2 0xffc03260 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
|
||||
#define CAN1_MBRIF2 0xffc03264 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
|
||||
#define CAN1_MBIM2 0xffc03268 /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
|
||||
#define CAN1_RFH2 0xffc0326c /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
|
||||
#define CAN1_OPSS2 0xffc03270 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
|
||||
|
||||
/* CAN Controller 1 Clock/Interrupt/Counter Registers */
|
||||
|
||||
#define CAN1_CLOCK 0xffc03280 /* CAN Controller 1 Clock Register */
|
||||
#define CAN1_TIMING 0xffc03284 /* CAN Controller 1 Timing Register */
|
||||
#define CAN1_DEBUG 0xffc03288 /* CAN Controller 1 Debug Register */
|
||||
#define CAN1_STATUS 0xffc0328c /* CAN Controller 1 Global Status Register */
|
||||
#define CAN1_CEC 0xffc03290 /* CAN Controller 1 Error Counter Register */
|
||||
#define CAN1_GIS 0xffc03294 /* CAN Controller 1 Global Interrupt Status Register */
|
||||
#define CAN1_GIM 0xffc03298 /* CAN Controller 1 Global Interrupt Mask Register */
|
||||
#define CAN1_GIF 0xffc0329c /* CAN Controller 1 Global Interrupt Flag Register */
|
||||
#define CAN1_CONTROL 0xffc032a0 /* CAN Controller 1 Master Control Register */
|
||||
#define CAN1_INTR 0xffc032a4 /* CAN Controller 1 Interrupt Pending Register */
|
||||
#define CAN1_MBTD 0xffc032ac /* CAN Controller 1 Mailbox Temporary Disable Register */
|
||||
#define CAN1_EWR 0xffc032b0 /* CAN Controller 1 Programmable Warning Level Register */
|
||||
#define CAN1_ESR 0xffc032b4 /* CAN Controller 1 Error Status Register */
|
||||
#define CAN1_UCCNT 0xffc032c4 /* CAN Controller 1 Universal Counter Register */
|
||||
#define CAN1_UCRC 0xffc032c8 /* CAN Controller 1 Universal Counter Force Reload Register */
|
||||
#define CAN1_UCCNF 0xffc032cc /* CAN Controller 1 Universal Counter Configuration Register */
|
||||
|
||||
/* CAN Controller 1 Mailbox Acceptance Registers */
|
||||
|
||||
#define CAN1_AM00L 0xffc03300 /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
|
||||
#define CAN1_AM00H 0xffc03304 /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
|
||||
#define CAN1_AM01L 0xffc03308 /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
|
||||
#define CAN1_AM01H 0xffc0330c /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
|
||||
#define CAN1_AM02L 0xffc03310 /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
|
||||
#define CAN1_AM02H 0xffc03314 /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
|
||||
#define CAN1_AM03L 0xffc03318 /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
|
||||
#define CAN1_AM03H 0xffc0331c /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
|
||||
#define CAN1_AM04L 0xffc03320 /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
|
||||
#define CAN1_AM04H 0xffc03324 /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
|
||||
#define CAN1_AM05L 0xffc03328 /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
|
||||
#define CAN1_AM05H 0xffc0332c /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
|
||||
#define CAN1_AM06L 0xffc03330 /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
|
||||
#define CAN1_AM06H 0xffc03334 /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
|
||||
#define CAN1_AM07L 0xffc03338 /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
|
||||
#define CAN1_AM07H 0xffc0333c /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
|
||||
#define CAN1_AM08L 0xffc03340 /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
|
||||
#define CAN1_AM08H 0xffc03344 /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
|
||||
#define CAN1_AM09L 0xffc03348 /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
|
||||
#define CAN1_AM09H 0xffc0334c /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
|
||||
#define CAN1_AM10L 0xffc03350 /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
|
||||
#define CAN1_AM10H 0xffc03354 /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
|
||||
#define CAN1_AM11L 0xffc03358 /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
|
||||
#define CAN1_AM11H 0xffc0335c /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
|
||||
#define CAN1_AM12L 0xffc03360 /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
|
||||
#define CAN1_AM12H 0xffc03364 /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
|
||||
#define CAN1_AM13L 0xffc03368 /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
|
||||
#define CAN1_AM13H 0xffc0336c /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
|
||||
#define CAN1_AM14L 0xffc03370 /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
|
||||
#define CAN1_AM14H 0xffc03374 /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
|
||||
#define CAN1_AM15L 0xffc03378 /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
|
||||
#define CAN1_AM15H 0xffc0337c /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
|
||||
|
||||
/* CAN Controller 1 Mailbox Acceptance Registers */
|
||||
|
||||
#define CAN1_AM16L 0xffc03380 /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
|
||||
#define CAN1_AM16H 0xffc03384 /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
|
||||
#define CAN1_AM17L 0xffc03388 /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
|
||||
#define CAN1_AM17H 0xffc0338c /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
|
||||
#define CAN1_AM18L 0xffc03390 /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
|
||||
#define CAN1_AM18H 0xffc03394 /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
|
||||
#define CAN1_AM19L 0xffc03398 /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
|
||||
#define CAN1_AM19H 0xffc0339c /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
|
||||
#define CAN1_AM20L 0xffc033a0 /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
|
||||
#define CAN1_AM20H 0xffc033a4 /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
|
||||
#define CAN1_AM21L 0xffc033a8 /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
|
||||
#define CAN1_AM21H 0xffc033ac /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
|
||||
#define CAN1_AM22L 0xffc033b0 /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
|
||||
#define CAN1_AM22H 0xffc033b4 /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
|
||||
#define CAN1_AM23L 0xffc033b8 /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
|
||||
#define CAN1_AM23H 0xffc033bc /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
|
||||
#define CAN1_AM24L 0xffc033c0 /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
|
||||
#define CAN1_AM24H 0xffc033c4 /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
|
||||
#define CAN1_AM25L 0xffc033c8 /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
|
||||
#define CAN1_AM25H 0xffc033cc /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
|
||||
#define CAN1_AM26L 0xffc033d0 /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
|
||||
#define CAN1_AM26H 0xffc033d4 /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
|
||||
#define CAN1_AM27L 0xffc033d8 /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
|
||||
#define CAN1_AM27H 0xffc033dc /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
|
||||
#define CAN1_AM28L 0xffc033e0 /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
|
||||
#define CAN1_AM28H 0xffc033e4 /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
|
||||
#define CAN1_AM29L 0xffc033e8 /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
|
||||
#define CAN1_AM29H 0xffc033ec /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
|
||||
#define CAN1_AM30L 0xffc033f0 /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
|
||||
#define CAN1_AM30H 0xffc033f4 /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
|
||||
#define CAN1_AM31L 0xffc033f8 /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
|
||||
#define CAN1_AM31H 0xffc033fc /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
|
||||
|
||||
/* CAN Controller 1 Mailbox Data Registers */
|
||||
|
||||
#define CAN1_MB00_DATA0 0xffc03400 /* CAN Controller 1 Mailbox 0 Data 0 Register */
|
||||
#define CAN1_MB00_DATA1 0xffc03404 /* CAN Controller 1 Mailbox 0 Data 1 Register */
|
||||
#define CAN1_MB00_DATA2 0xffc03408 /* CAN Controller 1 Mailbox 0 Data 2 Register */
|
||||
#define CAN1_MB00_DATA3 0xffc0340c /* CAN Controller 1 Mailbox 0 Data 3 Register */
|
||||
#define CAN1_MB00_LENGTH 0xffc03410 /* CAN Controller 1 Mailbox 0 Length Register */
|
||||
#define CAN1_MB00_TIMESTAMP 0xffc03414 /* CAN Controller 1 Mailbox 0 Timestamp Register */
|
||||
#define CAN1_MB00_ID0 0xffc03418 /* CAN Controller 1 Mailbox 0 ID0 Register */
|
||||
#define CAN1_MB00_ID1 0xffc0341c /* CAN Controller 1 Mailbox 0 ID1 Register */
|
||||
#define CAN1_MB01_DATA0 0xffc03420 /* CAN Controller 1 Mailbox 1 Data 0 Register */
|
||||
#define CAN1_MB01_DATA1 0xffc03424 /* CAN Controller 1 Mailbox 1 Data 1 Register */
|
||||
#define CAN1_MB01_DATA2 0xffc03428 /* CAN Controller 1 Mailbox 1 Data 2 Register */
|
||||
#define CAN1_MB01_DATA3 0xffc0342c /* CAN Controller 1 Mailbox 1 Data 3 Register */
|
||||
#define CAN1_MB01_LENGTH 0xffc03430 /* CAN Controller 1 Mailbox 1 Length Register */
|
||||
#define CAN1_MB01_TIMESTAMP 0xffc03434 /* CAN Controller 1 Mailbox 1 Timestamp Register */
|
||||
#define CAN1_MB01_ID0 0xffc03438 /* CAN Controller 1 Mailbox 1 ID0 Register */
|
||||
#define CAN1_MB01_ID1 0xffc0343c /* CAN Controller 1 Mailbox 1 ID1 Register */
|
||||
#define CAN1_MB02_DATA0 0xffc03440 /* CAN Controller 1 Mailbox 2 Data 0 Register */
|
||||
#define CAN1_MB02_DATA1 0xffc03444 /* CAN Controller 1 Mailbox 2 Data 1 Register */
|
||||
#define CAN1_MB02_DATA2 0xffc03448 /* CAN Controller 1 Mailbox 2 Data 2 Register */
|
||||
#define CAN1_MB02_DATA3 0xffc0344c /* CAN Controller 1 Mailbox 2 Data 3 Register */
|
||||
#define CAN1_MB02_LENGTH 0xffc03450 /* CAN Controller 1 Mailbox 2 Length Register */
|
||||
#define CAN1_MB02_TIMESTAMP 0xffc03454 /* CAN Controller 1 Mailbox 2 Timestamp Register */
|
||||
#define CAN1_MB02_ID0 0xffc03458 /* CAN Controller 1 Mailbox 2 ID0 Register */
|
||||
#define CAN1_MB02_ID1 0xffc0345c /* CAN Controller 1 Mailbox 2 ID1 Register */
|
||||
#define CAN1_MB03_DATA0 0xffc03460 /* CAN Controller 1 Mailbox 3 Data 0 Register */
|
||||
#define CAN1_MB03_DATA1 0xffc03464 /* CAN Controller 1 Mailbox 3 Data 1 Register */
|
||||
#define CAN1_MB03_DATA2 0xffc03468 /* CAN Controller 1 Mailbox 3 Data 2 Register */
|
||||
#define CAN1_MB03_DATA3 0xffc0346c /* CAN Controller 1 Mailbox 3 Data 3 Register */
|
||||
#define CAN1_MB03_LENGTH 0xffc03470 /* CAN Controller 1 Mailbox 3 Length Register */
|
||||
#define CAN1_MB03_TIMESTAMP 0xffc03474 /* CAN Controller 1 Mailbox 3 Timestamp Register */
|
||||
#define CAN1_MB03_ID0 0xffc03478 /* CAN Controller 1 Mailbox 3 ID0 Register */
|
||||
#define CAN1_MB03_ID1 0xffc0347c /* CAN Controller 1 Mailbox 3 ID1 Register */
|
||||
#define CAN1_MB04_DATA0 0xffc03480 /* CAN Controller 1 Mailbox 4 Data 0 Register */
|
||||
#define CAN1_MB04_DATA1 0xffc03484 /* CAN Controller 1 Mailbox 4 Data 1 Register */
|
||||
#define CAN1_MB04_DATA2 0xffc03488 /* CAN Controller 1 Mailbox 4 Data 2 Register */
|
||||
#define CAN1_MB04_DATA3 0xffc0348c /* CAN Controller 1 Mailbox 4 Data 3 Register */
|
||||
#define CAN1_MB04_LENGTH 0xffc03490 /* CAN Controller 1 Mailbox 4 Length Register */
|
||||
#define CAN1_MB04_TIMESTAMP 0xffc03494 /* CAN Controller 1 Mailbox 4 Timestamp Register */
|
||||
#define CAN1_MB04_ID0 0xffc03498 /* CAN Controller 1 Mailbox 4 ID0 Register */
|
||||
#define CAN1_MB04_ID1 0xffc0349c /* CAN Controller 1 Mailbox 4 ID1 Register */
|
||||
#define CAN1_MB05_DATA0 0xffc034a0 /* CAN Controller 1 Mailbox 5 Data 0 Register */
|
||||
#define CAN1_MB05_DATA1 0xffc034a4 /* CAN Controller 1 Mailbox 5 Data 1 Register */
|
||||
#define CAN1_MB05_DATA2 0xffc034a8 /* CAN Controller 1 Mailbox 5 Data 2 Register */
|
||||
#define CAN1_MB05_DATA3 0xffc034ac /* CAN Controller 1 Mailbox 5 Data 3 Register */
|
||||
#define CAN1_MB05_LENGTH 0xffc034b0 /* CAN Controller 1 Mailbox 5 Length Register */
|
||||
#define CAN1_MB05_TIMESTAMP 0xffc034b4 /* CAN Controller 1 Mailbox 5 Timestamp Register */
|
||||
#define CAN1_MB05_ID0 0xffc034b8 /* CAN Controller 1 Mailbox 5 ID0 Register */
|
||||
#define CAN1_MB05_ID1 0xffc034bc /* CAN Controller 1 Mailbox 5 ID1 Register */
|
||||
#define CAN1_MB06_DATA0 0xffc034c0 /* CAN Controller 1 Mailbox 6 Data 0 Register */
|
||||
#define CAN1_MB06_DATA1 0xffc034c4 /* CAN Controller 1 Mailbox 6 Data 1 Register */
|
||||
#define CAN1_MB06_DATA2 0xffc034c8 /* CAN Controller 1 Mailbox 6 Data 2 Register */
|
||||
#define CAN1_MB06_DATA3 0xffc034cc /* CAN Controller 1 Mailbox 6 Data 3 Register */
|
||||
#define CAN1_MB06_LENGTH 0xffc034d0 /* CAN Controller 1 Mailbox 6 Length Register */
|
||||
#define CAN1_MB06_TIMESTAMP 0xffc034d4 /* CAN Controller 1 Mailbox 6 Timestamp Register */
|
||||
#define CAN1_MB06_ID0 0xffc034d8 /* CAN Controller 1 Mailbox 6 ID0 Register */
|
||||
#define CAN1_MB06_ID1 0xffc034dc /* CAN Controller 1 Mailbox 6 ID1 Register */
|
||||
#define CAN1_MB07_DATA0 0xffc034e0 /* CAN Controller 1 Mailbox 7 Data 0 Register */
|
||||
#define CAN1_MB07_DATA1 0xffc034e4 /* CAN Controller 1 Mailbox 7 Data 1 Register */
|
||||
#define CAN1_MB07_DATA2 0xffc034e8 /* CAN Controller 1 Mailbox 7 Data 2 Register */
|
||||
#define CAN1_MB07_DATA3 0xffc034ec /* CAN Controller 1 Mailbox 7 Data 3 Register */
|
||||
#define CAN1_MB07_LENGTH 0xffc034f0 /* CAN Controller 1 Mailbox 7 Length Register */
|
||||
#define CAN1_MB07_TIMESTAMP 0xffc034f4 /* CAN Controller 1 Mailbox 7 Timestamp Register */
|
||||
#define CAN1_MB07_ID0 0xffc034f8 /* CAN Controller 1 Mailbox 7 ID0 Register */
|
||||
#define CAN1_MB07_ID1 0xffc034fc /* CAN Controller 1 Mailbox 7 ID1 Register */
|
||||
#define CAN1_MB08_DATA0 0xffc03500 /* CAN Controller 1 Mailbox 8 Data 0 Register */
|
||||
#define CAN1_MB08_DATA1 0xffc03504 /* CAN Controller 1 Mailbox 8 Data 1 Register */
|
||||
#define CAN1_MB08_DATA2 0xffc03508 /* CAN Controller 1 Mailbox 8 Data 2 Register */
|
||||
#define CAN1_MB08_DATA3 0xffc0350c /* CAN Controller 1 Mailbox 8 Data 3 Register */
|
||||
#define CAN1_MB08_LENGTH 0xffc03510 /* CAN Controller 1 Mailbox 8 Length Register */
|
||||
#define CAN1_MB08_TIMESTAMP 0xffc03514 /* CAN Controller 1 Mailbox 8 Timestamp Register */
|
||||
#define CAN1_MB08_ID0 0xffc03518 /* CAN Controller 1 Mailbox 8 ID0 Register */
|
||||
#define CAN1_MB08_ID1 0xffc0351c /* CAN Controller 1 Mailbox 8 ID1 Register */
|
||||
#define CAN1_MB09_DATA0 0xffc03520 /* CAN Controller 1 Mailbox 9 Data 0 Register */
|
||||
#define CAN1_MB09_DATA1 0xffc03524 /* CAN Controller 1 Mailbox 9 Data 1 Register */
|
||||
#define CAN1_MB09_DATA2 0xffc03528 /* CAN Controller 1 Mailbox 9 Data 2 Register */
|
||||
#define CAN1_MB09_DATA3 0xffc0352c /* CAN Controller 1 Mailbox 9 Data 3 Register */
|
||||
#define CAN1_MB09_LENGTH 0xffc03530 /* CAN Controller 1 Mailbox 9 Length Register */
|
||||
#define CAN1_MB09_TIMESTAMP 0xffc03534 /* CAN Controller 1 Mailbox 9 Timestamp Register */
|
||||
#define CAN1_MB09_ID0 0xffc03538 /* CAN Controller 1 Mailbox 9 ID0 Register */
|
||||
#define CAN1_MB09_ID1 0xffc0353c /* CAN Controller 1 Mailbox 9 ID1 Register */
|
||||
#define CAN1_MB10_DATA0 0xffc03540 /* CAN Controller 1 Mailbox 10 Data 0 Register */
|
||||
#define CAN1_MB10_DATA1 0xffc03544 /* CAN Controller 1 Mailbox 10 Data 1 Register */
|
||||
#define CAN1_MB10_DATA2 0xffc03548 /* CAN Controller 1 Mailbox 10 Data 2 Register */
|
||||
#define CAN1_MB10_DATA3 0xffc0354c /* CAN Controller 1 Mailbox 10 Data 3 Register */
|
||||
#define CAN1_MB10_LENGTH 0xffc03550 /* CAN Controller 1 Mailbox 10 Length Register */
|
||||
#define CAN1_MB10_TIMESTAMP 0xffc03554 /* CAN Controller 1 Mailbox 10 Timestamp Register */
|
||||
#define CAN1_MB10_ID0 0xffc03558 /* CAN Controller 1 Mailbox 10 ID0 Register */
|
||||
#define CAN1_MB10_ID1 0xffc0355c /* CAN Controller 1 Mailbox 10 ID1 Register */
|
||||
#define CAN1_MB11_DATA0 0xffc03560 /* CAN Controller 1 Mailbox 11 Data 0 Register */
|
||||
#define CAN1_MB11_DATA1 0xffc03564 /* CAN Controller 1 Mailbox 11 Data 1 Register */
|
||||
#define CAN1_MB11_DATA2 0xffc03568 /* CAN Controller 1 Mailbox 11 Data 2 Register */
|
||||
#define CAN1_MB11_DATA3 0xffc0356c /* CAN Controller 1 Mailbox 11 Data 3 Register */
|
||||
#define CAN1_MB11_LENGTH 0xffc03570 /* CAN Controller 1 Mailbox 11 Length Register */
|
||||
#define CAN1_MB11_TIMESTAMP 0xffc03574 /* CAN Controller 1 Mailbox 11 Timestamp Register */
|
||||
#define CAN1_MB11_ID0 0xffc03578 /* CAN Controller 1 Mailbox 11 ID0 Register */
|
||||
#define CAN1_MB11_ID1 0xffc0357c /* CAN Controller 1 Mailbox 11 ID1 Register */
|
||||
#define CAN1_MB12_DATA0 0xffc03580 /* CAN Controller 1 Mailbox 12 Data 0 Register */
|
||||
#define CAN1_MB12_DATA1 0xffc03584 /* CAN Controller 1 Mailbox 12 Data 1 Register */
|
||||
#define CAN1_MB12_DATA2 0xffc03588 /* CAN Controller 1 Mailbox 12 Data 2 Register */
|
||||
#define CAN1_MB12_DATA3 0xffc0358c /* CAN Controller 1 Mailbox 12 Data 3 Register */
|
||||
#define CAN1_MB12_LENGTH 0xffc03590 /* CAN Controller 1 Mailbox 12 Length Register */
|
||||
#define CAN1_MB12_TIMESTAMP 0xffc03594 /* CAN Controller 1 Mailbox 12 Timestamp Register */
|
||||
#define CAN1_MB12_ID0 0xffc03598 /* CAN Controller 1 Mailbox 12 ID0 Register */
|
||||
#define CAN1_MB12_ID1 0xffc0359c /* CAN Controller 1 Mailbox 12 ID1 Register */
|
||||
#define CAN1_MB13_DATA0 0xffc035a0 /* CAN Controller 1 Mailbox 13 Data 0 Register */
|
||||
#define CAN1_MB13_DATA1 0xffc035a4 /* CAN Controller 1 Mailbox 13 Data 1 Register */
|
||||
#define CAN1_MB13_DATA2 0xffc035a8 /* CAN Controller 1 Mailbox 13 Data 2 Register */
|
||||
#define CAN1_MB13_DATA3 0xffc035ac /* CAN Controller 1 Mailbox 13 Data 3 Register */
|
||||
#define CAN1_MB13_LENGTH 0xffc035b0 /* CAN Controller 1 Mailbox 13 Length Register */
|
||||
#define CAN1_MB13_TIMESTAMP 0xffc035b4 /* CAN Controller 1 Mailbox 13 Timestamp Register */
|
||||
#define CAN1_MB13_ID0 0xffc035b8 /* CAN Controller 1 Mailbox 13 ID0 Register */
|
||||
#define CAN1_MB13_ID1 0xffc035bc /* CAN Controller 1 Mailbox 13 ID1 Register */
|
||||
#define CAN1_MB14_DATA0 0xffc035c0 /* CAN Controller 1 Mailbox 14 Data 0 Register */
|
||||
#define CAN1_MB14_DATA1 0xffc035c4 /* CAN Controller 1 Mailbox 14 Data 1 Register */
|
||||
#define CAN1_MB14_DATA2 0xffc035c8 /* CAN Controller 1 Mailbox 14 Data 2 Register */
|
||||
#define CAN1_MB14_DATA3 0xffc035cc /* CAN Controller 1 Mailbox 14 Data 3 Register */
|
||||
#define CAN1_MB14_LENGTH 0xffc035d0 /* CAN Controller 1 Mailbox 14 Length Register */
|
||||
#define CAN1_MB14_TIMESTAMP 0xffc035d4 /* CAN Controller 1 Mailbox 14 Timestamp Register */
|
||||
#define CAN1_MB14_ID0 0xffc035d8 /* CAN Controller 1 Mailbox 14 ID0 Register */
|
||||
#define CAN1_MB14_ID1 0xffc035dc /* CAN Controller 1 Mailbox 14 ID1 Register */
|
||||
#define CAN1_MB15_DATA0 0xffc035e0 /* CAN Controller 1 Mailbox 15 Data 0 Register */
|
||||
#define CAN1_MB15_DATA1 0xffc035e4 /* CAN Controller 1 Mailbox 15 Data 1 Register */
|
||||
#define CAN1_MB15_DATA2 0xffc035e8 /* CAN Controller 1 Mailbox 15 Data 2 Register */
|
||||
#define CAN1_MB15_DATA3 0xffc035ec /* CAN Controller 1 Mailbox 15 Data 3 Register */
|
||||
#define CAN1_MB15_LENGTH 0xffc035f0 /* CAN Controller 1 Mailbox 15 Length Register */
|
||||
#define CAN1_MB15_TIMESTAMP 0xffc035f4 /* CAN Controller 1 Mailbox 15 Timestamp Register */
|
||||
#define CAN1_MB15_ID0 0xffc035f8 /* CAN Controller 1 Mailbox 15 ID0 Register */
|
||||
#define CAN1_MB15_ID1 0xffc035fc /* CAN Controller 1 Mailbox 15 ID1 Register */
|
||||
|
||||
/* CAN Controller 1 Mailbox Data Registers */
|
||||
|
||||
#define CAN1_MB16_DATA0 0xffc03600 /* CAN Controller 1 Mailbox 16 Data 0 Register */
|
||||
#define CAN1_MB16_DATA1 0xffc03604 /* CAN Controller 1 Mailbox 16 Data 1 Register */
|
||||
#define CAN1_MB16_DATA2 0xffc03608 /* CAN Controller 1 Mailbox 16 Data 2 Register */
|
||||
#define CAN1_MB16_DATA3 0xffc0360c /* CAN Controller 1 Mailbox 16 Data 3 Register */
|
||||
#define CAN1_MB16_LENGTH 0xffc03610 /* CAN Controller 1 Mailbox 16 Length Register */
|
||||
#define CAN1_MB16_TIMESTAMP 0xffc03614 /* CAN Controller 1 Mailbox 16 Timestamp Register */
|
||||
#define CAN1_MB16_ID0 0xffc03618 /* CAN Controller 1 Mailbox 16 ID0 Register */
|
||||
#define CAN1_MB16_ID1 0xffc0361c /* CAN Controller 1 Mailbox 16 ID1 Register */
|
||||
#define CAN1_MB17_DATA0 0xffc03620 /* CAN Controller 1 Mailbox 17 Data 0 Register */
|
||||
#define CAN1_MB17_DATA1 0xffc03624 /* CAN Controller 1 Mailbox 17 Data 1 Register */
|
||||
#define CAN1_MB17_DATA2 0xffc03628 /* CAN Controller 1 Mailbox 17 Data 2 Register */
|
||||
#define CAN1_MB17_DATA3 0xffc0362c /* CAN Controller 1 Mailbox 17 Data 3 Register */
|
||||
#define CAN1_MB17_LENGTH 0xffc03630 /* CAN Controller 1 Mailbox 17 Length Register */
|
||||
#define CAN1_MB17_TIMESTAMP 0xffc03634 /* CAN Controller 1 Mailbox 17 Timestamp Register */
|
||||
#define CAN1_MB17_ID0 0xffc03638 /* CAN Controller 1 Mailbox 17 ID0 Register */
|
||||
#define CAN1_MB17_ID1 0xffc0363c /* CAN Controller 1 Mailbox 17 ID1 Register */
|
||||
#define CAN1_MB18_DATA0 0xffc03640 /* CAN Controller 1 Mailbox 18 Data 0 Register */
|
||||
#define CAN1_MB18_DATA1 0xffc03644 /* CAN Controller 1 Mailbox 18 Data 1 Register */
|
||||
#define CAN1_MB18_DATA2 0xffc03648 /* CAN Controller 1 Mailbox 18 Data 2 Register */
|
||||
#define CAN1_MB18_DATA3 0xffc0364c /* CAN Controller 1 Mailbox 18 Data 3 Register */
|
||||
#define CAN1_MB18_LENGTH 0xffc03650 /* CAN Controller 1 Mailbox 18 Length Register */
|
||||
#define CAN1_MB18_TIMESTAMP 0xffc03654 /* CAN Controller 1 Mailbox 18 Timestamp Register */
|
||||
#define CAN1_MB18_ID0 0xffc03658 /* CAN Controller 1 Mailbox 18 ID0 Register */
|
||||
#define CAN1_MB18_ID1 0xffc0365c /* CAN Controller 1 Mailbox 18 ID1 Register */
|
||||
#define CAN1_MB19_DATA0 0xffc03660 /* CAN Controller 1 Mailbox 19 Data 0 Register */
|
||||
#define CAN1_MB19_DATA1 0xffc03664 /* CAN Controller 1 Mailbox 19 Data 1 Register */
|
||||
#define CAN1_MB19_DATA2 0xffc03668 /* CAN Controller 1 Mailbox 19 Data 2 Register */
|
||||
#define CAN1_MB19_DATA3 0xffc0366c /* CAN Controller 1 Mailbox 19 Data 3 Register */
|
||||
#define CAN1_MB19_LENGTH 0xffc03670 /* CAN Controller 1 Mailbox 19 Length Register */
|
||||
#define CAN1_MB19_TIMESTAMP 0xffc03674 /* CAN Controller 1 Mailbox 19 Timestamp Register */
|
||||
#define CAN1_MB19_ID0 0xffc03678 /* CAN Controller 1 Mailbox 19 ID0 Register */
|
||||
#define CAN1_MB19_ID1 0xffc0367c /* CAN Controller 1 Mailbox 19 ID1 Register */
|
||||
#define CAN1_MB20_DATA0 0xffc03680 /* CAN Controller 1 Mailbox 20 Data 0 Register */
|
||||
#define CAN1_MB20_DATA1 0xffc03684 /* CAN Controller 1 Mailbox 20 Data 1 Register */
|
||||
#define CAN1_MB20_DATA2 0xffc03688 /* CAN Controller 1 Mailbox 20 Data 2 Register */
|
||||
#define CAN1_MB20_DATA3 0xffc0368c /* CAN Controller 1 Mailbox 20 Data 3 Register */
|
||||
#define CAN1_MB20_LENGTH 0xffc03690 /* CAN Controller 1 Mailbox 20 Length Register */
|
||||
#define CAN1_MB20_TIMESTAMP 0xffc03694 /* CAN Controller 1 Mailbox 20 Timestamp Register */
|
||||
#define CAN1_MB20_ID0 0xffc03698 /* CAN Controller 1 Mailbox 20 ID0 Register */
|
||||
#define CAN1_MB20_ID1 0xffc0369c /* CAN Controller 1 Mailbox 20 ID1 Register */
|
||||
#define CAN1_MB21_DATA0 0xffc036a0 /* CAN Controller 1 Mailbox 21 Data 0 Register */
|
||||
#define CAN1_MB21_DATA1 0xffc036a4 /* CAN Controller 1 Mailbox 21 Data 1 Register */
|
||||
#define CAN1_MB21_DATA2 0xffc036a8 /* CAN Controller 1 Mailbox 21 Data 2 Register */
|
||||
#define CAN1_MB21_DATA3 0xffc036ac /* CAN Controller 1 Mailbox 21 Data 3 Register */
|
||||
#define CAN1_MB21_LENGTH 0xffc036b0 /* CAN Controller 1 Mailbox 21 Length Register */
|
||||
#define CAN1_MB21_TIMESTAMP 0xffc036b4 /* CAN Controller 1 Mailbox 21 Timestamp Register */
|
||||
#define CAN1_MB21_ID0 0xffc036b8 /* CAN Controller 1 Mailbox 21 ID0 Register */
|
||||
#define CAN1_MB21_ID1 0xffc036bc /* CAN Controller 1 Mailbox 21 ID1 Register */
|
||||
#define CAN1_MB22_DATA0 0xffc036c0 /* CAN Controller 1 Mailbox 22 Data 0 Register */
|
||||
#define CAN1_MB22_DATA1 0xffc036c4 /* CAN Controller 1 Mailbox 22 Data 1 Register */
|
||||
#define CAN1_MB22_DATA2 0xffc036c8 /* CAN Controller 1 Mailbox 22 Data 2 Register */
|
||||
#define CAN1_MB22_DATA3 0xffc036cc /* CAN Controller 1 Mailbox 22 Data 3 Register */
|
||||
#define CAN1_MB22_LENGTH 0xffc036d0 /* CAN Controller 1 Mailbox 22 Length Register */
|
||||
#define CAN1_MB22_TIMESTAMP 0xffc036d4 /* CAN Controller 1 Mailbox 22 Timestamp Register */
|
||||
#define CAN1_MB22_ID0 0xffc036d8 /* CAN Controller 1 Mailbox 22 ID0 Register */
|
||||
#define CAN1_MB22_ID1 0xffc036dc /* CAN Controller 1 Mailbox 22 ID1 Register */
|
||||
#define CAN1_MB23_DATA0 0xffc036e0 /* CAN Controller 1 Mailbox 23 Data 0 Register */
|
||||
#define CAN1_MB23_DATA1 0xffc036e4 /* CAN Controller 1 Mailbox 23 Data 1 Register */
|
||||
#define CAN1_MB23_DATA2 0xffc036e8 /* CAN Controller 1 Mailbox 23 Data 2 Register */
|
||||
#define CAN1_MB23_DATA3 0xffc036ec /* CAN Controller 1 Mailbox 23 Data 3 Register */
|
||||
#define CAN1_MB23_LENGTH 0xffc036f0 /* CAN Controller 1 Mailbox 23 Length Register */
|
||||
#define CAN1_MB23_TIMESTAMP 0xffc036f4 /* CAN Controller 1 Mailbox 23 Timestamp Register */
|
||||
#define CAN1_MB23_ID0 0xffc036f8 /* CAN Controller 1 Mailbox 23 ID0 Register */
|
||||
#define CAN1_MB23_ID1 0xffc036fc /* CAN Controller 1 Mailbox 23 ID1 Register */
|
||||
#define CAN1_MB24_DATA0 0xffc03700 /* CAN Controller 1 Mailbox 24 Data 0 Register */
|
||||
#define CAN1_MB24_DATA1 0xffc03704 /* CAN Controller 1 Mailbox 24 Data 1 Register */
|
||||
#define CAN1_MB24_DATA2 0xffc03708 /* CAN Controller 1 Mailbox 24 Data 2 Register */
|
||||
#define CAN1_MB24_DATA3 0xffc0370c /* CAN Controller 1 Mailbox 24 Data 3 Register */
|
||||
#define CAN1_MB24_LENGTH 0xffc03710 /* CAN Controller 1 Mailbox 24 Length Register */
|
||||
#define CAN1_MB24_TIMESTAMP 0xffc03714 /* CAN Controller 1 Mailbox 24 Timestamp Register */
|
||||
#define CAN1_MB24_ID0 0xffc03718 /* CAN Controller 1 Mailbox 24 ID0 Register */
|
||||
#define CAN1_MB24_ID1 0xffc0371c /* CAN Controller 1 Mailbox 24 ID1 Register */
|
||||
#define CAN1_MB25_DATA0 0xffc03720 /* CAN Controller 1 Mailbox 25 Data 0 Register */
|
||||
#define CAN1_MB25_DATA1 0xffc03724 /* CAN Controller 1 Mailbox 25 Data 1 Register */
|
||||
#define CAN1_MB25_DATA2 0xffc03728 /* CAN Controller 1 Mailbox 25 Data 2 Register */
|
||||
#define CAN1_MB25_DATA3 0xffc0372c /* CAN Controller 1 Mailbox 25 Data 3 Register */
|
||||
#define CAN1_MB25_LENGTH 0xffc03730 /* CAN Controller 1 Mailbox 25 Length Register */
|
||||
#define CAN1_MB25_TIMESTAMP 0xffc03734 /* CAN Controller 1 Mailbox 25 Timestamp Register */
|
||||
#define CAN1_MB25_ID0 0xffc03738 /* CAN Controller 1 Mailbox 25 ID0 Register */
|
||||
#define CAN1_MB25_ID1 0xffc0373c /* CAN Controller 1 Mailbox 25 ID1 Register */
|
||||
#define CAN1_MB26_DATA0 0xffc03740 /* CAN Controller 1 Mailbox 26 Data 0 Register */
|
||||
#define CAN1_MB26_DATA1 0xffc03744 /* CAN Controller 1 Mailbox 26 Data 1 Register */
|
||||
#define CAN1_MB26_DATA2 0xffc03748 /* CAN Controller 1 Mailbox 26 Data 2 Register */
|
||||
#define CAN1_MB26_DATA3 0xffc0374c /* CAN Controller 1 Mailbox 26 Data 3 Register */
|
||||
#define CAN1_MB26_LENGTH 0xffc03750 /* CAN Controller 1 Mailbox 26 Length Register */
|
||||
#define CAN1_MB26_TIMESTAMP 0xffc03754 /* CAN Controller 1 Mailbox 26 Timestamp Register */
|
||||
#define CAN1_MB26_ID0 0xffc03758 /* CAN Controller 1 Mailbox 26 ID0 Register */
|
||||
#define CAN1_MB26_ID1 0xffc0375c /* CAN Controller 1 Mailbox 26 ID1 Register */
|
||||
#define CAN1_MB27_DATA0 0xffc03760 /* CAN Controller 1 Mailbox 27 Data 0 Register */
|
||||
#define CAN1_MB27_DATA1 0xffc03764 /* CAN Controller 1 Mailbox 27 Data 1 Register */
|
||||
#define CAN1_MB27_DATA2 0xffc03768 /* CAN Controller 1 Mailbox 27 Data 2 Register */
|
||||
#define CAN1_MB27_DATA3 0xffc0376c /* CAN Controller 1 Mailbox 27 Data 3 Register */
|
||||
#define CAN1_MB27_LENGTH 0xffc03770 /* CAN Controller 1 Mailbox 27 Length Register */
|
||||
#define CAN1_MB27_TIMESTAMP 0xffc03774 /* CAN Controller 1 Mailbox 27 Timestamp Register */
|
||||
#define CAN1_MB27_ID0 0xffc03778 /* CAN Controller 1 Mailbox 27 ID0 Register */
|
||||
#define CAN1_MB27_ID1 0xffc0377c /* CAN Controller 1 Mailbox 27 ID1 Register */
|
||||
#define CAN1_MB28_DATA0 0xffc03780 /* CAN Controller 1 Mailbox 28 Data 0 Register */
|
||||
#define CAN1_MB28_DATA1 0xffc03784 /* CAN Controller 1 Mailbox 28 Data 1 Register */
|
||||
#define CAN1_MB28_DATA2 0xffc03788 /* CAN Controller 1 Mailbox 28 Data 2 Register */
|
||||
#define CAN1_MB28_DATA3 0xffc0378c /* CAN Controller 1 Mailbox 28 Data 3 Register */
|
||||
#define CAN1_MB28_LENGTH 0xffc03790 /* CAN Controller 1 Mailbox 28 Length Register */
|
||||
#define CAN1_MB28_TIMESTAMP 0xffc03794 /* CAN Controller 1 Mailbox 28 Timestamp Register */
|
||||
#define CAN1_MB28_ID0 0xffc03798 /* CAN Controller 1 Mailbox 28 ID0 Register */
|
||||
#define CAN1_MB28_ID1 0xffc0379c /* CAN Controller 1 Mailbox 28 ID1 Register */
|
||||
#define CAN1_MB29_DATA0 0xffc037a0 /* CAN Controller 1 Mailbox 29 Data 0 Register */
|
||||
#define CAN1_MB29_DATA1 0xffc037a4 /* CAN Controller 1 Mailbox 29 Data 1 Register */
|
||||
#define CAN1_MB29_DATA2 0xffc037a8 /* CAN Controller 1 Mailbox 29 Data 2 Register */
|
||||
#define CAN1_MB29_DATA3 0xffc037ac /* CAN Controller 1 Mailbox 29 Data 3 Register */
|
||||
#define CAN1_MB29_LENGTH 0xffc037b0 /* CAN Controller 1 Mailbox 29 Length Register */
|
||||
#define CAN1_MB29_TIMESTAMP 0xffc037b4 /* CAN Controller 1 Mailbox 29 Timestamp Register */
|
||||
#define CAN1_MB29_ID0 0xffc037b8 /* CAN Controller 1 Mailbox 29 ID0 Register */
|
||||
#define CAN1_MB29_ID1 0xffc037bc /* CAN Controller 1 Mailbox 29 ID1 Register */
|
||||
#define CAN1_MB30_DATA0 0xffc037c0 /* CAN Controller 1 Mailbox 30 Data 0 Register */
|
||||
#define CAN1_MB30_DATA1 0xffc037c4 /* CAN Controller 1 Mailbox 30 Data 1 Register */
|
||||
#define CAN1_MB30_DATA2 0xffc037c8 /* CAN Controller 1 Mailbox 30 Data 2 Register */
|
||||
#define CAN1_MB30_DATA3 0xffc037cc /* CAN Controller 1 Mailbox 30 Data 3 Register */
|
||||
#define CAN1_MB30_LENGTH 0xffc037d0 /* CAN Controller 1 Mailbox 30 Length Register */
|
||||
#define CAN1_MB30_TIMESTAMP 0xffc037d4 /* CAN Controller 1 Mailbox 30 Timestamp Register */
|
||||
#define CAN1_MB30_ID0 0xffc037d8 /* CAN Controller 1 Mailbox 30 ID0 Register */
|
||||
#define CAN1_MB30_ID1 0xffc037dc /* CAN Controller 1 Mailbox 30 ID1 Register */
|
||||
#define CAN1_MB31_DATA0 0xffc037e0 /* CAN Controller 1 Mailbox 31 Data 0 Register */
|
||||
#define CAN1_MB31_DATA1 0xffc037e4 /* CAN Controller 1 Mailbox 31 Data 1 Register */
|
||||
#define CAN1_MB31_DATA2 0xffc037e8 /* CAN Controller 1 Mailbox 31 Data 2 Register */
|
||||
#define CAN1_MB31_DATA3 0xffc037ec /* CAN Controller 1 Mailbox 31 Data 3 Register */
|
||||
#define CAN1_MB31_LENGTH 0xffc037f0 /* CAN Controller 1 Mailbox 31 Length Register */
|
||||
#define CAN1_MB31_TIMESTAMP 0xffc037f4 /* CAN Controller 1 Mailbox 31 Timestamp Register */
|
||||
#define CAN1_MB31_ID0 0xffc037f8 /* CAN Controller 1 Mailbox 31 ID0 Register */
|
||||
#define CAN1_MB31_ID1 0xffc037fc /* CAN Controller 1 Mailbox 31 ID1 Register */
|
||||
|
||||
/* HOST Port Registers */
|
||||
|
||||
#define HOST_CONTROL 0xffc03a00 /* HOST Control Register */
|
||||
#define HOST_STATUS 0xffc03a04 /* HOST Status Register */
|
||||
#define HOST_TIMEOUT 0xffc03a08 /* HOST Acknowledge Mode Timeout Register */
|
||||
|
||||
/* Pixel Compositor (PIXC) Registers */
|
||||
|
||||
#define PIXC_CTL 0xffc04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
|
||||
#define PIXC_PPL 0xffc04404 /* Holds the number of pixels per line of the display */
|
||||
#define PIXC_LPF 0xffc04408 /* Holds the number of lines per frame of the display */
|
||||
#define PIXC_AHSTART 0xffc0440c /* Contains horizontal start pixel information of the overlay data (set A) */
|
||||
#define PIXC_AHEND 0xffc04410 /* Contains horizontal end pixel information of the overlay data (set A) */
|
||||
#define PIXC_AVSTART 0xffc04414 /* Contains vertical start pixel information of the overlay data (set A) */
|
||||
#define PIXC_AVEND 0xffc04418 /* Contains vertical end pixel information of the overlay data (set A) */
|
||||
#define PIXC_ATRANSP 0xffc0441c /* Contains the transparency ratio (set A) */
|
||||
#define PIXC_BHSTART 0xffc04420 /* Contains horizontal start pixel information of the overlay data (set B) */
|
||||
#define PIXC_BHEND 0xffc04424 /* Contains horizontal end pixel information of the overlay data (set B) */
|
||||
#define PIXC_BVSTART 0xffc04428 /* Contains vertical start pixel information of the overlay data (set B) */
|
||||
#define PIXC_BVEND 0xffc0442c /* Contains vertical end pixel information of the overlay data (set B) */
|
||||
#define PIXC_BTRANSP 0xffc04430 /* Contains the transparency ratio (set B) */
|
||||
#define PIXC_INTRSTAT 0xffc0443c /* Overlay interrupt configuration/status */
|
||||
#define PIXC_RYCON 0xffc04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
|
||||
#define PIXC_GUCON 0xffc04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */
|
||||
#define PIXC_BVCON 0xffc04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */
|
||||
#define PIXC_CCBIAS 0xffc0444c /* Bias values for the color space conversion matrix */
|
||||
#define PIXC_TC 0xffc04450 /* Holds the transparent color value */
|
||||
|
||||
/* Handshake MDMA 0 Registers */
|
||||
|
||||
#define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */
|
||||
#define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */
|
||||
#define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */
|
||||
#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
|
||||
#define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
|
||||
#define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */
|
||||
#define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */
|
||||
|
||||
/* Handshake MDMA 1 Registers */
|
||||
|
||||
#define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */
|
||||
#define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */
|
||||
#define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */
|
||||
#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
|
||||
#define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
|
||||
#define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */
|
||||
#define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */
|
||||
|
||||
|
||||
/* ********************************************************** */
|
||||
/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
|
||||
/* and MULTI BIT READ MACROS */
|
||||
/* ********************************************************** */
|
||||
|
||||
/* Bit masks for PIXC_CTL */
|
||||
|
||||
#define PIXC_EN 0x1 /* Pixel Compositor Enable */
|
||||
#define nPIXC_EN 0x0
|
||||
#define OVR_A_EN 0x2 /* Overlay A Enable */
|
||||
#define nOVR_A_EN 0x0
|
||||
#define OVR_B_EN 0x4 /* Overlay B Enable */
|
||||
#define nOVR_B_EN 0x0
|
||||
#define IMG_FORM 0x8 /* Image Data Format */
|
||||
#define nIMG_FORM 0x0
|
||||
#define OVR_FORM 0x10 /* Overlay Data Format */
|
||||
#define nOVR_FORM 0x0
|
||||
#define OUT_FORM 0x20 /* Output Data Format */
|
||||
#define nOUT_FORM 0x0
|
||||
#define UDS_MOD 0x40 /* Resampling Mode */
|
||||
#define nUDS_MOD 0x0
|
||||
#define TC_EN 0x80 /* Transparent Color Enable */
|
||||
#define nTC_EN 0x0
|
||||
#define IMG_STAT 0x300 /* Image FIFO Status */
|
||||
#define OVR_STAT 0xc00 /* Overlay FIFO Status */
|
||||
#define WM_LVL 0x3000 /* FIFO Watermark Level */
|
||||
|
||||
/* Bit masks for PIXC_AHSTART */
|
||||
|
||||
#define A_HSTART 0xfff /* Horizontal Start Coordinates */
|
||||
|
||||
/* Bit masks for PIXC_AHEND */
|
||||
|
||||
#define A_HEND 0xfff /* Horizontal End Coordinates */
|
||||
|
||||
/* Bit masks for PIXC_AVSTART */
|
||||
|
||||
#define A_VSTART 0x3ff /* Vertical Start Coordinates */
|
||||
|
||||
/* Bit masks for PIXC_AVEND */
|
||||
|
||||
#define A_VEND 0x3ff /* Vertical End Coordinates */
|
||||
|
||||
/* Bit masks for PIXC_ATRANSP */
|
||||
|
||||
#define A_TRANSP 0xf /* Transparency Value */
|
||||
|
||||
/* Bit masks for PIXC_BHSTART */
|
||||
|
||||
#define B_HSTART 0xfff /* Horizontal Start Coordinates */
|
||||
|
||||
/* Bit masks for PIXC_BHEND */
|
||||
|
||||
#define B_HEND 0xfff /* Horizontal End Coordinates */
|
||||
|
||||
/* Bit masks for PIXC_BVSTART */
|
||||
|
||||
#define B_VSTART 0x3ff /* Vertical Start Coordinates */
|
||||
|
||||
/* Bit masks for PIXC_BVEND */
|
||||
|
||||
#define B_VEND 0x3ff /* Vertical End Coordinates */
|
||||
|
||||
/* Bit masks for PIXC_BTRANSP */
|
||||
|
||||
#define B_TRANSP 0xf /* Transparency Value */
|
||||
|
||||
/* Bit masks for PIXC_INTRSTAT */
|
||||
|
||||
#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */
|
||||
#define nOVR_INT_EN 0x0
|
||||
#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */
|
||||
#define nFRM_INT_EN 0x0
|
||||
#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */
|
||||
#define nOVR_INT_STAT 0x0
|
||||
#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */
|
||||
#define nFRM_INT_STAT 0x0
|
||||
|
||||
/* Bit masks for PIXC_RYCON */
|
||||
|
||||
#define A11 0x3ff /* A11 in the Coefficient Matrix */
|
||||
#define A12 0xffc00 /* A12 in the Coefficient Matrix */
|
||||
#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */
|
||||
#define RY_MULT4 0x40000000 /* Multiply Row by 4 */
|
||||
#define nRY_MULT4 0x0
|
||||
|
||||
/* Bit masks for PIXC_GUCON */
|
||||
|
||||
#define A21 0x3ff /* A21 in the Coefficient Matrix */
|
||||
#define A22 0xffc00 /* A22 in the Coefficient Matrix */
|
||||
#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */
|
||||
#define GU_MULT4 0x40000000 /* Multiply Row by 4 */
|
||||
#define nGU_MULT4 0x0
|
||||
|
||||
/* Bit masks for PIXC_BVCON */
|
||||
|
||||
#define A31 0x3ff /* A31 in the Coefficient Matrix */
|
||||
#define A32 0xffc00 /* A32 in the Coefficient Matrix */
|
||||
#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */
|
||||
#define BV_MULT4 0x40000000 /* Multiply Row by 4 */
|
||||
#define nBV_MULT4 0x0
|
||||
|
||||
/* Bit masks for PIXC_CCBIAS */
|
||||
|
||||
#define A14 0x3ff /* A14 in the Bias Vector */
|
||||
#define A24 0xffc00 /* A24 in the Bias Vector */
|
||||
#define A34 0x3ff00000 /* A34 in the Bias Vector */
|
||||
|
||||
/* Bit masks for PIXC_TC */
|
||||
|
||||
#define RY_TRANS 0xff /* Transparent Color - R/Y Component */
|
||||
#define GU_TRANS 0xff00 /* Transparent Color - G/U Component */
|
||||
#define BV_TRANS 0xff0000 /* Transparent Color - B/V Component */
|
||||
|
||||
/* Bit masks for HOST_CONTROL */
|
||||
|
||||
#define HOST_EN 0x1 /* Host Enable */
|
||||
#define nHOST_EN 0x0
|
||||
#define HOST_END 0x2 /* Host Endianess */
|
||||
#define nHOST_END 0x0
|
||||
#define DATA_SIZE 0x4 /* Data Size */
|
||||
#define nDATA_SIZE 0x0
|
||||
#define HOST_RST 0x8 /* Host Reset */
|
||||
#define nHOST_RST 0x0
|
||||
#define HRDY_OVR 0x20 /* Host Ready Override */
|
||||
#define nHRDY_OVR 0x0
|
||||
#define INT_MODE 0x40 /* Interrupt Mode */
|
||||
#define nINT_MODE 0x0
|
||||
#define BT_EN 0x80 /* Bus Timeout Enable */
|
||||
#define nBT_EN 0x0
|
||||
#define EHW 0x100 /* Enable Host Write */
|
||||
#define nEHW 0x0
|
||||
#define EHR 0x200 /* Enable Host Read */
|
||||
#define nEHR 0x0
|
||||
#define BDR 0x400 /* Burst DMA Requests */
|
||||
#define nBDR 0x0
|
||||
|
||||
/* Bit masks for HOST_STATUS */
|
||||
|
||||
#define READY 0x1 /* DMA Ready */
|
||||
#define nREADY 0x0
|
||||
#define FIFOFULL 0x2 /* FIFO Full */
|
||||
#define nFIFOFULL 0x0
|
||||
#define FIFOEMPTY 0x4 /* FIFO Empty */
|
||||
#define nFIFOEMPTY 0x0
|
||||
#define COMPLETE 0x8 /* DMA Complete */
|
||||
#define nCOMPLETE 0x0
|
||||
#define HSHK 0x10 /* Host Handshake */
|
||||
#define nHSHK 0x0
|
||||
#define TIMEOUT 0x20 /* Host Timeout */
|
||||
#define nTIMEOUT 0x0
|
||||
#define HIRQ 0x40 /* Host Interrupt Request */
|
||||
#define nHIRQ 0x0
|
||||
#define ALLOW_CNFG 0x80 /* Allow New Configuration */
|
||||
#define nALLOW_CNFG 0x0
|
||||
#define DMA_DIR 0x100 /* DMA Direction */
|
||||
#define nDMA_DIR 0x0
|
||||
#define BTE 0x200 /* Bus Timeout Enabled */
|
||||
#define nBTE 0x0
|
||||
|
||||
/* Bit masks for HOST_TIMEOUT */
|
||||
|
||||
#define COUNT_TIMEOUT 0x7ff /* Host Timeout count */
|
||||
|
||||
/* Bit masks for TIMER_ENABLE1 */
|
||||
|
||||
#define TIMEN8 0x1 /* Timer 8 Enable */
|
||||
#define nTIMEN8 0x0
|
||||
#define TIMEN9 0x2 /* Timer 9 Enable */
|
||||
#define nTIMEN9 0x0
|
||||
#define TIMEN10 0x4 /* Timer 10 Enable */
|
||||
#define nTIMEN10 0x0
|
||||
|
||||
/* Bit masks for TIMER_DISABLE1 */
|
||||
|
||||
#define TIMDIS8 0x1 /* Timer 8 Disable */
|
||||
#define nTIMDIS8 0x0
|
||||
#define TIMDIS9 0x2 /* Timer 9 Disable */
|
||||
#define nTIMDIS9 0x0
|
||||
#define TIMDIS10 0x4 /* Timer 10 Disable */
|
||||
#define nTIMDIS10 0x0
|
||||
|
||||
/* Bit masks for TIMER_STATUS1 */
|
||||
|
||||
#define TIMIL8 0x1 /* Timer 8 Interrupt */
|
||||
#define nTIMIL8 0x0
|
||||
#define TIMIL9 0x2 /* Timer 9 Interrupt */
|
||||
#define nTIMIL9 0x0
|
||||
#define TIMIL10 0x4 /* Timer 10 Interrupt */
|
||||
#define nTIMIL10 0x0
|
||||
#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */
|
||||
#define nTOVF_ERR8 0x0
|
||||
#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */
|
||||
#define nTOVF_ERR9 0x0
|
||||
#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */
|
||||
#define nTOVF_ERR10 0x0
|
||||
#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */
|
||||
#define nTRUN8 0x0
|
||||
#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */
|
||||
#define nTRUN9 0x0
|
||||
#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */
|
||||
#define nTRUN10 0x0
|
||||
|
||||
/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
|
||||
|
||||
/* Bit masks for HMDMAx_CONTROL */
|
||||
|
||||
#define HMDMAEN 0x1 /* Handshake MDMA Enable */
|
||||
#define nHMDMAEN 0x0
|
||||
#define REP 0x2 /* Handshake MDMA Request Polarity */
|
||||
#define nREP 0x0
|
||||
#define UTE 0x8 /* Urgency Threshold Enable */
|
||||
#define nUTE 0x0
|
||||
#define OIE 0x10 /* Overflow Interrupt Enable */
|
||||
#define nOIE 0x0
|
||||
#define BDIE 0x20 /* Block Done Interrupt Enable */
|
||||
#define nBDIE 0x0
|
||||
#define MBDI 0x40 /* Mask Block Done Interrupt */
|
||||
#define nMBDI 0x0
|
||||
#define DRQ 0x300 /* Handshake MDMA Request Type */
|
||||
#define RBC 0x1000 /* Force Reload of BCOUNT */
|
||||
#define nRBC 0x0
|
||||
#define PS 0x2000 /* Pin Status */
|
||||
#define nPS 0x0
|
||||
#define OI 0x4000 /* Overflow Interrupt Generated */
|
||||
#define nOI 0x0
|
||||
#define BDI 0x8000 /* Block Done Interrupt Generated */
|
||||
#define nBDI 0x0
|
||||
|
||||
/* ******************************************* */
|
||||
/* MULTI BIT MACRO ENUMERATIONS */
|
||||
/* ******************************************* */
|
||||
|
||||
#endif /* _DEF_BF544_H */
|
||||
1966
include/asm-blackfin/mach-bf548/defBF548.h
Normal file
1966
include/asm-blackfin/mach-bf548/defBF548.h
Normal file
File diff suppressed because it is too large
Load Diff
3472
include/asm-blackfin/mach-bf548/defBF549.h
Normal file
3472
include/asm-blackfin/mach-bf548/defBF549.h
Normal file
File diff suppressed because it is too large
Load Diff
4902
include/asm-blackfin/mach-bf548/defBF54x_base.h
Normal file
4902
include/asm-blackfin/mach-bf548/defBF54x_base.h
Normal file
File diff suppressed because it is too large
Load Diff
@ -904,23 +904,6 @@
|
||||
#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */
|
||||
#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */
|
||||
|
||||
/* ********* WATCHDOG TIMER MASKS ********************8 */
|
||||
|
||||
/* Watchdog Timer WDOG_CTL Register */
|
||||
#define ICTL(x) ((x<<1) & 0x0006)
|
||||
#define ENABLE_RESET 0x00000000 /* Set Watchdog Timer to generate reset */
|
||||
#define ENABLE_NMI 0x00000002 /* Set Watchdog Timer to generate non-maskable interrupt */
|
||||
#define ENABLE_GPI 0x00000004 /* Set Watchdog Timer to generate general-purpose interrupt */
|
||||
#define DISABLE_EVT 0x00000006 /* Disable Watchdog Timer interrupts */
|
||||
|
||||
#define TMR_EN 0x0000
|
||||
#define TMR_DIS 0x0AD0
|
||||
#define TRO 0x8000
|
||||
|
||||
#define ICTL_P0 0x01
|
||||
#define ICTL_P1 0x02
|
||||
#define TRO_P 0x0F
|
||||
|
||||
/* ***************************** UART CONTROLLER MASKS ********************** */
|
||||
|
||||
/* UART_LCR Register */
|
||||
@ -1214,18 +1197,18 @@
|
||||
#define TIMIL9 0x0002
|
||||
#define TIMIL10 0x0004
|
||||
#define TIMIL11 0x0008
|
||||
#define TOVL_ERR0 0x00000010
|
||||
#define TOVL_ERR1 0x00000020
|
||||
#define TOVL_ERR2 0x00000040
|
||||
#define TOVL_ERR3 0x00000080
|
||||
#define TOVL_ERR4 0x00100000
|
||||
#define TOVL_ERR5 0x00200000
|
||||
#define TOVL_ERR6 0x00400000
|
||||
#define TOVL_ERR7 0x00800000
|
||||
#define TOVL_ERR8 0x0010
|
||||
#define TOVL_ERR9 0x0020
|
||||
#define TOVL_ERR10 0x0040
|
||||
#define TOVL_ERR11 0x0080
|
||||
#define TOVF_ERR0 0x00000010
|
||||
#define TOVF_ERR1 0x00000020
|
||||
#define TOVF_ERR2 0x00000040
|
||||
#define TOVF_ERR3 0x00000080
|
||||
#define TOVF_ERR4 0x00100000
|
||||
#define TOVF_ERR5 0x00200000
|
||||
#define TOVF_ERR6 0x00400000
|
||||
#define TOVF_ERR7 0x00800000
|
||||
#define TOVF_ERR8 0x0010
|
||||
#define TOVF_ERR9 0x0020
|
||||
#define TOVF_ERR10 0x0040
|
||||
#define TOVF_ERR11 0x0080
|
||||
#define TRUN0 0x00001000
|
||||
#define TRUN1 0x00002000
|
||||
#define TRUN2 0x00004000
|
||||
@ -1251,18 +1234,18 @@
|
||||
#define TIMIL9_P 0x01
|
||||
#define TIMIL10_P 0x02
|
||||
#define TIMIL11_P 0x03
|
||||
#define TOVL_ERR0_P 0x04
|
||||
#define TOVL_ERR1_P 0x05
|
||||
#define TOVL_ERR2_P 0x06
|
||||
#define TOVL_ERR3_P 0x07
|
||||
#define TOVL_ERR4_P 0x14
|
||||
#define TOVL_ERR5_P 0x15
|
||||
#define TOVL_ERR6_P 0x16
|
||||
#define TOVL_ERR7_P 0x17
|
||||
#define TOVL_ERR8_P 0x04
|
||||
#define TOVL_ERR9_P 0x05
|
||||
#define TOVL_ERR10_P 0x06
|
||||
#define TOVL_ERR11_P 0x07
|
||||
#define TOVF_ERR0_P 0x04
|
||||
#define TOVF_ERR1_P 0x05
|
||||
#define TOVF_ERR2_P 0x06
|
||||
#define TOVF_ERR3_P 0x07
|
||||
#define TOVF_ERR4_P 0x14
|
||||
#define TOVF_ERR5_P 0x15
|
||||
#define TOVF_ERR6_P 0x16
|
||||
#define TOVF_ERR7_P 0x17
|
||||
#define TOVF_ERR8_P 0x04
|
||||
#define TOVF_ERR9_P 0x05
|
||||
#define TOVF_ERR10_P 0x06
|
||||
#define TOVF_ERR11_P 0x07
|
||||
#define TRUN0_P 0x0C
|
||||
#define TRUN1_P 0x0D
|
||||
#define TRUN2_P 0x0E
|
||||
@ -1276,6 +1259,32 @@
|
||||
#define TRUN10_P 0x0E
|
||||
#define TRUN11_P 0x0F
|
||||
|
||||
/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
|
||||
#define TOVL_ERR0 TOVF_ERR0
|
||||
#define TOVL_ERR1 TOVF_ERR1
|
||||
#define TOVL_ERR2 TOVF_ERR2
|
||||
#define TOVL_ERR3 TOVF_ERR3
|
||||
#define TOVL_ERR4 TOVF_ERR4
|
||||
#define TOVL_ERR5 TOVF_ERR5
|
||||
#define TOVL_ERR6 TOVF_ERR6
|
||||
#define TOVL_ERR7 TOVF_ERR7
|
||||
#define TOVL_ERR8 TOVF_ERR8
|
||||
#define TOVL_ERR9 TOVF_ERR9
|
||||
#define TOVL_ERR10 TOVF_ERR10
|
||||
#define TOVL_ERR11 TOVF_ERR11
|
||||
#define TOVL_ERR0_P TOVF_ERR0_P
|
||||
#define TOVL_ERR1_P TOVF_ERR1_P
|
||||
#define TOVL_ERR2_P TOVF_ERR2_P
|
||||
#define TOVL_ERR3_P TOVF_ERR3_P
|
||||
#define TOVL_ERR4_P TOVF_ERR4_P
|
||||
#define TOVL_ERR5_P TOVF_ERR5_P
|
||||
#define TOVL_ERR6_P TOVF_ERR6_P
|
||||
#define TOVL_ERR7_P TOVF_ERR7_P
|
||||
#define TOVL_ERR8_P TOVF_ERR8_P
|
||||
#define TOVL_ERR9_P TOVF_ERR9_P
|
||||
#define TOVL_ERR10_P TOVF_ERR10_P
|
||||
#define TOVL_ERR11_P TOVF_ERR11_P
|
||||
|
||||
/* TIMERx_CONFIG Registers */
|
||||
#define PWM_OUT 0x0001
|
||||
#define WDTH_CAP 0x0002
|
||||
@ -1700,18 +1709,4 @@
|
||||
#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */
|
||||
#define BGSTAT 0x00000020 /* Bus granted */
|
||||
|
||||
/*VR_CTL Masks*/
|
||||
#define WAKE 0x100
|
||||
#define VLEV_6 0x60
|
||||
#define VLEV_7 0x70
|
||||
#define VLEV_8 0x80
|
||||
#define VLEV_9 0x90
|
||||
#define VLEV_10 0xA0
|
||||
#define VLEV_11 0xB0
|
||||
#define VLEV_12 0xC0
|
||||
#define VLEV_13 0xD0
|
||||
#define VLEV_14 0xE0
|
||||
#define VLEV_15 0xF0
|
||||
#define FREQ_3 0x03
|
||||
|
||||
#endif /* _DEF_BF561_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user