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arm64: dts: meson: g12b: add cooling properties

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Add missing #colling-cells field for G12B SoC
Add cooling-map for passive and hot trip point

Tested-by: Christian Hewitt <christianshewitt@gmail.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Guillaume La Roque <glaroque@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
This commit is contained in:
Guillaume La Roque 2019-10-04 11:01:13 +02:00 committed by Kevin Hilman
parent 8eef8bca12
commit 195f140318
2 changed files with 30 additions and 0 deletions
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24
arch/arm64/boot/dts/amlogic/meson-g12.dtsi
View File

@ -347,6 +347,29 @@
}; };
}; };
&cpu_thermal {
cooling-maps {
map0 {
trip = <&cpu_passive>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu102 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu103 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu_hot>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu102 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu103 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
&ethmac { &ethmac {
power-domains = <&pwrc PWRC_G12A_ETH_ID>; power-domains = <&pwrc PWRC_G12A_ETH_ID>;
}; };
@ -366,3 +389,4 @@
&simplefb_hdmi { &simplefb_hdmi {
power-domains = <&pwrc PWRC_G12A_VPU_ID>; power-domains = <&pwrc PWRC_G12A_VPU_ID>;
}; };

6
arch/arm64/boot/dts/amlogic/meson-g12b.dtsi
View File

@ -50,6 +50,7 @@
enable-method = "psci"; enable-method = "psci";
capacity-dmips-mhz = <592>; capacity-dmips-mhz = <592>;
next-level-cache = <&l2>; next-level-cache = <&l2>;
#cooling-cells = <2>;
}; };
cpu1: cpu@1 { cpu1: cpu@1 {
@ -59,6 +60,7 @@
enable-method = "psci"; enable-method = "psci";
capacity-dmips-mhz = <592>; capacity-dmips-mhz = <592>;
next-level-cache = <&l2>; next-level-cache = <&l2>;
#cooling-cells = <2>;
}; };
cpu100: cpu@100 { cpu100: cpu@100 {
@ -68,6 +70,7 @@
enable-method = "psci"; enable-method = "psci";
capacity-dmips-mhz = <1024>; capacity-dmips-mhz = <1024>;
next-level-cache = <&l2>; next-level-cache = <&l2>;
#cooling-cells = <2>;
}; };
cpu101: cpu@101 { cpu101: cpu@101 {
@ -77,6 +80,7 @@
enable-method = "psci"; enable-method = "psci";
capacity-dmips-mhz = <1024>; capacity-dmips-mhz = <1024>;
next-level-cache = <&l2>; next-level-cache = <&l2>;
#cooling-cells = <2>;
}; };
cpu102: cpu@102 { cpu102: cpu@102 {
@ -86,6 +90,7 @@
enable-method = "psci"; enable-method = "psci";
capacity-dmips-mhz = <1024>; capacity-dmips-mhz = <1024>;
next-level-cache = <&l2>; next-level-cache = <&l2>;
#cooling-cells = <2>;
}; };
cpu103: cpu@103 { cpu103: cpu@103 {
@ -95,6 +100,7 @@
enable-method = "psci"; enable-method = "psci";
capacity-dmips-mhz = <1024>; capacity-dmips-mhz = <1024>;
next-level-cache = <&l2>; next-level-cache = <&l2>;
#cooling-cells = <2>;
}; };
l2: l2-cache0 { l2: l2-cache0 {