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net: mvpp2: force the XLG MAC link up or down when not using in-band

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This patch force the XLG MAC link state in the phylink link_up() and
link_down() helpers when not using in-band auto-negotiation. This mimics
what's already done for the GMAC and follows what's advised in the
phylink documentation.

Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Antoine Tenart
2019-03-01 11:52:13 +01:00
committed by David S. Miller
parent f17e70d258
commit 1970ee9614
2 changed files with 27 additions and 10 deletions
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2
drivers/net/ethernet/marvell/mvpp2/mvpp2.h
View File

@ -430,6 +430,8 @@
#define MVPP22_XLG_CTRL0_REG 0x100 #define MVPP22_XLG_CTRL0_REG 0x100
#define MVPP22_XLG_CTRL0_PORT_EN BIT(0) #define MVPP22_XLG_CTRL0_PORT_EN BIT(0)
#define MVPP22_XLG_CTRL0_MAC_RESET_DIS BIT(1) #define MVPP22_XLG_CTRL0_MAC_RESET_DIS BIT(1)
#define MVPP22_XLG_CTRL0_FORCE_LINK_DOWN BIT(2)
#define MVPP22_XLG_CTRL0_FORCE_LINK_PASS BIT(3)
#define MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN BIT(7) #define MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN BIT(7)
#define MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN BIT(8) #define MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN BIT(8)
#define MVPP22_XLG_CTRL0_MIB_CNT_DIS BIT(14) #define MVPP22_XLG_CTRL0_MIB_CNT_DIS BIT(14)

35
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
View File

@ -4684,6 +4684,7 @@ static void mvpp2_mac_config(struct net_device *dev, unsigned int mode,
/* Make sure the port is disabled when reconfiguring the mode */ /* Make sure the port is disabled when reconfiguring the mode */
mvpp2_port_disable(port); mvpp2_port_disable(port);
if (port->priv->hw_version == MVPP22 && change_interface) { if (port->priv->hw_version == MVPP22 && change_interface) {
mvpp22_gop_mask_irq(port); mvpp22_gop_mask_irq(port);
@ -4717,11 +4718,18 @@ static void mvpp2_mac_link_up(struct net_device *dev, unsigned int mode,
struct mvpp2_port *port = netdev_priv(dev); struct mvpp2_port *port = netdev_priv(dev);
u32 val; u32 val;
if (!phylink_autoneg_inband(mode) && !mvpp2_is_xlg(interface)) { if (!phylink_autoneg_inband(mode)) {
val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); if (mvpp2_is_xlg(interface)) {
val &= ~MVPP2_GMAC_FORCE_LINK_DOWN; val = readl(port->base + MVPP22_XLG_CTRL0_REG);
val |= MVPP2_GMAC_FORCE_LINK_PASS; val &= ~MVPP22_XLG_CTRL0_FORCE_LINK_DOWN;
writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); val |= MVPP22_XLG_CTRL0_FORCE_LINK_PASS;
writel(val, port->base + MVPP22_XLG_CTRL0_REG);
} else {
val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
val &= ~MVPP2_GMAC_FORCE_LINK_DOWN;
val |= MVPP2_GMAC_FORCE_LINK_PASS;
writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
}
} }
mvpp2_port_enable(port); mvpp2_port_enable(port);
@ -4737,11 +4745,18 @@ static void mvpp2_mac_link_down(struct net_device *dev, unsigned int mode,
struct mvpp2_port *port = netdev_priv(dev); struct mvpp2_port *port = netdev_priv(dev);
u32 val; u32 val;
if (!phylink_autoneg_inband(mode) && !mvpp2_is_xlg(interface)) { if (!phylink_autoneg_inband(mode)) {
val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); if (mvpp2_is_xlg(interface)) {
val &= ~MVPP2_GMAC_FORCE_LINK_PASS; val = readl(port->base + MVPP22_XLG_CTRL0_REG);
val |= MVPP2_GMAC_FORCE_LINK_DOWN; val &= ~MVPP22_XLG_CTRL0_FORCE_LINK_PASS;
writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); val |= MVPP22_XLG_CTRL0_FORCE_LINK_DOWN;
writel(val, port->base + MVPP22_XLG_CTRL0_REG);
} else {
val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
val &= ~MVPP2_GMAC_FORCE_LINK_PASS;
val |= MVPP2_GMAC_FORCE_LINK_DOWN;
writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
}
} }
netif_tx_stop_all_queues(dev); netif_tx_stop_all_queues(dev);