reset: uniphier: rename MIO reset to SD reset for Pro5, PXs2, LD20 SoCs
I made a mistake as for naming for this block. The MIO block is not implemented for these 3 SoCs in the first place. The current naming will be a trouble if an SoC with both MIO and SD-ctrl blocks appear in the future. This driver has just been merged in the previous merge window. Rename it before the release. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
This commit is contained in:
parent
75924903c5
commit
19eb4a4722
@ -6,25 +6,25 @@ System reset
|
|||||||
|
|
||||||
Required properties:
|
Required properties:
|
||||||
- compatible: should be one of the following:
|
- compatible: should be one of the following:
|
||||||
"socionext,uniphier-sld3-reset" - for PH1-sLD3 SoC.
|
"socionext,uniphier-sld3-reset" - for sLD3 SoC.
|
||||||
"socionext,uniphier-ld4-reset" - for PH1-LD4 SoC.
|
"socionext,uniphier-ld4-reset" - for LD4 SoC.
|
||||||
"socionext,uniphier-pro4-reset" - for PH1-Pro4 SoC.
|
"socionext,uniphier-pro4-reset" - for Pro4 SoC.
|
||||||
"socionext,uniphier-sld8-reset" - for PH1-sLD8 SoC.
|
"socionext,uniphier-sld8-reset" - for sLD8 SoC.
|
||||||
"socionext,uniphier-pro5-reset" - for PH1-Pro5 SoC.
|
"socionext,uniphier-pro5-reset" - for Pro5 SoC.
|
||||||
"socionext,uniphier-pxs2-reset" - for ProXstream2/PH1-LD6b SoC.
|
"socionext,uniphier-pxs2-reset" - for PXs2/LD6b SoC.
|
||||||
"socionext,uniphier-ld11-reset" - for PH1-LD11 SoC.
|
"socionext,uniphier-ld11-reset" - for LD11 SoC.
|
||||||
"socionext,uniphier-ld20-reset" - for PH1-LD20 SoC.
|
"socionext,uniphier-ld20-reset" - for LD20 SoC.
|
||||||
- #reset-cells: should be 1.
|
- #reset-cells: should be 1.
|
||||||
|
|
||||||
Example:
|
Example:
|
||||||
|
|
||||||
sysctrl@61840000 {
|
sysctrl@61840000 {
|
||||||
compatible = "socionext,uniphier-ld20-sysctrl",
|
compatible = "socionext,uniphier-ld11-sysctrl",
|
||||||
"simple-mfd", "syscon";
|
"simple-mfd", "syscon";
|
||||||
reg = <0x61840000 0x4000>;
|
reg = <0x61840000 0x4000>;
|
||||||
|
|
||||||
reset {
|
reset {
|
||||||
compatible = "socionext,uniphier-ld20-reset";
|
compatible = "socionext,uniphier-ld11-reset";
|
||||||
#reset-cells = <1>;
|
#reset-cells = <1>;
|
||||||
};
|
};
|
||||||
|
|
||||||
@ -32,30 +32,30 @@ Example:
|
|||||||
};
|
};
|
||||||
|
|
||||||
|
|
||||||
Media I/O (MIO) reset
|
Media I/O (MIO) reset, SD reset
|
||||||
---------------------
|
-------------------------------
|
||||||
|
|
||||||
Required properties:
|
Required properties:
|
||||||
- compatible: should be one of the following:
|
- compatible: should be one of the following:
|
||||||
"socionext,uniphier-sld3-mio-reset" - for PH1-sLD3 SoC.
|
"socionext,uniphier-sld3-mio-reset" - for sLD3 SoC.
|
||||||
"socionext,uniphier-ld4-mio-reset" - for PH1-LD4 SoC.
|
"socionext,uniphier-ld4-mio-reset" - for LD4 SoC.
|
||||||
"socionext,uniphier-pro4-mio-reset" - for PH1-Pro4 SoC.
|
"socionext,uniphier-pro4-mio-reset" - for Pro4 SoC.
|
||||||
"socionext,uniphier-sld8-mio-reset" - for PH1-sLD8 SoC.
|
"socionext,uniphier-sld8-mio-reset" - for sLD8 SoC.
|
||||||
"socionext,uniphier-pro5-mio-reset" - for PH1-Pro5 SoC.
|
"socionext,uniphier-pro5-sd-reset" - for Pro5 SoC.
|
||||||
"socionext,uniphier-pxs2-mio-reset" - for ProXstream2/PH1-LD6b SoC.
|
"socionext,uniphier-pxs2-sd-reset" - for PXs2/LD6b SoC.
|
||||||
"socionext,uniphier-ld11-mio-reset" - for PH1-LD11 SoC.
|
"socionext,uniphier-ld11-mio-reset" - for LD11 SoC.
|
||||||
"socionext,uniphier-ld20-mio-reset" - for PH1-LD20 SoC.
|
"socionext,uniphier-ld20-sd-reset" - for LD20 SoC.
|
||||||
- #reset-cells: should be 1.
|
- #reset-cells: should be 1.
|
||||||
|
|
||||||
Example:
|
Example:
|
||||||
|
|
||||||
mioctrl@59810000 {
|
mioctrl@59810000 {
|
||||||
compatible = "socionext,uniphier-ld20-mioctrl",
|
compatible = "socionext,uniphier-ld11-mioctrl",
|
||||||
"simple-mfd", "syscon";
|
"simple-mfd", "syscon";
|
||||||
reg = <0x59810000 0x800>;
|
reg = <0x59810000 0x800>;
|
||||||
|
|
||||||
reset {
|
reset {
|
||||||
compatible = "socionext,uniphier-ld20-mio-reset";
|
compatible = "socionext,uniphier-ld11-mio-reset";
|
||||||
#reset-cells = <1>;
|
#reset-cells = <1>;
|
||||||
};
|
};
|
||||||
|
|
||||||
@ -68,24 +68,24 @@ Peripheral reset
|
|||||||
|
|
||||||
Required properties:
|
Required properties:
|
||||||
- compatible: should be one of the following:
|
- compatible: should be one of the following:
|
||||||
"socionext,uniphier-ld4-peri-reset" - for PH1-LD4 SoC.
|
"socionext,uniphier-ld4-peri-reset" - for LD4 SoC.
|
||||||
"socionext,uniphier-pro4-peri-reset" - for PH1-Pro4 SoC.
|
"socionext,uniphier-pro4-peri-reset" - for Pro4 SoC.
|
||||||
"socionext,uniphier-sld8-peri-reset" - for PH1-sLD8 SoC.
|
"socionext,uniphier-sld8-peri-reset" - for sLD8 SoC.
|
||||||
"socionext,uniphier-pro5-peri-reset" - for PH1-Pro5 SoC.
|
"socionext,uniphier-pro5-peri-reset" - for Pro5 SoC.
|
||||||
"socionext,uniphier-pxs2-peri-reset" - for ProXstream2/PH1-LD6b SoC.
|
"socionext,uniphier-pxs2-peri-reset" - for PXs2/LD6b SoC.
|
||||||
"socionext,uniphier-ld11-peri-reset" - for PH1-LD11 SoC.
|
"socionext,uniphier-ld11-peri-reset" - for LD11 SoC.
|
||||||
"socionext,uniphier-ld20-peri-reset" - for PH1-LD20 SoC.
|
"socionext,uniphier-ld20-peri-reset" - for LD20 SoC.
|
||||||
- #reset-cells: should be 1.
|
- #reset-cells: should be 1.
|
||||||
|
|
||||||
Example:
|
Example:
|
||||||
|
|
||||||
perictrl@59820000 {
|
perictrl@59820000 {
|
||||||
compatible = "socionext,uniphier-ld20-perictrl",
|
compatible = "socionext,uniphier-ld11-perictrl",
|
||||||
"simple-mfd", "syscon";
|
"simple-mfd", "syscon";
|
||||||
reg = <0x59820000 0x200>;
|
reg = <0x59820000 0x200>;
|
||||||
|
|
||||||
reset {
|
reset {
|
||||||
compatible = "socionext,uniphier-ld20-peri-reset";
|
compatible = "socionext,uniphier-ld11-peri-reset";
|
||||||
#reset-cells = <1>;
|
#reset-cells = <1>;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
@ -154,7 +154,7 @@ const struct uniphier_reset_data uniphier_sld3_mio_reset_data[] = {
|
|||||||
UNIPHIER_RESET_END,
|
UNIPHIER_RESET_END,
|
||||||
};
|
};
|
||||||
|
|
||||||
const struct uniphier_reset_data uniphier_pro5_mio_reset_data[] = {
|
const struct uniphier_reset_data uniphier_pro5_sd_reset_data[] = {
|
||||||
UNIPHIER_MIO_RESET_SD(0, 0),
|
UNIPHIER_MIO_RESET_SD(0, 0),
|
||||||
UNIPHIER_MIO_RESET_SD(1, 1),
|
UNIPHIER_MIO_RESET_SD(1, 1),
|
||||||
UNIPHIER_MIO_RESET_EMMC_HW_RESET(6, 1),
|
UNIPHIER_MIO_RESET_EMMC_HW_RESET(6, 1),
|
||||||
@ -360,7 +360,7 @@ static const struct of_device_id uniphier_reset_match[] = {
|
|||||||
.compatible = "socionext,uniphier-ld20-reset",
|
.compatible = "socionext,uniphier-ld20-reset",
|
||||||
.data = uniphier_ld20_sys_reset_data,
|
.data = uniphier_ld20_sys_reset_data,
|
||||||
},
|
},
|
||||||
/* Media I/O reset */
|
/* Media I/O reset, SD reset */
|
||||||
{
|
{
|
||||||
.compatible = "socionext,uniphier-sld3-mio-reset",
|
.compatible = "socionext,uniphier-sld3-mio-reset",
|
||||||
.data = uniphier_sld3_mio_reset_data,
|
.data = uniphier_sld3_mio_reset_data,
|
||||||
@ -378,20 +378,20 @@ static const struct of_device_id uniphier_reset_match[] = {
|
|||||||
.data = uniphier_sld3_mio_reset_data,
|
.data = uniphier_sld3_mio_reset_data,
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
.compatible = "socionext,uniphier-pro5-mio-reset",
|
.compatible = "socionext,uniphier-pro5-sd-reset",
|
||||||
.data = uniphier_pro5_mio_reset_data,
|
.data = uniphier_pro5_sd_reset_data,
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
.compatible = "socionext,uniphier-pxs2-mio-reset",
|
.compatible = "socionext,uniphier-pxs2-sd-reset",
|
||||||
.data = uniphier_pro5_mio_reset_data,
|
.data = uniphier_pro5_sd_reset_data,
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
.compatible = "socionext,uniphier-ld11-mio-reset",
|
.compatible = "socionext,uniphier-ld11-mio-reset",
|
||||||
.data = uniphier_sld3_mio_reset_data,
|
.data = uniphier_sld3_mio_reset_data,
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
.compatible = "socionext,uniphier-ld20-mio-reset",
|
.compatible = "socionext,uniphier-ld20-sd-reset",
|
||||||
.data = uniphier_pro5_mio_reset_data,
|
.data = uniphier_pro5_sd_reset_data,
|
||||||
},
|
},
|
||||||
/* Peripheral reset */
|
/* Peripheral reset */
|
||||||
{
|
{
|
||||||
|
Loading…
Reference in New Issue
Block a user