ASoC: Merge fixes due to dependencies
So we can apply the tlv320aic3xxx DT conversion.
This commit is contained in:
commit
1a32b4b9a6
@ -8,7 +8,7 @@ Required properties:
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"ti,tlv320aic32x6" TLV320AIC3206, TLV320AIC3256
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"ti,tlv320aic32x6" TLV320AIC3206, TLV320AIC3256
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"ti,tas2505" TAS2505, TAS2521
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"ti,tas2505" TAS2505, TAS2521
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- reg: I2C slave address
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- reg: I2C slave address
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- supply-*: Required supply regulators are:
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- *-supply: Required supply regulators are:
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"iov" - digital IO power supply
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"iov" - digital IO power supply
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"ldoin" - LDO power supply
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"ldoin" - LDO power supply
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"dv" - Digital core power supply
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"dv" - Digital core power supply
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@ -2124,6 +2124,7 @@ static int cs_dsp_load_coeff(struct cs_dsp *dsp, const struct firmware *firmware
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file, blocks, le32_to_cpu(blk->len),
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file, blocks, le32_to_cpu(blk->len),
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type, le32_to_cpu(blk->id));
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type, le32_to_cpu(blk->id));
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region_name = cs_dsp_mem_region_name(type);
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mem = cs_dsp_find_region(dsp, type);
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mem = cs_dsp_find_region(dsp, type);
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if (!mem) {
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if (!mem) {
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cs_dsp_err(dsp, "No base for region %x\n", type);
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cs_dsp_err(dsp, "No base for region %x\n", type);
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@ -2147,8 +2148,8 @@ static int cs_dsp_load_coeff(struct cs_dsp *dsp, const struct firmware *firmware
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reg = dsp->ops->region_to_reg(mem, reg);
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reg = dsp->ops->region_to_reg(mem, reg);
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reg += offset;
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reg += offset;
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} else {
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} else {
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cs_dsp_err(dsp, "No %x for algorithm %x\n",
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cs_dsp_err(dsp, "No %s for algorithm %x\n",
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type, le32_to_cpu(blk->id));
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region_name, le32_to_cpu(blk->id));
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}
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}
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break;
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break;
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@ -170,6 +170,7 @@ struct snd_soc_acpi_link_adr {
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/* Descriptor for SST ASoC machine driver */
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/* Descriptor for SST ASoC machine driver */
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struct snd_soc_acpi_mach {
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struct snd_soc_acpi_mach {
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u8 id[ACPI_ID_LEN];
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u8 id[ACPI_ID_LEN];
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const char *uid;
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const struct snd_soc_acpi_codecs *comp_ids;
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const struct snd_soc_acpi_codecs *comp_ids;
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const u32 link_mask;
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const u32 link_mask;
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const struct snd_soc_acpi_link_adr *links;
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const struct snd_soc_acpi_link_adr *links;
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@ -122,6 +122,10 @@ int snd_soc_dpcm_can_be_free_stop(struct snd_soc_pcm_runtime *fe,
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int snd_soc_dpcm_can_be_params(struct snd_soc_pcm_runtime *fe,
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int snd_soc_dpcm_can_be_params(struct snd_soc_pcm_runtime *fe,
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struct snd_soc_pcm_runtime *be, int stream);
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struct snd_soc_pcm_runtime *be, int stream);
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/* can this BE perform prepare */
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int snd_soc_dpcm_can_be_prepared(struct snd_soc_pcm_runtime *fe,
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struct snd_soc_pcm_runtime *be, int stream);
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/* is the current PCM operation for this FE ? */
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/* is the current PCM operation for this FE ? */
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int snd_soc_dpcm_fe_can_update(struct snd_soc_pcm_runtime *fe, int stream);
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int snd_soc_dpcm_fe_can_update(struct snd_soc_pcm_runtime *fe, int stream);
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@ -66,7 +66,8 @@ enum skl_ch_cfg {
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SKL_CH_CFG_DUAL_MONO = 9,
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SKL_CH_CFG_DUAL_MONO = 9,
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SKL_CH_CFG_I2S_DUAL_STEREO_0 = 10,
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SKL_CH_CFG_I2S_DUAL_STEREO_0 = 10,
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SKL_CH_CFG_I2S_DUAL_STEREO_1 = 11,
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SKL_CH_CFG_I2S_DUAL_STEREO_1 = 11,
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SKL_CH_CFG_4_CHANNEL = 12,
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SKL_CH_CFG_7_1 = 12,
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SKL_CH_CFG_4_CHANNEL = SKL_CH_CFG_7_1,
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SKL_CH_CFG_INVALID
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SKL_CH_CFG_INVALID
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};
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};
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@ -198,8 +198,7 @@ static int create_acp63_platform_devs(struct pci_dev *pci, struct acp63_dev_data
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case ACP63_PDM_DEV_MASK:
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case ACP63_PDM_DEV_MASK:
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adata->pdm_dev_index = 0;
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adata->pdm_dev_index = 0;
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acp63_fill_platform_dev_info(&pdevinfo[0], parent, NULL, "acp_ps_pdm_dma",
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acp63_fill_platform_dev_info(&pdevinfo[0], parent, NULL, "acp_ps_pdm_dma",
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0, adata->res, 1, &adata->acp_lock,
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0, adata->res, 1, NULL, 0);
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sizeof(adata->acp_lock));
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acp63_fill_platform_dev_info(&pdevinfo[1], parent, NULL, "dmic-codec",
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acp63_fill_platform_dev_info(&pdevinfo[1], parent, NULL, "dmic-codec",
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0, NULL, 0, NULL, 0);
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0, NULL, 0, NULL, 0);
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acp63_fill_platform_dev_info(&pdevinfo[2], parent, NULL, "acp_ps_mach",
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acp63_fill_platform_dev_info(&pdevinfo[2], parent, NULL, "acp_ps_mach",
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@ -358,12 +358,12 @@ static int acp63_pdm_audio_probe(struct platform_device *pdev)
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{
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{
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struct resource *res;
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struct resource *res;
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struct pdm_dev_data *adata;
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struct pdm_dev_data *adata;
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struct acp63_dev_data *acp_data;
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struct device *parent;
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int status;
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int status;
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if (!pdev->dev.platform_data) {
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parent = pdev->dev.parent;
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dev_err(&pdev->dev, "platform_data not retrieved\n");
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acp_data = dev_get_drvdata(parent);
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return -ENODEV;
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}
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res) {
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if (!res) {
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dev_err(&pdev->dev, "IORESOURCE_MEM FAILED\n");
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dev_err(&pdev->dev, "IORESOURCE_MEM FAILED\n");
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@ -379,7 +379,7 @@ static int acp63_pdm_audio_probe(struct platform_device *pdev)
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return -ENOMEM;
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return -ENOMEM;
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adata->capture_stream = NULL;
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adata->capture_stream = NULL;
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adata->acp_lock = pdev->dev.platform_data;
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adata->acp_lock = &acp_data->acp_lock;
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dev_set_drvdata(&pdev->dev, adata);
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dev_set_drvdata(&pdev->dev, adata);
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status = devm_snd_soc_register_component(&pdev->dev,
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status = devm_snd_soc_register_component(&pdev->dev,
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&acp63_pdm_component,
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&acp63_pdm_component,
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@ -171,6 +171,13 @@ static const struct dmi_system_id yc_acp_quirk_table[] = {
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DMI_MATCH(DMI_PRODUCT_NAME, "21CL"),
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DMI_MATCH(DMI_PRODUCT_NAME, "21CL"),
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}
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}
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},
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},
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{
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.driver_data = &acp6x_card,
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.matches = {
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DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
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DMI_MATCH(DMI_PRODUCT_NAME, "21EF"),
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}
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},
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{
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{
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.driver_data = &acp6x_card,
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.driver_data = &acp6x_card,
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.matches = {
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.matches = {
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@ -46,7 +46,7 @@ static const struct reg_default cs35l41_reg[] = {
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{ CS35L41_DSP1_RX5_SRC, 0x00000020 },
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{ CS35L41_DSP1_RX5_SRC, 0x00000020 },
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{ CS35L41_DSP1_RX6_SRC, 0x00000021 },
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{ CS35L41_DSP1_RX6_SRC, 0x00000021 },
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{ CS35L41_DSP1_RX7_SRC, 0x0000003A },
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{ CS35L41_DSP1_RX7_SRC, 0x0000003A },
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{ CS35L41_DSP1_RX8_SRC, 0x00000001 },
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{ CS35L41_DSP1_RX8_SRC, 0x0000003B },
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{ CS35L41_NGATE1_SRC, 0x00000008 },
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{ CS35L41_NGATE1_SRC, 0x00000008 },
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{ CS35L41_NGATE2_SRC, 0x00000009 },
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{ CS35L41_NGATE2_SRC, 0x00000009 },
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{ CS35L41_AMP_DIG_VOL_CTRL, 0x00008000 },
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{ CS35L41_AMP_DIG_VOL_CTRL, 0x00008000 },
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@ -58,8 +58,8 @@ static const struct reg_default cs35l41_reg[] = {
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{ CS35L41_IRQ1_MASK2, 0xFFFFFFFF },
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{ CS35L41_IRQ1_MASK2, 0xFFFFFFFF },
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{ CS35L41_IRQ1_MASK3, 0xFFFF87FF },
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{ CS35L41_IRQ1_MASK3, 0xFFFF87FF },
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{ CS35L41_IRQ1_MASK4, 0xFEFFFFFF },
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{ CS35L41_IRQ1_MASK4, 0xFEFFFFFF },
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{ CS35L41_GPIO1_CTRL1, 0xE1000001 },
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{ CS35L41_GPIO1_CTRL1, 0x81000001 },
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{ CS35L41_GPIO2_CTRL1, 0xE1000001 },
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{ CS35L41_GPIO2_CTRL1, 0x81000001 },
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{ CS35L41_MIXER_NGATE_CFG, 0x00000000 },
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{ CS35L41_MIXER_NGATE_CFG, 0x00000000 },
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{ CS35L41_MIXER_NGATE_CH1_CFG, 0x00000303 },
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{ CS35L41_MIXER_NGATE_CH1_CFG, 0x00000303 },
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{ CS35L41_MIXER_NGATE_CH2_CFG, 0x00000303 },
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{ CS35L41_MIXER_NGATE_CH2_CFG, 0x00000303 },
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@ -704,9 +704,6 @@ static int cs35l56_sdw_dai_hw_free(struct snd_pcm_substream *substream,
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static int cs35l56_sdw_dai_set_stream(struct snd_soc_dai *dai,
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static int cs35l56_sdw_dai_set_stream(struct snd_soc_dai *dai,
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void *sdw_stream, int direction)
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void *sdw_stream, int direction)
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{
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{
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if (!sdw_stream)
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return 0;
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snd_soc_dai_dma_data_set(dai, direction, sdw_stream);
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snd_soc_dai_dma_data_set(dai, direction, sdw_stream);
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return 0;
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return 0;
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@ -746,6 +746,8 @@ static int tx_macro_put_dec_enum(struct snd_kcontrol *kcontrol,
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struct tx_macro *tx = snd_soc_component_get_drvdata(component);
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struct tx_macro *tx = snd_soc_component_get_drvdata(component);
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val = ucontrol->value.enumerated.item[0];
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val = ucontrol->value.enumerated.item[0];
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if (val >= e->items)
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return -EINVAL;
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switch (e->reg) {
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switch (e->reg) {
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case CDC_TX_INP_MUX_ADC_MUX0_CFG0:
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case CDC_TX_INP_MUX_ADC_MUX0_CFG0:
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@ -772,6 +774,9 @@ static int tx_macro_put_dec_enum(struct snd_kcontrol *kcontrol,
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case CDC_TX_INP_MUX_ADC_MUX7_CFG0:
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case CDC_TX_INP_MUX_ADC_MUX7_CFG0:
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mic_sel_reg = CDC_TX7_TX_PATH_CFG0;
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mic_sel_reg = CDC_TX7_TX_PATH_CFG0;
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break;
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break;
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default:
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dev_err(component->dev, "Error in configuration!!\n");
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return -EINVAL;
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}
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}
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if (val != 0) {
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if (val != 0) {
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@ -211,7 +211,7 @@ static int max98363_io_init(struct sdw_slave *slave)
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}
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}
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#define MAX98363_RATES SNDRV_PCM_RATE_8000_192000
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#define MAX98363_RATES SNDRV_PCM_RATE_8000_192000
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#define MAX98363_FORMATS (SNDRV_PCM_FMTBIT_S32_LE)
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#define MAX98363_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
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static int max98363_sdw_dai_hw_params(struct snd_pcm_substream *substream,
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static int max98363_sdw_dai_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_pcm_hw_params *params,
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@ -246,7 +246,7 @@ static int max98363_sdw_dai_hw_params(struct snd_pcm_substream *substream,
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stream_config.frame_rate = params_rate(params);
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stream_config.frame_rate = params_rate(params);
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stream_config.bps = snd_pcm_format_width(params_format(params));
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stream_config.bps = snd_pcm_format_width(params_format(params));
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stream_config.direction = direction;
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stream_config.direction = direction;
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stream_config.ch_count = params_channels(params);
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stream_config.ch_count = 1;
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if (stream_config.ch_count > runtime->hw.channels_max) {
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if (stream_config.ch_count > runtime->hw.channels_max) {
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stream_config.ch_count = runtime->hw.channels_max;
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stream_config.ch_count = runtime->hw.channels_max;
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@ -1903,6 +1903,30 @@ static const struct dmi_system_id nau8824_quirk_table[] = {
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},
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},
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.driver_data = (void *)(NAU8824_MONO_SPEAKER),
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.driver_data = (void *)(NAU8824_MONO_SPEAKER),
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},
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},
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{
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/* Positivo CW14Q01P */
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "Positivo Tecnologia SA"),
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DMI_MATCH(DMI_BOARD_NAME, "CW14Q01P"),
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},
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.driver_data = (void *)(NAU8824_JD_ACTIVE_HIGH),
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},
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{
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/* Positivo K1424G */
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "Positivo Tecnologia SA"),
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DMI_MATCH(DMI_BOARD_NAME, "K1424G"),
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},
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.driver_data = (void *)(NAU8824_JD_ACTIVE_HIGH),
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},
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{
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/* Positivo N14ZP74G */
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "Positivo Tecnologia SA"),
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DMI_MATCH(DMI_BOARD_NAME, "N14ZP74G"),
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},
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.driver_data = (void *)(NAU8824_JD_ACTIVE_HIGH),
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},
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{}
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{}
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};
|
};
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@ -266,7 +266,9 @@ static int rt5682_i2c_probe(struct i2c_client *i2c)
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ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL,
|
ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL,
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rt5682_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
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rt5682_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
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| IRQF_ONESHOT, "rt5682", rt5682);
|
| IRQF_ONESHOT, "rt5682", rt5682);
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if (ret)
|
if (!ret)
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|
rt5682->irq = i2c->irq;
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|
else
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dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
|
dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
|
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}
|
}
|
||||||
|
|
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@ -2959,6 +2959,9 @@ static int rt5682_suspend(struct snd_soc_component *component)
|
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if (rt5682->is_sdw)
|
if (rt5682->is_sdw)
|
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return 0;
|
return 0;
|
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|
|
||||||
|
if (rt5682->irq)
|
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|
disable_irq(rt5682->irq);
|
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|
|
||||||
cancel_delayed_work_sync(&rt5682->jack_detect_work);
|
cancel_delayed_work_sync(&rt5682->jack_detect_work);
|
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cancel_delayed_work_sync(&rt5682->jd_check_work);
|
cancel_delayed_work_sync(&rt5682->jd_check_work);
|
||||||
if (rt5682->hs_jack && (rt5682->jack_type & SND_JACK_HEADSET) == SND_JACK_HEADSET) {
|
if (rt5682->hs_jack && (rt5682->jack_type & SND_JACK_HEADSET) == SND_JACK_HEADSET) {
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@ -3027,6 +3030,9 @@ static int rt5682_resume(struct snd_soc_component *component)
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mod_delayed_work(system_power_efficient_wq,
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mod_delayed_work(system_power_efficient_wq,
|
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&rt5682->jack_detect_work, msecs_to_jiffies(0));
|
&rt5682->jack_detect_work, msecs_to_jiffies(0));
|
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|
|
||||||
|
if (rt5682->irq)
|
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|
enable_irq(rt5682->irq);
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
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#else
|
#else
|
||||||
|
@ -1461,6 +1461,7 @@ struct rt5682_priv {
|
|||||||
int pll_out[RT5682_PLLS];
|
int pll_out[RT5682_PLLS];
|
||||||
|
|
||||||
int jack_type;
|
int jack_type;
|
||||||
|
int irq;
|
||||||
int irq_work_delay_time;
|
int irq_work_delay_time;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
@ -1190,7 +1190,6 @@ static const struct regmap_config wcd938x_regmap_config = {
|
|||||||
.readable_reg = wcd938x_readable_register,
|
.readable_reg = wcd938x_readable_register,
|
||||||
.writeable_reg = wcd938x_writeable_register,
|
.writeable_reg = wcd938x_writeable_register,
|
||||||
.volatile_reg = wcd938x_volatile_register,
|
.volatile_reg = wcd938x_volatile_register,
|
||||||
.can_multi_write = true,
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static const struct sdw_slave_ops wcd9380_slave_ops = {
|
static const struct sdw_slave_ops wcd9380_slave_ops = {
|
||||||
|
@ -645,7 +645,6 @@ static struct regmap_config wsa881x_regmap_config = {
|
|||||||
.readable_reg = wsa881x_readable_register,
|
.readable_reg = wsa881x_readable_register,
|
||||||
.reg_format_endian = REGMAP_ENDIAN_NATIVE,
|
.reg_format_endian = REGMAP_ENDIAN_NATIVE,
|
||||||
.val_format_endian = REGMAP_ENDIAN_NATIVE,
|
.val_format_endian = REGMAP_ENDIAN_NATIVE,
|
||||||
.can_multi_write = true,
|
|
||||||
};
|
};
|
||||||
|
|
||||||
enum {
|
enum {
|
||||||
|
@ -946,7 +946,6 @@ static struct regmap_config wsa883x_regmap_config = {
|
|||||||
.writeable_reg = wsa883x_writeable_register,
|
.writeable_reg = wsa883x_writeable_register,
|
||||||
.reg_format_endian = REGMAP_ENDIAN_NATIVE,
|
.reg_format_endian = REGMAP_ENDIAN_NATIVE,
|
||||||
.val_format_endian = REGMAP_ENDIAN_NATIVE,
|
.val_format_endian = REGMAP_ENDIAN_NATIVE,
|
||||||
.can_multi_write = true,
|
|
||||||
.use_single_read = true,
|
.use_single_read = true,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
@ -184,30 +184,6 @@ static void i2s_stop(struct dw_i2s_dev *dev,
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
static int dw_i2s_startup(struct snd_pcm_substream *substream,
|
|
||||||
struct snd_soc_dai *cpu_dai)
|
|
||||||
{
|
|
||||||
struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
|
|
||||||
union dw_i2s_snd_dma_data *dma_data = NULL;
|
|
||||||
|
|
||||||
if (!(dev->capability & DWC_I2S_RECORD) &&
|
|
||||||
(substream->stream == SNDRV_PCM_STREAM_CAPTURE))
|
|
||||||
return -EINVAL;
|
|
||||||
|
|
||||||
if (!(dev->capability & DWC_I2S_PLAY) &&
|
|
||||||
(substream->stream == SNDRV_PCM_STREAM_PLAYBACK))
|
|
||||||
return -EINVAL;
|
|
||||||
|
|
||||||
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
|
|
||||||
dma_data = &dev->play_dma_data;
|
|
||||||
else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
|
|
||||||
dma_data = &dev->capture_dma_data;
|
|
||||||
|
|
||||||
snd_soc_dai_set_dma_data(cpu_dai, substream, (void *)dma_data);
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static void dw_i2s_config(struct dw_i2s_dev *dev, int stream)
|
static void dw_i2s_config(struct dw_i2s_dev *dev, int stream)
|
||||||
{
|
{
|
||||||
u32 ch_reg;
|
u32 ch_reg;
|
||||||
@ -306,12 +282,6 @@ static int dw_i2s_hw_params(struct snd_pcm_substream *substream,
|
|||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
static void dw_i2s_shutdown(struct snd_pcm_substream *substream,
|
|
||||||
struct snd_soc_dai *dai)
|
|
||||||
{
|
|
||||||
snd_soc_dai_set_dma_data(dai, substream, NULL);
|
|
||||||
}
|
|
||||||
|
|
||||||
static int dw_i2s_prepare(struct snd_pcm_substream *substream,
|
static int dw_i2s_prepare(struct snd_pcm_substream *substream,
|
||||||
struct snd_soc_dai *dai)
|
struct snd_soc_dai *dai)
|
||||||
{
|
{
|
||||||
@ -383,8 +353,6 @@ static int dw_i2s_set_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
|
|||||||
}
|
}
|
||||||
|
|
||||||
static const struct snd_soc_dai_ops dw_i2s_dai_ops = {
|
static const struct snd_soc_dai_ops dw_i2s_dai_ops = {
|
||||||
.startup = dw_i2s_startup,
|
|
||||||
.shutdown = dw_i2s_shutdown,
|
|
||||||
.hw_params = dw_i2s_hw_params,
|
.hw_params = dw_i2s_hw_params,
|
||||||
.prepare = dw_i2s_prepare,
|
.prepare = dw_i2s_prepare,
|
||||||
.trigger = dw_i2s_trigger,
|
.trigger = dw_i2s_trigger,
|
||||||
@ -626,6 +594,14 @@ static int dw_configure_dai_by_dt(struct dw_i2s_dev *dev,
|
|||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static int dw_i2s_dai_probe(struct snd_soc_dai *dai)
|
||||||
|
{
|
||||||
|
struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
|
||||||
|
|
||||||
|
snd_soc_dai_init_dma_data(dai, &dev->play_dma_data, &dev->capture_dma_data);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
static int dw_i2s_probe(struct platform_device *pdev)
|
static int dw_i2s_probe(struct platform_device *pdev)
|
||||||
{
|
{
|
||||||
const struct i2s_platform_data *pdata = pdev->dev.platform_data;
|
const struct i2s_platform_data *pdata = pdev->dev.platform_data;
|
||||||
@ -644,6 +620,7 @@ static int dw_i2s_probe(struct platform_device *pdev)
|
|||||||
return -ENOMEM;
|
return -ENOMEM;
|
||||||
|
|
||||||
dw_i2s_dai->ops = &dw_i2s_dai_ops;
|
dw_i2s_dai->ops = &dw_i2s_dai_ops;
|
||||||
|
dw_i2s_dai->probe = dw_i2s_dai_probe;
|
||||||
|
|
||||||
dev->i2s_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
|
dev->i2s_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
|
||||||
if (IS_ERR(dev->i2s_base))
|
if (IS_ERR(dev->i2s_base))
|
||||||
|
@ -491,14 +491,21 @@ static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
|
|||||||
regmap_update_bits(sai->regmap, reg, FSL_SAI_CR2_MSEL_MASK,
|
regmap_update_bits(sai->regmap, reg, FSL_SAI_CR2_MSEL_MASK,
|
||||||
FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
|
FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
|
||||||
|
|
||||||
if (savediv == 1)
|
if (savediv == 1) {
|
||||||
regmap_update_bits(sai->regmap, reg,
|
regmap_update_bits(sai->regmap, reg,
|
||||||
FSL_SAI_CR2_DIV_MASK | FSL_SAI_CR2_BYP,
|
FSL_SAI_CR2_DIV_MASK | FSL_SAI_CR2_BYP,
|
||||||
FSL_SAI_CR2_BYP);
|
FSL_SAI_CR2_BYP);
|
||||||
else
|
if (fsl_sai_dir_is_synced(sai, adir))
|
||||||
|
regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
|
||||||
|
FSL_SAI_CR2_BCI, FSL_SAI_CR2_BCI);
|
||||||
|
else
|
||||||
|
regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
|
||||||
|
FSL_SAI_CR2_BCI, 0);
|
||||||
|
} else {
|
||||||
regmap_update_bits(sai->regmap, reg,
|
regmap_update_bits(sai->regmap, reg,
|
||||||
FSL_SAI_CR2_DIV_MASK | FSL_SAI_CR2_BYP,
|
FSL_SAI_CR2_DIV_MASK | FSL_SAI_CR2_BYP,
|
||||||
savediv / 2 - 1);
|
savediv / 2 - 1);
|
||||||
|
}
|
||||||
|
|
||||||
if (sai->soc_data->max_register >= FSL_SAI_MCTL) {
|
if (sai->soc_data->max_register >= FSL_SAI_MCTL) {
|
||||||
/* SAI is in master mode at this point, so enable MCLK */
|
/* SAI is in master mode at this point, so enable MCLK */
|
||||||
|
@ -116,6 +116,7 @@
|
|||||||
|
|
||||||
/* SAI Transmit and Receive Configuration 2 Register */
|
/* SAI Transmit and Receive Configuration 2 Register */
|
||||||
#define FSL_SAI_CR2_SYNC BIT(30)
|
#define FSL_SAI_CR2_SYNC BIT(30)
|
||||||
|
#define FSL_SAI_CR2_BCI BIT(28)
|
||||||
#define FSL_SAI_CR2_MSEL_MASK (0x3 << 26)
|
#define FSL_SAI_CR2_MSEL_MASK (0x3 << 26)
|
||||||
#define FSL_SAI_CR2_MSEL_BUS 0
|
#define FSL_SAI_CR2_MSEL_BUS 0
|
||||||
#define FSL_SAI_CR2_MSEL_MCLK1 BIT(26)
|
#define FSL_SAI_CR2_MSEL_MCLK1 BIT(26)
|
||||||
|
@ -314,7 +314,7 @@ int asoc_simple_startup(struct snd_pcm_substream *substream)
|
|||||||
}
|
}
|
||||||
ret = snd_pcm_hw_constraint_minmax(substream->runtime, SNDRV_PCM_HW_PARAM_RATE,
|
ret = snd_pcm_hw_constraint_minmax(substream->runtime, SNDRV_PCM_HW_PARAM_RATE,
|
||||||
fixed_rate, fixed_rate);
|
fixed_rate, fixed_rate);
|
||||||
if (ret)
|
if (ret < 0)
|
||||||
goto codec_err;
|
goto codec_err;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -416,6 +416,7 @@ static int __simple_for_each_link(struct asoc_simple_priv *priv,
|
|||||||
|
|
||||||
if (ret < 0) {
|
if (ret < 0) {
|
||||||
of_node_put(codec);
|
of_node_put(codec);
|
||||||
|
of_node_put(plat);
|
||||||
of_node_put(np);
|
of_node_put(np);
|
||||||
goto error;
|
goto error;
|
||||||
}
|
}
|
||||||
|
@ -169,6 +169,7 @@ static bool apl_lp_streaming(struct avs_dev *adev)
|
|||||||
{
|
{
|
||||||
struct avs_path *path;
|
struct avs_path *path;
|
||||||
|
|
||||||
|
spin_lock(&adev->path_list_lock);
|
||||||
/* Any gateway without buffer allocated in LP area disqualifies D0IX. */
|
/* Any gateway without buffer allocated in LP area disqualifies D0IX. */
|
||||||
list_for_each_entry(path, &adev->path_list, node) {
|
list_for_each_entry(path, &adev->path_list, node) {
|
||||||
struct avs_path_pipeline *ppl;
|
struct avs_path_pipeline *ppl;
|
||||||
@ -188,11 +189,14 @@ static bool apl_lp_streaming(struct avs_dev *adev)
|
|||||||
if (cfg->copier.dma_type == INVALID_OBJECT_ID)
|
if (cfg->copier.dma_type == INVALID_OBJECT_ID)
|
||||||
continue;
|
continue;
|
||||||
|
|
||||||
if (!mod->gtw_attrs.lp_buffer_alloc)
|
if (!mod->gtw_attrs.lp_buffer_alloc) {
|
||||||
|
spin_unlock(&adev->path_list_lock);
|
||||||
return false;
|
return false;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
spin_unlock(&adev->path_list_lock);
|
||||||
|
|
||||||
return true;
|
return true;
|
||||||
}
|
}
|
||||||
|
@ -283,8 +283,8 @@ void avs_release_firmwares(struct avs_dev *adev);
|
|||||||
|
|
||||||
int avs_dsp_init_module(struct avs_dev *adev, u16 module_id, u8 ppl_instance_id,
|
int avs_dsp_init_module(struct avs_dev *adev, u16 module_id, u8 ppl_instance_id,
|
||||||
u8 core_id, u8 domain, void *param, u32 param_size,
|
u8 core_id, u8 domain, void *param, u32 param_size,
|
||||||
u16 *instance_id);
|
u8 *instance_id);
|
||||||
void avs_dsp_delete_module(struct avs_dev *adev, u16 module_id, u16 instance_id,
|
void avs_dsp_delete_module(struct avs_dev *adev, u16 module_id, u8 instance_id,
|
||||||
u8 ppl_instance_id, u8 core_id);
|
u8 ppl_instance_id, u8 core_id);
|
||||||
int avs_dsp_create_pipeline(struct avs_dev *adev, u16 req_size, u8 priority,
|
int avs_dsp_create_pipeline(struct avs_dev *adev, u16 req_size, u8 priority,
|
||||||
bool lp, u16 attributes, u8 *instance_id);
|
bool lp, u16 attributes, u8 *instance_id);
|
||||||
|
@ -443,7 +443,7 @@ static int avs_register_i2s_boards(struct avs_dev *adev)
|
|||||||
}
|
}
|
||||||
|
|
||||||
for (mach = boards->machs; mach->id[0]; mach++) {
|
for (mach = boards->machs; mach->id[0]; mach++) {
|
||||||
if (!acpi_dev_present(mach->id, NULL, -1))
|
if (!acpi_dev_present(mach->id, mach->uid, -1))
|
||||||
continue;
|
continue;
|
||||||
|
|
||||||
if (mach->machine_quirk)
|
if (mach->machine_quirk)
|
||||||
|
@ -21,17 +21,25 @@ static struct avs_dev *avs_get_kcontrol_adev(struct snd_kcontrol *kcontrol)
|
|||||||
return to_avs_dev(w->dapm->component->dev);
|
return to_avs_dev(w->dapm->component->dev);
|
||||||
}
|
}
|
||||||
|
|
||||||
static struct avs_path_module *avs_get_kcontrol_module(struct avs_dev *adev, u32 id)
|
static struct avs_path_module *avs_get_volume_module(struct avs_dev *adev, u32 id)
|
||||||
{
|
{
|
||||||
struct avs_path *path;
|
struct avs_path *path;
|
||||||
struct avs_path_pipeline *ppl;
|
struct avs_path_pipeline *ppl;
|
||||||
struct avs_path_module *mod;
|
struct avs_path_module *mod;
|
||||||
|
|
||||||
list_for_each_entry(path, &adev->path_list, node)
|
spin_lock(&adev->path_list_lock);
|
||||||
list_for_each_entry(ppl, &path->ppl_list, node)
|
list_for_each_entry(path, &adev->path_list, node) {
|
||||||
list_for_each_entry(mod, &ppl->mod_list, node)
|
list_for_each_entry(ppl, &path->ppl_list, node) {
|
||||||
if (mod->template->ctl_id && mod->template->ctl_id == id)
|
list_for_each_entry(mod, &ppl->mod_list, node) {
|
||||||
|
if (guid_equal(&mod->template->cfg_ext->type, &AVS_PEAKVOL_MOD_UUID)
|
||||||
|
&& mod->template->ctl_id == id) {
|
||||||
|
spin_unlock(&adev->path_list_lock);
|
||||||
return mod;
|
return mod;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
spin_unlock(&adev->path_list_lock);
|
||||||
|
|
||||||
return NULL;
|
return NULL;
|
||||||
}
|
}
|
||||||
@ -49,7 +57,7 @@ int avs_control_volume_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_va
|
|||||||
/* prevent access to modules while path is being constructed */
|
/* prevent access to modules while path is being constructed */
|
||||||
mutex_lock(&adev->path_mutex);
|
mutex_lock(&adev->path_mutex);
|
||||||
|
|
||||||
active_module = avs_get_kcontrol_module(adev, ctl_data->id);
|
active_module = avs_get_volume_module(adev, ctl_data->id);
|
||||||
if (active_module) {
|
if (active_module) {
|
||||||
ret = avs_ipc_peakvol_get_volume(adev, active_module->module_id,
|
ret = avs_ipc_peakvol_get_volume(adev, active_module->module_id,
|
||||||
active_module->instance_id, &dspvols,
|
active_module->instance_id, &dspvols,
|
||||||
@ -89,7 +97,7 @@ int avs_control_volume_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_va
|
|||||||
changed = 1;
|
changed = 1;
|
||||||
}
|
}
|
||||||
|
|
||||||
active_module = avs_get_kcontrol_module(adev, ctl_data->id);
|
active_module = avs_get_volume_module(adev, ctl_data->id);
|
||||||
if (active_module) {
|
if (active_module) {
|
||||||
dspvol.channel_id = AVS_ALL_CHANNELS_MASK;
|
dspvol.channel_id = AVS_ALL_CHANNELS_MASK;
|
||||||
dspvol.target_volume = *volume;
|
dspvol.target_volume = *volume;
|
||||||
|
@ -225,7 +225,7 @@ err:
|
|||||||
|
|
||||||
int avs_dsp_init_module(struct avs_dev *adev, u16 module_id, u8 ppl_instance_id,
|
int avs_dsp_init_module(struct avs_dev *adev, u16 module_id, u8 ppl_instance_id,
|
||||||
u8 core_id, u8 domain, void *param, u32 param_size,
|
u8 core_id, u8 domain, void *param, u32 param_size,
|
||||||
u16 *instance_id)
|
u8 *instance_id)
|
||||||
{
|
{
|
||||||
struct avs_module_entry mentry;
|
struct avs_module_entry mentry;
|
||||||
bool was_loaded = false;
|
bool was_loaded = false;
|
||||||
@ -272,7 +272,7 @@ err_mod_entry:
|
|||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
||||||
void avs_dsp_delete_module(struct avs_dev *adev, u16 module_id, u16 instance_id,
|
void avs_dsp_delete_module(struct avs_dev *adev, u16 module_id, u8 instance_id,
|
||||||
u8 ppl_instance_id, u8 core_id)
|
u8 ppl_instance_id, u8 core_id)
|
||||||
{
|
{
|
||||||
struct avs_module_entry mentry;
|
struct avs_module_entry mentry;
|
||||||
|
@ -619,7 +619,7 @@ enum avs_channel_config {
|
|||||||
AVS_CHANNEL_CONFIG_DUAL_MONO = 9,
|
AVS_CHANNEL_CONFIG_DUAL_MONO = 9,
|
||||||
AVS_CHANNEL_CONFIG_I2S_DUAL_STEREO_0 = 10,
|
AVS_CHANNEL_CONFIG_I2S_DUAL_STEREO_0 = 10,
|
||||||
AVS_CHANNEL_CONFIG_I2S_DUAL_STEREO_1 = 11,
|
AVS_CHANNEL_CONFIG_I2S_DUAL_STEREO_1 = 11,
|
||||||
AVS_CHANNEL_CONFIG_4_CHANNEL = 12,
|
AVS_CHANNEL_CONFIG_7_1 = 12,
|
||||||
AVS_CHANNEL_CONFIG_INVALID
|
AVS_CHANNEL_CONFIG_INVALID
|
||||||
};
|
};
|
||||||
|
|
||||||
|
@ -37,7 +37,7 @@ struct avs_path_pipeline {
|
|||||||
|
|
||||||
struct avs_path_module {
|
struct avs_path_module {
|
||||||
u16 module_id;
|
u16 module_id;
|
||||||
u16 instance_id;
|
u8 instance_id;
|
||||||
union avs_gtw_attributes gtw_attrs;
|
union avs_gtw_attributes gtw_attrs;
|
||||||
|
|
||||||
struct avs_tplg_module *template;
|
struct avs_tplg_module *template;
|
||||||
|
@ -468,21 +468,34 @@ static int avs_dai_fe_startup(struct snd_pcm_substream *substream, struct snd_so
|
|||||||
|
|
||||||
host_stream = snd_hdac_ext_stream_assign(bus, substream, HDAC_EXT_STREAM_TYPE_HOST);
|
host_stream = snd_hdac_ext_stream_assign(bus, substream, HDAC_EXT_STREAM_TYPE_HOST);
|
||||||
if (!host_stream) {
|
if (!host_stream) {
|
||||||
kfree(data);
|
ret = -EBUSY;
|
||||||
return -EBUSY;
|
goto err;
|
||||||
}
|
}
|
||||||
|
|
||||||
data->host_stream = host_stream;
|
data->host_stream = host_stream;
|
||||||
snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
|
ret = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
|
||||||
|
if (ret < 0)
|
||||||
|
goto err;
|
||||||
|
|
||||||
/* avoid wrap-around with wall-clock */
|
/* avoid wrap-around with wall-clock */
|
||||||
snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME, 20, 178000000);
|
ret = snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME, 20, 178000000);
|
||||||
snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_rates);
|
if (ret < 0)
|
||||||
|
goto err;
|
||||||
|
|
||||||
|
ret = snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_rates);
|
||||||
|
if (ret < 0)
|
||||||
|
goto err;
|
||||||
|
|
||||||
snd_pcm_set_sync(substream);
|
snd_pcm_set_sync(substream);
|
||||||
|
|
||||||
dev_dbg(dai->dev, "%s fe STARTUP tag %d str %p",
|
dev_dbg(dai->dev, "%s fe STARTUP tag %d str %p",
|
||||||
__func__, hdac_stream(host_stream)->stream_tag, substream);
|
__func__, hdac_stream(host_stream)->stream_tag, substream);
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
|
|
||||||
|
err:
|
||||||
|
kfree(data);
|
||||||
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
||||||
static void avs_dai_fe_shutdown(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
|
static void avs_dai_fe_shutdown(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
|
||||||
|
@ -18,7 +18,7 @@ static int avs_dsp_init_probe(struct avs_dev *adev, union avs_connector_node_id
|
|||||||
{
|
{
|
||||||
struct avs_probe_cfg cfg = {{0}};
|
struct avs_probe_cfg cfg = {{0}};
|
||||||
struct avs_module_entry mentry;
|
struct avs_module_entry mentry;
|
||||||
u16 dummy;
|
u8 dummy;
|
||||||
|
|
||||||
avs_get_module_entry(adev, &AVS_PROBE_MOD_UUID, &mentry);
|
avs_get_module_entry(adev, &AVS_PROBE_MOD_UUID, &mentry);
|
||||||
|
|
||||||
|
@ -436,13 +436,6 @@ int mt8188_afe_init_clock(struct mtk_base_afe *afe)
|
|||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
void mt8188_afe_deinit_clock(void *priv)
|
|
||||||
{
|
|
||||||
struct mtk_base_afe *afe = priv;
|
|
||||||
|
|
||||||
mt8188_audsys_clk_unregister(afe);
|
|
||||||
}
|
|
||||||
|
|
||||||
int mt8188_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk)
|
int mt8188_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk)
|
||||||
{
|
{
|
||||||
int ret;
|
int ret;
|
||||||
|
@ -111,7 +111,6 @@ int mt8188_afe_get_default_mclk_source_by_rate(int rate);
|
|||||||
int mt8188_get_apll_by_rate(struct mtk_base_afe *afe, int rate);
|
int mt8188_get_apll_by_rate(struct mtk_base_afe *afe, int rate);
|
||||||
int mt8188_get_apll_by_name(struct mtk_base_afe *afe, const char *name);
|
int mt8188_get_apll_by_name(struct mtk_base_afe *afe, const char *name);
|
||||||
int mt8188_afe_init_clock(struct mtk_base_afe *afe);
|
int mt8188_afe_init_clock(struct mtk_base_afe *afe);
|
||||||
void mt8188_afe_deinit_clock(void *priv);
|
|
||||||
int mt8188_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk);
|
int mt8188_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk);
|
||||||
void mt8188_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk);
|
void mt8188_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk);
|
||||||
int mt8188_afe_set_clk_rate(struct mtk_base_afe *afe, struct clk *clk,
|
int mt8188_afe_set_clk_rate(struct mtk_base_afe *afe, struct clk *clk,
|
||||||
|
@ -3256,10 +3256,6 @@ static int mt8188_afe_pcm_dev_probe(struct platform_device *pdev)
|
|||||||
if (ret)
|
if (ret)
|
||||||
return dev_err_probe(dev, ret, "init clock error");
|
return dev_err_probe(dev, ret, "init clock error");
|
||||||
|
|
||||||
ret = devm_add_action_or_reset(dev, mt8188_afe_deinit_clock, (void *)afe);
|
|
||||||
if (ret)
|
|
||||||
return ret;
|
|
||||||
|
|
||||||
spin_lock_init(&afe_priv->afe_ctrl_lock);
|
spin_lock_init(&afe_priv->afe_ctrl_lock);
|
||||||
|
|
||||||
mutex_init(&afe->irq_alloc_lock);
|
mutex_init(&afe->irq_alloc_lock);
|
||||||
|
@ -138,6 +138,29 @@ static const struct afe_gate aud_clks[CLK_AUD_NR_CLK] = {
|
|||||||
GATE_AUD6(CLK_AUD_GASRC11, "aud_gasrc11", "top_asm_h", 11),
|
GATE_AUD6(CLK_AUD_GASRC11, "aud_gasrc11", "top_asm_h", 11),
|
||||||
};
|
};
|
||||||
|
|
||||||
|
static void mt8188_audsys_clk_unregister(void *data)
|
||||||
|
{
|
||||||
|
struct mtk_base_afe *afe = data;
|
||||||
|
struct mt8188_afe_private *afe_priv = afe->platform_priv;
|
||||||
|
struct clk *clk;
|
||||||
|
struct clk_lookup *cl;
|
||||||
|
int i;
|
||||||
|
|
||||||
|
if (!afe_priv)
|
||||||
|
return;
|
||||||
|
|
||||||
|
for (i = 0; i < CLK_AUD_NR_CLK; i++) {
|
||||||
|
cl = afe_priv->lookup[i];
|
||||||
|
if (!cl)
|
||||||
|
continue;
|
||||||
|
|
||||||
|
clk = cl->clk;
|
||||||
|
clk_unregister_gate(clk);
|
||||||
|
|
||||||
|
clkdev_drop(cl);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
int mt8188_audsys_clk_register(struct mtk_base_afe *afe)
|
int mt8188_audsys_clk_register(struct mtk_base_afe *afe)
|
||||||
{
|
{
|
||||||
struct mt8188_afe_private *afe_priv = afe->platform_priv;
|
struct mt8188_afe_private *afe_priv = afe->platform_priv;
|
||||||
@ -179,27 +202,5 @@ int mt8188_audsys_clk_register(struct mtk_base_afe *afe)
|
|||||||
afe_priv->lookup[i] = cl;
|
afe_priv->lookup[i] = cl;
|
||||||
}
|
}
|
||||||
|
|
||||||
return 0;
|
return devm_add_action_or_reset(afe->dev, mt8188_audsys_clk_unregister, afe);
|
||||||
}
|
|
||||||
|
|
||||||
void mt8188_audsys_clk_unregister(struct mtk_base_afe *afe)
|
|
||||||
{
|
|
||||||
struct mt8188_afe_private *afe_priv = afe->platform_priv;
|
|
||||||
struct clk *clk;
|
|
||||||
struct clk_lookup *cl;
|
|
||||||
int i;
|
|
||||||
|
|
||||||
if (!afe_priv)
|
|
||||||
return;
|
|
||||||
|
|
||||||
for (i = 0; i < CLK_AUD_NR_CLK; i++) {
|
|
||||||
cl = afe_priv->lookup[i];
|
|
||||||
if (!cl)
|
|
||||||
continue;
|
|
||||||
|
|
||||||
clk = cl->clk;
|
|
||||||
clk_unregister_gate(clk);
|
|
||||||
|
|
||||||
clkdev_drop(cl);
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
@ -10,6 +10,5 @@
|
|||||||
#define _MT8188_AUDSYS_CLK_H_
|
#define _MT8188_AUDSYS_CLK_H_
|
||||||
|
|
||||||
int mt8188_audsys_clk_register(struct mtk_base_afe *afe);
|
int mt8188_audsys_clk_register(struct mtk_base_afe *afe);
|
||||||
void mt8188_audsys_clk_unregister(struct mtk_base_afe *afe);
|
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
@ -410,11 +410,6 @@ int mt8195_afe_init_clock(struct mtk_base_afe *afe)
|
|||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
void mt8195_afe_deinit_clock(struct mtk_base_afe *afe)
|
|
||||||
{
|
|
||||||
mt8195_audsys_clk_unregister(afe);
|
|
||||||
}
|
|
||||||
|
|
||||||
int mt8195_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk)
|
int mt8195_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk)
|
||||||
{
|
{
|
||||||
int ret;
|
int ret;
|
||||||
|
@ -101,7 +101,6 @@ int mt8195_afe_get_mclk_source_clk_id(int sel);
|
|||||||
int mt8195_afe_get_mclk_source_rate(struct mtk_base_afe *afe, int apll);
|
int mt8195_afe_get_mclk_source_rate(struct mtk_base_afe *afe, int apll);
|
||||||
int mt8195_afe_get_default_mclk_source_by_rate(int rate);
|
int mt8195_afe_get_default_mclk_source_by_rate(int rate);
|
||||||
int mt8195_afe_init_clock(struct mtk_base_afe *afe);
|
int mt8195_afe_init_clock(struct mtk_base_afe *afe);
|
||||||
void mt8195_afe_deinit_clock(struct mtk_base_afe *afe);
|
|
||||||
int mt8195_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk);
|
int mt8195_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk);
|
||||||
void mt8195_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk);
|
void mt8195_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk);
|
||||||
int mt8195_afe_prepare_clk(struct mtk_base_afe *afe, struct clk *clk);
|
int mt8195_afe_prepare_clk(struct mtk_base_afe *afe, struct clk *clk);
|
||||||
|
@ -3224,15 +3224,11 @@ err_pm_put:
|
|||||||
|
|
||||||
static void mt8195_afe_pcm_dev_remove(struct platform_device *pdev)
|
static void mt8195_afe_pcm_dev_remove(struct platform_device *pdev)
|
||||||
{
|
{
|
||||||
struct mtk_base_afe *afe = platform_get_drvdata(pdev);
|
|
||||||
|
|
||||||
snd_soc_unregister_component(&pdev->dev);
|
snd_soc_unregister_component(&pdev->dev);
|
||||||
|
|
||||||
pm_runtime_disable(&pdev->dev);
|
pm_runtime_disable(&pdev->dev);
|
||||||
if (!pm_runtime_status_suspended(&pdev->dev))
|
if (!pm_runtime_status_suspended(&pdev->dev))
|
||||||
mt8195_afe_runtime_suspend(&pdev->dev);
|
mt8195_afe_runtime_suspend(&pdev->dev);
|
||||||
|
|
||||||
mt8195_afe_deinit_clock(afe);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static const struct of_device_id mt8195_afe_pcm_dt_match[] = {
|
static const struct of_device_id mt8195_afe_pcm_dt_match[] = {
|
||||||
|
@ -148,6 +148,29 @@ static const struct afe_gate aud_clks[CLK_AUD_NR_CLK] = {
|
|||||||
GATE_AUD6(CLK_AUD_GASRC19, "aud_gasrc19", "top_asm_h", 19),
|
GATE_AUD6(CLK_AUD_GASRC19, "aud_gasrc19", "top_asm_h", 19),
|
||||||
};
|
};
|
||||||
|
|
||||||
|
static void mt8195_audsys_clk_unregister(void *data)
|
||||||
|
{
|
||||||
|
struct mtk_base_afe *afe = data;
|
||||||
|
struct mt8195_afe_private *afe_priv = afe->platform_priv;
|
||||||
|
struct clk *clk;
|
||||||
|
struct clk_lookup *cl;
|
||||||
|
int i;
|
||||||
|
|
||||||
|
if (!afe_priv)
|
||||||
|
return;
|
||||||
|
|
||||||
|
for (i = 0; i < CLK_AUD_NR_CLK; i++) {
|
||||||
|
cl = afe_priv->lookup[i];
|
||||||
|
if (!cl)
|
||||||
|
continue;
|
||||||
|
|
||||||
|
clk = cl->clk;
|
||||||
|
clk_unregister_gate(clk);
|
||||||
|
|
||||||
|
clkdev_drop(cl);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
int mt8195_audsys_clk_register(struct mtk_base_afe *afe)
|
int mt8195_audsys_clk_register(struct mtk_base_afe *afe)
|
||||||
{
|
{
|
||||||
struct mt8195_afe_private *afe_priv = afe->platform_priv;
|
struct mt8195_afe_private *afe_priv = afe->platform_priv;
|
||||||
@ -188,27 +211,5 @@ int mt8195_audsys_clk_register(struct mtk_base_afe *afe)
|
|||||||
afe_priv->lookup[i] = cl;
|
afe_priv->lookup[i] = cl;
|
||||||
}
|
}
|
||||||
|
|
||||||
return 0;
|
return devm_add_action_or_reset(afe->dev, mt8195_audsys_clk_unregister, afe);
|
||||||
}
|
|
||||||
|
|
||||||
void mt8195_audsys_clk_unregister(struct mtk_base_afe *afe)
|
|
||||||
{
|
|
||||||
struct mt8195_afe_private *afe_priv = afe->platform_priv;
|
|
||||||
struct clk *clk;
|
|
||||||
struct clk_lookup *cl;
|
|
||||||
int i;
|
|
||||||
|
|
||||||
if (!afe_priv)
|
|
||||||
return;
|
|
||||||
|
|
||||||
for (i = 0; i < CLK_AUD_NR_CLK; i++) {
|
|
||||||
cl = afe_priv->lookup[i];
|
|
||||||
if (!cl)
|
|
||||||
continue;
|
|
||||||
|
|
||||||
clk = cl->clk;
|
|
||||||
clk_unregister_gate(clk);
|
|
||||||
|
|
||||||
clkdev_drop(cl);
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
@ -10,6 +10,5 @@
|
|||||||
#define _MT8195_AUDSYS_CLK_H_
|
#define _MT8195_AUDSYS_CLK_H_
|
||||||
|
|
||||||
int mt8195_audsys_clk_register(struct mtk_base_afe *afe);
|
int mt8195_audsys_clk_register(struct mtk_base_afe *afe);
|
||||||
void mt8195_audsys_clk_unregister(struct mtk_base_afe *afe);
|
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
@ -2431,6 +2431,9 @@ int dpcm_be_dai_prepare(struct snd_soc_pcm_runtime *fe, int stream)
|
|||||||
if (!snd_soc_dpcm_be_can_update(fe, be, stream))
|
if (!snd_soc_dpcm_be_can_update(fe, be, stream))
|
||||||
continue;
|
continue;
|
||||||
|
|
||||||
|
if (!snd_soc_dpcm_can_be_prepared(fe, be, stream))
|
||||||
|
continue;
|
||||||
|
|
||||||
if ((be->dpcm[stream].state != SND_SOC_DPCM_STATE_HW_PARAMS) &&
|
if ((be->dpcm[stream].state != SND_SOC_DPCM_STATE_HW_PARAMS) &&
|
||||||
(be->dpcm[stream].state != SND_SOC_DPCM_STATE_STOP) &&
|
(be->dpcm[stream].state != SND_SOC_DPCM_STATE_STOP) &&
|
||||||
(be->dpcm[stream].state != SND_SOC_DPCM_STATE_SUSPEND) &&
|
(be->dpcm[stream].state != SND_SOC_DPCM_STATE_SUSPEND) &&
|
||||||
@ -3087,3 +3090,20 @@ int snd_soc_dpcm_can_be_params(struct snd_soc_pcm_runtime *fe,
|
|||||||
return snd_soc_dpcm_check_state(fe, be, stream, state, ARRAY_SIZE(state));
|
return snd_soc_dpcm_check_state(fe, be, stream, state, ARRAY_SIZE(state));
|
||||||
}
|
}
|
||||||
EXPORT_SYMBOL_GPL(snd_soc_dpcm_can_be_params);
|
EXPORT_SYMBOL_GPL(snd_soc_dpcm_can_be_params);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* We can only prepare a BE DAI if any of it's FE are not prepared,
|
||||||
|
* running or paused for the specified stream direction.
|
||||||
|
*/
|
||||||
|
int snd_soc_dpcm_can_be_prepared(struct snd_soc_pcm_runtime *fe,
|
||||||
|
struct snd_soc_pcm_runtime *be, int stream)
|
||||||
|
{
|
||||||
|
const enum snd_soc_dpcm_state state[] = {
|
||||||
|
SND_SOC_DPCM_STATE_START,
|
||||||
|
SND_SOC_DPCM_STATE_PAUSED,
|
||||||
|
SND_SOC_DPCM_STATE_PREPARE,
|
||||||
|
};
|
||||||
|
|
||||||
|
return snd_soc_dpcm_check_state(fe, be, stream, state, ARRAY_SIZE(state));
|
||||||
|
}
|
||||||
|
EXPORT_SYMBOL_GPL(snd_soc_dpcm_can_be_prepared);
|
||||||
|
@ -117,6 +117,9 @@ int tegra_pcm_open(struct snd_soc_component *component,
|
|||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/* Set wait time to 500ms by default */
|
||||||
|
substream->wait_time = 500;
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
EXPORT_SYMBOL_GPL(tegra_pcm_open);
|
EXPORT_SYMBOL_GPL(tegra_pcm_open);
|
||||||
|
Loading…
x
Reference in New Issue
Block a user