[TG3]: Add 5787 nvram support
Support additional nvrams and new nvram format for 5787 and 5754. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Michael Chan
David S. Miller
parent
d9ab5ad12b
commit
1b27777a9b
@ -7816,29 +7816,53 @@ static void tg3_get_ethtool_stats (struct net_device *dev,
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}
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#define NVRAM_TEST_SIZE 0x100
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#define NVRAM_SELFBOOT_FORMAT1_SIZE 0x14
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static int tg3_test_nvram(struct tg3 *tp)
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{
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u32 *buf, csum;
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int i, j, err = 0;
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u32 *buf, csum, magic;
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int i, j, err = 0, size;
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buf = kmalloc(NVRAM_TEST_SIZE, GFP_KERNEL);
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if (tg3_nvram_read(tp, 0, &magic) != 0)
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return -EIO;
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magic = swab32(magic);
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if (magic == TG3_EEPROM_MAGIC)
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size = NVRAM_TEST_SIZE;
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else if ((magic & 0xff000000) == 0xa5000000) {
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if ((magic & 0xe00000) == 0x200000)
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size = NVRAM_SELFBOOT_FORMAT1_SIZE;
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else
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return 0;
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} else
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return -EIO;
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buf = kmalloc(size, GFP_KERNEL);
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if (buf == NULL)
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return -ENOMEM;
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for (i = 0, j = 0; i < NVRAM_TEST_SIZE; i += 4, j++) {
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err = -EIO;
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for (i = 0, j = 0; i < size; i += 4, j++) {
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u32 val;
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if ((err = tg3_nvram_read(tp, i, &val)) != 0)
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break;
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buf[j] = cpu_to_le32(val);
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}
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if (i < NVRAM_TEST_SIZE)
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if (i < size)
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goto out;
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err = -EIO;
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if (cpu_to_be32(buf[0]) != TG3_EEPROM_MAGIC)
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goto out;
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/* Selfboot format */
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if (cpu_to_be32(buf[0]) != TG3_EEPROM_MAGIC) {
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u8 *buf8 = (u8 *) buf, csum8 = 0;
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for (i = 0; i < size; i++)
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csum8 += buf8[i];
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if (csum8 == 0)
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return 0;
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return -EIO;
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}
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/* Bootstrap checksum at offset 0x10 */
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csum = calc_crc((unsigned char *) buf, 0x10);
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@ -8561,14 +8585,15 @@ static struct ethtool_ops tg3_ethtool_ops = {
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static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
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{
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u32 cursize, val;
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u32 cursize, val, magic;
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tp->nvram_size = EEPROM_CHIP_SIZE;
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if (tg3_nvram_read(tp, 0, &val) != 0)
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return;
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if (swab32(val) != TG3_EEPROM_MAGIC)
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magic = swab32(val);
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if ((magic != TG3_EEPROM_MAGIC) && ((magic & 0xff000000) != 0xa5000000))
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return;
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/*
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@ -8576,13 +8601,13 @@ static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
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* When we encounter our validation signature, we know the addressing
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* has wrapped around, and thus have our chip size.
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*/
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cursize = 0x800;
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cursize = 0x10;
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while (cursize < tp->nvram_size) {
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if (tg3_nvram_read(tp, cursize, &val) != 0)
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return;
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if (swab32(val) == TG3_EEPROM_MAGIC)
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if (swab32(val) == magic)
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break;
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cursize <<= 1;
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@ -8595,6 +8620,15 @@ static void __devinit tg3_get_nvram_size(struct tg3 *tp)
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{
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u32 val;
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if (tg3_nvram_read(tp, 0, &val) != 0)
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return;
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/* Selfboot format */
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if (swab32(val) != TG3_EEPROM_MAGIC) {
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tg3_get_eeprom_size(tp);
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return;
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}
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if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
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if (val != 0) {
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tp->nvram_size = (val >> 16) * 1024;
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@ -8718,6 +8752,44 @@ static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
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}
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}
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static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
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{
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u32 nvcfg1;
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nvcfg1 = tr32(NVRAM_CFG1);
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switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
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case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
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case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
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case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
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case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
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tp->nvram_jedecnum = JEDEC_ATMEL;
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tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
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tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
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nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
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tw32(NVRAM_CFG1, nvcfg1);
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break;
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case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
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case FLASH_5755VENDOR_ATMEL_FLASH_1:
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case FLASH_5755VENDOR_ATMEL_FLASH_2:
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case FLASH_5755VENDOR_ATMEL_FLASH_3:
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tp->nvram_jedecnum = JEDEC_ATMEL;
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tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
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tp->tg3_flags2 |= TG3_FLG2_FLASH;
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tp->nvram_pagesize = 264;
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break;
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case FLASH_5752VENDOR_ST_M45PE10:
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case FLASH_5752VENDOR_ST_M45PE20:
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case FLASH_5752VENDOR_ST_M45PE40:
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tp->nvram_jedecnum = JEDEC_ST;
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tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
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tp->tg3_flags2 |= TG3_FLG2_FLASH;
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tp->nvram_pagesize = 256;
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break;
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}
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}
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/* Chips other than 5700/5701 use the NVRAM for fetching info. */
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static void __devinit tg3_nvram_init(struct tg3 *tp)
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{
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@ -8753,6 +8825,8 @@ static void __devinit tg3_nvram_init(struct tg3 *tp)
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
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tg3_get_5752_nvram_info(tp);
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else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
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tg3_get_5787_nvram_info(tp);
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else
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tg3_get_nvram_info(tp);
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@ -9041,6 +9115,7 @@ static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
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nvram_cmd |= NVRAM_CMD_LAST;
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if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
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(GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) &&
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(tp->nvram_jedecnum == JEDEC_ST) &&
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(nvram_cmd & NVRAM_CMD_FIRST)) {
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@ -9444,6 +9519,7 @@ static void __devinit tg3_read_partno(struct tg3 *tp)
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{
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unsigned char vpd_data[256];
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int i;
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u32 magic;
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if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
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/* Sun decided not to put the necessary bits in the
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@ -9453,16 +9529,43 @@ static void __devinit tg3_read_partno(struct tg3 *tp)
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return;
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}
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for (i = 0; i < 256; i += 4) {
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u32 tmp;
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if (tg3_nvram_read(tp, 0x0, &magic))
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return;
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if (tg3_nvram_read(tp, 0x100 + i, &tmp))
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goto out_not_found;
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if (swab32(magic) == TG3_EEPROM_MAGIC) {
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for (i = 0; i < 256; i += 4) {
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u32 tmp;
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vpd_data[i + 0] = ((tmp >> 0) & 0xff);
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vpd_data[i + 1] = ((tmp >> 8) & 0xff);
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vpd_data[i + 2] = ((tmp >> 16) & 0xff);
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vpd_data[i + 3] = ((tmp >> 24) & 0xff);
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if (tg3_nvram_read(tp, 0x100 + i, &tmp))
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goto out_not_found;
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vpd_data[i + 0] = ((tmp >> 0) & 0xff);
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vpd_data[i + 1] = ((tmp >> 8) & 0xff);
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vpd_data[i + 2] = ((tmp >> 16) & 0xff);
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vpd_data[i + 3] = ((tmp >> 24) & 0xff);
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}
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} else {
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int vpd_cap;
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vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
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for (i = 0; i < 256; i += 4) {
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u32 tmp, j = 0;
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u16 tmp16;
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pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
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i);
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while (j++ < 100) {
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pci_read_config_word(tp->pdev, vpd_cap +
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PCI_VPD_ADDR, &tmp16);
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if (tmp16 & 0x8000)
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break;
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msleep(1);
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}
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pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
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&tmp);
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tmp = cpu_to_le32(tmp);
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memcpy(&vpd_data[i], &tmp, 4);
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}
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}
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/* Now parse and find the part number. */
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@ -1438,6 +1438,13 @@
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#define FLASH_5752VENDOR_ST_M45PE10 0x02400000
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#define FLASH_5752VENDOR_ST_M45PE20 0x02400002
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#define FLASH_5752VENDOR_ST_M45PE40 0x02400001
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#define FLASH_5755VENDOR_ATMEL_FLASH_1 0x03400001
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#define FLASH_5755VENDOR_ATMEL_FLASH_2 0x03400002
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#define FLASH_5755VENDOR_ATMEL_FLASH_3 0x03400000
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#define FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ 0x03000003
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#define FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ 0x03000002
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#define FLASH_5787VENDOR_MICRO_EEPROM_64KHZ 0x03000000
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#define FLASH_5787VENDOR_MICRO_EEPROM_376KHZ 0x02000000
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#define NVRAM_CFG1_5752PAGE_SIZE_MASK 0x70000000
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#define FLASH_5752PAGE_SIZE_256 0x00000000
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#define FLASH_5752PAGE_SIZE_512 0x10000000
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