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i.MX arm64 device tree changes for 6.7

Browse Source 
- New board support: TQ-Systems LS1043A/LS1046A and LS1088 based boards,
   VAR-SOM-MX6 SoM, SolidRun LX2162A SoM & Clearfog, and phyGATE-Tauri
   i.MX 8M Mini board.
 - A set of changes from Adam Ford adding audio related devices for i.MX8M
   SoCs, migrating sound card to simple-audio-card for imx8mm-beacon board,
   and adding DMIC support i.MX8M Beacon boards.
 - A series from Alexander Stein to add LVDS overlay support for i.MX8M
   based MBA8Mx boards.
 - A couple of changes from Cem Tenruh to add gpio-line-names for i.MX8MP
   based phycore boards.
 - A bunch of dt-schema check fixes from Fabio Estevam.
 - A few changes from Frank Li to add edma devices and enable UART
   support for i.MX93 and i.MX8 SoCs and related boards.
 - A series from Marek Vasut to improve various aspects of i.MX8MP based
   DHCOM boards support.
 - A series from Teresa Remmet to enable Flexcan, USB and RS232/RS485
   support for imx8mp-phyboard-pollux board.
 - A number of changes from Tim Harvey to add imx219 overlay and TPM
   device support for Gateworks boards.
 - Other small and random changes.
 -----BEGIN PGP SIGNATURE-----
 
 iQFIBAABCgAyFiEEFmJXigPl4LoGSz08UFdYWoewfM4FAmUr4vkUHHNoYXduZ3Vv
 QGtlcm5lbC5vcmcACgkQUFdYWoewfM7tGgf/VJGYHr/aD3jwIrRkrxy8iifuCPFD
 00sN6CwuiWjHkJxF9QEtbx7k+YCWVPhSDxiG1ttikjXOuzqoLWZ83B3YJPdwDHeZ
 8aZmoRT6QrGwcEUM0ULEmdi8yQNjosQ7nGGYHtqi4yCz3qNSFOZ/POfgMqDjOgI5
 pRTy5/NRkIT5Q2n7wP7IkrWYd+o3Mqc+TbToKRB+amXZabTVk/sJWqYzHnJjemK4
 ZUZJf6kABY5yIIcFXCfZMeQSn0aPGk/bAiNBcoyk6lu7lMvpHVTIYvWipGIkfv7Z
 isJs/0ZQV6wPP6pRHK/GvZf0pEZunRPttsiC76hajadjEscJ6RJEFu0LGQ==
 =HSVc
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmUtNW4ACgkQYKtH/8kJ
 UicaHRAAwNKos1jCle4m813GXWWHN6wmt68ogx5fqa4UFm/9ZlI8avn35tip9c6D
 K9tzeGWJcHHC0veCzndoWxbdsrdKwAZiMSr8aY9VHbqMe9hoa3d/h+mgw4WDv6dG
 CVvnFWQfu/+ysnDO0fwXGrqwken2x43cpiX9+/GmQn4obdzRcGYs2b8KdiiAGlG8
 AEslXP8O+K2LueGcf2TqbEfgflS3DhVMub0cJ0Z7Qa6d20P6P4iK5BXwBMp77AuK
 abmDu7vKKneGdB2iXDxlq7Wq5CZevhnUx2nC5yNtTnwnTbabm7aNCIugGelRA0l+
 jvMq7RtJkyvBZDCAW5dh0oSR4RGAzjvTWycpvPUZzAZTNXlibffkmG68jU5nq44k
 kwwdbl/OnPFFiD66aiD/yrte1tQ9ZFca7bBdhCeT2eX6UA/+rqFNt2HyLPJVi+co
 uUbEsB7i8mAiUqqhK3/1dMWZ4ljaJBCA/tzuVt8BhEyHsPyKaqxo0k3yeYRr6CJA
 qLqq6wZmVxDMjgmIprfG+ICPen2Mv5Rww45cT+Dc6w02brl6C+yQF+1zitEapsSw
 tuKRaZlhTvEMtpH2ZjiRq1AfQcTCs+DFfxbMezA6TXXSWPbmizWFe2NRFQg9qzty
 5FX1lk+wzE84TNX6QA+vdeEUXG0/SUY6f5xjwQGXF7z8jI6X//c=
 =2Mkd
 -----END PGP SIGNATURE-----

Merge tag 'imx-dt64-6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt

i.MX arm64 device tree changes for 6.7

- New board support: TQ-Systems LS1043A/LS1046A and LS1088 based boards,
  VAR-SOM-MX6 SoM, SolidRun LX2162A SoM & Clearfog, and phyGATE-Tauri
  i.MX 8M Mini board.
- A set of changes from Adam Ford adding audio related devices for i.MX8M
  SoCs, migrating sound card to simple-audio-card for imx8mm-beacon board,
  and adding DMIC support i.MX8M Beacon boards.
- A series from Alexander Stein to add LVDS overlay support for i.MX8M
  based MBA8Mx boards.
- A couple of changes from Cem Tenruh to add gpio-line-names for i.MX8MP
  based phycore boards.
- A bunch of dt-schema check fixes from Fabio Estevam.
- A few changes from Frank Li to add edma devices and enable UART
  support for i.MX93 and i.MX8 SoCs and related boards.
- A series from Marek Vasut to improve various aspects of i.MX8MP based
  DHCOM boards support.
- A series from Teresa Remmet to enable Flexcan, USB and RS232/RS485
  support for imx8mp-phyboard-pollux board.
- A number of changes from Tim Harvey to add imx219 overlay and TPM
  device support for Gateworks boards.
- Other small and random changes.

* tag 'imx-dt64-6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (101 commits)
  arm64: dts: imx8mp: Drop i.MX8MP DHCOM rev.100 PHY address workaround from PDK3 DT
  arm64: dts: imx8mp: Update i.MX8MP DHCOM SoM DT to production rev.200
  arm64: dts: imx8mp: Add UART1 and RTC wake up source on DH i.MX8M Plus DHCOM SoM
  arm64: dts: imx8mp: Switch WiFI enable signal to mmc-pwrseq-simple on i.MX8MP DHCOM SoM
  arm64: dts: imx8mp: Fix property indent on DH i.MX8M Plus DHCOM PDK3
  arm64: dts: imx8mp: Describe VDD_ARM run and standby voltage for DH i.MX8M Plus DHCOM SoM
  arm64: dts: imx8mp: Describe VDD_ARM run and standby voltage for Data Modul i.MX8M Plus eDM SBC
  arm64: dts: imx8mp-beacon: Add DMIC support
  arm64: dts: imx8mn-beacon: Add DMIC support
  arm64: dts: imx8mm-beacon: Add DMIC support
  arm64: dts: imx8mm-beacon: Migrate sound card to simple-audio-card
  arm64: dts: imx8mn-evk: Remove codec clocks/clock-names
  arm64: dts: imx8mp-beacon: Configure 100MHz PCIe Ref Clk
  arm64: dts: imx8mn: Add sound-dai-cells to micfil node
  arm64: dts: imx8mm: Add sound-dai-cells to micfil node
  arm64: dts: freescale: add initial device tree for TQMLS1088A
  arm64: dts: freescale: add initial device tree for TQMLS1043A/TQMLS1046A
  arm64: dts: ls1043a: remove second dspi node
  arm64: dts: freescale: Add support for LX2162 SoM & Clearfog Board
  arm64: dts: lx2160a: describe the SerDes block #2
  ...

Link: https://lore.kernel.org/r/20231015132300.2268016-3-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2023-10-16 15:06:53 +02:00
commit 1b42ff0c86
87 changed files with 3291 additions and 457 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
MAINTAINERS
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@ -21831,9 +21831,11 @@ W: https://www.tq-group.com/en/products/tq-embedded/
F: arch/arm/boot/dts/imx*mba*.dts*
F: arch/arm/boot/dts/imx*tqma*.dts*
F: arch/arm/boot/dts/mba*.dtsi
F: arch/arm64/boot/dts/freescale/fsl-*tqml*.dts*
F: arch/arm64/boot/dts/freescale/imx*mba*.dts*
F: arch/arm64/boot/dts/freescale/imx*tqma*.dts*
F: arch/arm64/boot/dts/freescale/mba*.dtsi
F: arch/arm64/boot/dts/freescale/tqml*.dts*
F: drivers/gpio/gpio-tqmx86.c
F: drivers/mfd/tqmx86.c
F: drivers/watchdog/tqmx86_wdt.c

20
arch/arm64/boot/dts/freescale/Makefile
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@ -15,12 +15,15 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-tqmls1043a-mbls10xxa.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-frwy.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-tqmls1046a-mbls10xxa.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-ten64.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-tqmls1088a-mbls10xxa.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2081a-rdb.dtb
@ -33,6 +36,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-clearfog-cx.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-honeycomb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2162a-clearfog.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2162a-qds.dtb
fsl-ls1028a-qds-13bb-dtbs := fsl-ls1028a-qds.dtb fsl-ls1028a-qds-13bb.dtbo
@ -66,6 +70,8 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-mx8menlo.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-nitrogen-r2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-phg.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-phyboard-polis-rdk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-phygate-tauri-l.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-prt8mm.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-tqma8mqml-mba8mx.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw71xx-0x.dtb
@ -82,6 +88,10 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-yavia.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dahlia.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-yavia.dtb
imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33-dtbs += imx8mm-tqma8mqml-mba8mx.dtb imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-beacon-kit.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-bsh-smm-s2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-bsh-smm-s2pro.dtb
@ -91,6 +101,10 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-tqma8mqnl-mba8mx.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-var-som-symphony.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-venice-gw7902.dtb
imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33-dtbs += imx8mn-tqma8mqnl-mba8mx.dtb imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-beacon-kit.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-data-modul-edm-sbc.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-debix-model-a.dtb
@ -132,6 +146,10 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mq-pico-pi.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-thor96.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-rmb3.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-zest.dtb
imx8mq-tqma8mq-mba8mx-lvds-tm070jvhg33-dtbs += imx8mq-tqma8mq-mba8mx.dtb imx8mq-tqma8mq-mba8mx-lvds-tm070jvhg33.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mq-tqma8mq-mba8mx-lvds-tm070jvhg33.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qm-apalis-eval.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qm-apalis-ixora-v1.1.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qm-apalis-v1.1-eval.dtb
@ -158,6 +176,7 @@ imx8mm-venice-gw73xx-0x-rpidsi-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice
imx8mm-venice-gw73xx-0x-rs232-rts-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-rs232-rts.dtbo
imx8mm-venice-gw73xx-0x-rs422-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-rs422.dtbo
imx8mm-venice-gw73xx-0x-rs485-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-rs485.dtbo
imx8mp-venice-gw74xx-imx219-dtbs := imx8mp-venice-gw74xx.dtb imx8mp-venice-gw74xx-imx219.dtbo
imx8mp-venice-gw74xx-rpidsi-dtbs := imx8mp-venice-gw74xx.dtb imx8mp-venice-gw74xx-rpidsi.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x-imx219.dtb
@ -170,6 +189,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-rpidsi.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-rs232-rts.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-rs422.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-rs485.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw74xx-imx219.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw74xx-rpidsi.dtb
dtb-$(CONFIG_ARCH_S32) += s32g274a-evb.dtb

49
arch/arm64/boot/dts/freescale/fsl-ls1043a-tqmls1043a-mbls10xxa.dts Normal file
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@ -0,0 +1,49 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (c) 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Gregor Herburger, Timo Herbrecher
*
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "fsl-ls1043a-tqmls1043a.dtsi"
#include "tqmls10xxa-mbls10xxa.dtsi"
/ {
model = "TQ-Systems GmbH LS1043A TQMLS1043A SoM on MBLS10xxA board";
compatible = "tq,ls1043a-tqmls1043a-mbls10xxa", "tq,ls1043a-tqmls1043a",
"fsl,ls1043a";
aliases {
qsgmii-s1-p1 = &qsgmii1_phy1;
qsgmii-s1-p2 = &qsgmii1_phy2;
qsgmii-s1-p3 = &qsgmii1_phy3;
qsgmii-s1-p4 = &qsgmii1_phy4;
qsgmii-s2-p1 = &qsgmii2_phy1;
qsgmii-s2-p2 = &qsgmii2_phy2;
qsgmii-s2-p3 = &qsgmii2_phy3;
qsgmii-s2-p4 = &qsgmii2_phy4;
serial0 = &duart0;
serial1 = &duart1;
};
chosen {
stdout-path = &duart1;
};
};
&esdhc {
cd-gpios = <&gpio3 2 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>;
};
&usb2 {
status = "okay";
};
#include "fsl-ls1043-post.dtsi"
#include "tqmls104xa-mbls10xxa-fman.dtsi"

32
arch/arm64/boot/dts/freescale/fsl-ls1043a-tqmls1043a.dtsi Normal file
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@ -0,0 +1,32 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (c) 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Gregor Herburger, Timo Herbrecher
*
* Device Tree Include file for LS1043A based SoM of TQ
*/
#include "fsl-ls1043a.dtsi"
#include "tqmls10xxa.dtsi"
&qspi {
num-cs = <2>;
status = "okay";
qflash0: flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <62500000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
};
};
};

14
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
View File

@ -526,20 +526,6 @@
status = "disabled";
};
dspi1: spi@2110000 {
compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2110000 0x0 0x10000>;
interrupts = <0 65 0x4>;
clock-names = "dspi";
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(1)>;
spi-num-chipselects = <5>;
big-endian;
status = "disabled";
};
i2c0: i2c@2180000 {
compatible = "fsl,ls1043a-i2c", "fsl,vf610-i2c";
#address-cells = <1>;

56
arch/arm64/boot/dts/freescale/fsl-ls1046a-tqmls1046a-mbls10xxa.dts Normal file
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@ -0,0 +1,56 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (c) 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Gregor Herburger, Timo Herbrecher
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "fsl-ls1046a-tqmls1046a.dtsi"
#include "tqmls10xxa-mbls10xxa.dtsi"
/ {
model = "TQ-Systems GmbH LS1046A TQMLS1046A SoM on MBLS10xxA board";
compatible = "tq,ls1046a-tqmls1046a-mbls10xxa", "tq,ls1046a-tqmls1046a",
"fsl,ls1046a";
aliases {
qsgmii-s1-p1 = &qsgmii1_phy1;
qsgmii-s1-p2 = &qsgmii1_phy2;
qsgmii-s1-p3 = &qsgmii1_phy3;
qsgmii-s1-p4 = &qsgmii1_phy4;
qsgmii-s2-p1 = &qsgmii2_phy1;
qsgmii-s2-p2 = &qsgmii2_phy2;
qsgmii-s2-p3 = &qsgmii2_phy3;
qsgmii-s2-p4 = &qsgmii2_phy4;
serial0 = &duart0;
serial1 = &duart1;
};
chosen {
stdout-path = &duart1;
};
};
&dspi {
status = "okay";
};
&esdhc {
cd-gpios = <&gpio3 2 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>;
};
&usb2 {
status = "okay";
};
#include "fsl-ls1046-post.dtsi"
#include "tqmls104xa-mbls10xxa-fman.dtsi"
&enet7 {
status = "disabled";
};

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arch/arm64/boot/dts/freescale/fsl-ls1046a-tqmls1046a.dtsi Normal file
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@ -0,0 +1,42 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (c) 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Gregor Herburger, Timo Herbrecher
*
* Device Tree Include file for LS1046A based SoM of TQ
*/
#include "fsl-ls1046a.dtsi"
#include "tqmls10xxa.dtsi"
&qspi {
num-cs = <2>;
status = "okay";
qflash0: flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <62500000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
};
};
qflash1: flash@1 {
compatible = "jedec,spi-nor";
reg = <1>;
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <62500000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
};
};

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@ -0,0 +1,64 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (c) 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Gregor Herburger, Timo Herbrecher
*
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "fsl-ls1088a-tqmls1088a.dtsi"
#include "tqmls10xxa-mbls10xxa.dtsi"
/ {
model = "TQ-Systems GmbH LS1088A TQMLS1088A SoM on MBLS10xxA board";
compatible = "tq,ls1088a-tqmls1088a-mbls10xxa", "tq,ls1088a-tqmls1088a",
"fsl,ls1088a";
aliases {
dpmac1 = &dpmac1;
dpmac2 = &dpmac2;
dpmac3 = &dpmac3;
dpmac4 = &dpmac4;
dpmac5 = &dpmac5;
dpmac6 = &dpmac6;
dpmac7 = &dpmac7;
dpmac8 = &dpmac8;
dpmac9 = &dpmac9;
dpmac10 = &dpmac10;
qsgmii-s1-p1 = &qsgmii1_phy1;
qsgmii-s1-p2 = &qsgmii1_phy2;
qsgmii-s1-p3 = &qsgmii1_phy3;
qsgmii-s1-p4 = &qsgmii1_phy4;
qsgmii-s2-p1 = &qsgmii2_phy1;
qsgmii-s2-p2 = &qsgmii2_phy2;
qsgmii-s2-p3 = &qsgmii2_phy3;
qsgmii-s2-p4 = &qsgmii2_phy4;
rgmii-s1 = &rgmii_phy1;
rgmii-s2 = &rgmii_phy2;
serial0 = &duart0;
serial1 = &duart1;
};
chosen {
stdout-path = &duart1;
};
};
&esdhc {
cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
};
&sfp1_i2c {
status = "okay";
};
&sfp2_i2c {
status = "okay";
};
#include "tqmls1088a-mbls10xxa-mc.dtsi"

42
arch/arm64/boot/dts/freescale/fsl-ls1088a-tqmls1088a.dtsi Normal file
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@ -0,0 +1,42 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (c) 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Gregor Herburger, Timo Herbrecher
*
* Device Tree Include file for LS1088A based SoM of TQ
*/
#include "fsl-ls1088a.dtsi"
#include "tqmls10xxa.dtsi"
&qspi {
num-cs = <2>;
status = "okay";
qflash0: flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <62500000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
};
};
qflash1: flash@1 {
compatible = "jedec,spi-nor";
reg = <1>;
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <62500000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
};
};

46
arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
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@ -1186,26 +1186,34 @@
dma-coherent;
};
usb0: usb@3100000 {
status = "disabled";
compatible = "snps,dwc3";
reg = <0x0 0x3100000 0x0 0x10000>;
interrupts = <0 80 0x4>; /* Level high type */
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
};
bus: bus {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
ranges;
dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x00000000>;
usb1: usb@3110000 {
status = "disabled";
compatible = "snps,dwc3";
reg = <0x0 0x3110000 0x0 0x10000>;
interrupts = <0 81 0x4>; /* Level high type */
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
usb0: usb@3100000 {
compatible = "snps,dwc3";
reg = <0x0 0x3100000 0x0 0x10000>;
interrupts = <0 80 0x4>; /* Level high type */
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
status = "disabled";
};
usb1: usb@3110000 {
compatible = "snps,dwc3";
reg = <0x0 0x3110000 0x0 0x10000>;
interrupts = <0 81 0x4>; /* Level high type */
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
status = "disabled";
};
};
ccn@4000000 {

7
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
View File

@ -626,6 +626,13 @@
#phy-cells = <1>;
};
serdes_2: phy@1eb0000 {
compatible = "fsl,lynx-28g";
reg = <0x0 0x1eb0000 0x0 0x1e30>;
#phy-cells = <1>;
status = "disabled";
};
crypto: crypto@8000000 {
compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
fsl,sec-era = <10>;

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arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts Normal file
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@ -0,0 +1,376 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Device Tree file for LX2162A Clearfog
//
// Copyright 2023 Josua Mayer <josua@solid-run.com>
/dts-v1/;
#include "fsl-lx2160a.dtsi"
#include "fsl-lx2162a-sr-som.dtsi"
/ {
model = "SolidRun LX2162A Clearfog";
compatible = "solidrun,lx2162a-clearfog", "solidrun,lx2162a-som", "fsl,lx2160a";
aliases {
crypto = &crypto;
i2c0 = &i2c0;
i2c1 = &i2c2;
i2c2 = &i2c4;
i2c3 = &sfp_i2c0;
i2c4 = &sfp_i2c1;
i2c5 = &sfp_i2c2;
i2c6 = &sfp_i2c3;
i2c7 = &mpcie1_i2c;
i2c8 = &mpcie0_i2c;
i2c9 = &pcieclk_i2c;
mmc0 = &esdhc0;
mmc1 = &esdhc1;
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
leds {
compatible = "gpio-leds";
led_sfp_at: led-sfp-at {
gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; /* PROC_IRQ5 */
default-state = "off";
};
led_sfp_ab: led-sfp-ab {
gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; /* PROC_IRQ11 */
default-state = "off";
};
led_sfp_bt: led-sfp-bt {
gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; /* EVT1_B */
default-state = "off";
};
led_sfp_bb: led-sfp-bb {
gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; /* EVT2_B */
default-state = "off";
};
};
sfp_at: sfp-at {
compatible = "sff,sfp";
i2c-bus = <&sfp_i2c0>;
mod-def0-gpios = <&gpio2 16 GPIO_ACTIVE_LOW>; /* EVT4_B */
maximum-power-milliwatt = <2000>;
};
sfp_ab: sfp-ab {
compatible = "sff,sfp";
i2c-bus = <&sfp_i2c1>;
mod-def0-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; /* PROC_IRQ1 */
maximum-power-milliwatt = <2000>;
};
sfp_bt: sfp-bt {
compatible = "sff,sfp";
i2c-bus = <&sfp_i2c2>;
mod-def0-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; /* PROC_IRQ10 */
maximum-power-milliwatt = <2000>;
};
sfp_bb: sfp-bb {
compatible = "sff,sfp";
i2c-bus = <&sfp_i2c3>;
mod-def0-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; /* EVT3_B */
maximum-power-milliwatt = <2000>;
};
};
&dpmac3 {
sfp = <&sfp_at>;
managed = "in-band-status";
phys = <&serdes_1 7>;
};
&dpmac4 {
sfp = <&sfp_ab>;
managed = "in-band-status";
phys = <&serdes_1 6>;
};
&dpmac5 {
sfp = <&sfp_bt>;
managed = "in-band-status";
phys = <&serdes_1 5>;
};
&dpmac6 {
sfp = <&sfp_bb>;
managed = "in-band-status";
phys = <&serdes_1 4>;
};
&dpmac11 {
phys = <&serdes_2 0>;
phy-handle = <&ethernet_phy3>;
phy-connection-type = "sgmii";
status = "okay";
};
&dpmac12 {
phys = <&serdes_2 1>;
phy-handle = <&ethernet_phy1>;
phy-connection-type = "sgmii";
status = "okay";
};
&dpmac13 {
phys = <&serdes_2 6>;
phy-handle = <&ethernet_phy6>;
phy-connection-type = "sgmii";
status = "okay";
};
&dpmac14 {
phys = <&serdes_2 7>;
phy-handle = <&ethernet_phy8>;
phy-connection-type = "sgmii";
status = "okay";
};
&dpmac15 {
phys = <&serdes_2 4>;
phy-handle = <&ethernet_phy4>;
phy-connection-type = "sgmii";
status = "okay";
};
&dpmac16 {
phys = <&serdes_2 5>;
phy-handle = <&ethernet_phy2>;
phy-connection-type = "sgmii";
status = "okay";
};
&dpmac17 {
/* override connection to on-SoM phy */
/delete-property/ phy-handle;
/delete-property/ phy-connection-type;
phys = <&serdes_2 2>;
phy-handle = <&ethernet_phy5>;
phy-connection-type = "sgmii";
status = "okay";
};
&dpmac18 {
phys = <&serdes_2 3>;
phy-handle = <&ethernet_phy7>;
phy-connection-type = "sgmii";
status = "okay";
};
&emdio1 {
ethernet_phy1: ethernet-phy@8 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <8>;
max-speed = <1000>;
};
ethernet_phy2: ethernet-phy@9 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <9>;
max-speed = <1000>;
};
ethernet_phy3: ethernet-phy@10 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <10>;
max-speed = <1000>;
};
ethernet_phy4: ethernet-phy@11 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <11>;
max-speed = <1000>;
};
ethernet_phy5: ethernet-phy@12 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <12>;
max-speed = <1000>;
};
ethernet_phy6: ethernet-phy@13 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <13>;
max-speed = <1000>;
};
ethernet_phy7: ethernet-phy@14 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <14>;
max-speed = <1000>;
};
ethernet_phy8: ethernet-phy@15 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <15>;
max-speed = <1000>;
};
};
&esdhc0 {
sd-uhs-sdr104;
sd-uhs-sdr50;
sd-uhs-sdr25;
sd-uhs-sdr12;
status = "okay";
};
&ethernet_phy0 {
/*
* SoM has a phy at address 1 connected to SoC Ethernet Controller 1.
* It competes for WRIOP MAC17, and no connector has been wired.
*/
status = "disabled";
};
&i2c2 {
status = "okay";
/* retimer@18 */
i2c-mux@70 {
compatible = "nxp,pca9546";
reg = <0x70>;
#address-cells = <1>;
#size-cells = <0>;
i2c-mux-idle-disconnect;
sfp_i2c0: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
sfp_i2c1: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
sfp_i2c2: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
sfp_i2c3: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
};
i2c-mux@71 {
compatible = "nxp,pca9546";
reg = <0x71>;
#address-cells = <1>;
#size-cells = <0>;
i2c-mux-idle-disconnect;
mpcie1_i2c: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
mpcie0_i2c: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
pcieclk_i2c: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
/* clock-controller@6b */
};
};
};
&pcie3 {
status = "disabled";
};
&pcie4 {
status = "disabled";
};
&pcs_mdio3 {
status = "okay";
};
&pcs_mdio4 {
status = "okay";
};
&pcs_mdio5 {
status = "okay";
};
&pcs_mdio6 {
status = "okay";
};
&pcs_mdio11 {
status = "okay";
};
&pcs_mdio12 {
status = "okay";
};
&pcs_mdio13 {
status = "okay";
};
&pcs_mdio14 {
status = "okay";
};
&pcs_mdio15 {
status = "okay";
};
&pcs_mdio16 {
status = "okay";
};
&pcs_mdio17 {
status = "okay";
};
&pcs_mdio18 {
status = "okay";
};
&serdes_1 {
status = "okay";
};
&serdes_2 {
status = "okay";
};
&uart0 {
status = "okay";
};
&usb0 {
status = "okay";
};

73
arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi Normal file
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@ -0,0 +1,73 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Device Tree file for LX2162A-SOM
//
// Copyright 2021 Rabeeh Khoury <rabeeh@solid-run.com>
// Copyright 2023 Josua Mayer <josua@solid-run.com>
&crypto {
status = "okay";
};
&dpmac17 {
phy-handle = <&ethernet_phy0>;
phy-connection-type = "rgmii-id";
};
&emdio1 {
status = "okay";
ethernet_phy0: ethernet-phy@1 {
reg = <1>;
};
};
&esdhc1 {
bus-width = <8>;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
status = "okay";
};
&fspi {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
m25p,fast-read;
spi-max-frequency = <50000000>;
/* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
spi-rx-bus-width = <8>;
spi-tx-bus-width = <1>;
};
};
&i2c0 {
status = "okay";
fan-controller@18 {
compatible = "ti,amc6821";
reg = <0x18>;
};
ddr_spd: eeprom@51 {
compatible = "st,24c02", "atmel,24c02";
reg = <0x51>;
read-only;
};
config_eeprom: eeprom@57 {
compatible = "st,24c02", "atmel,24c02";
reg = <0x57>;
};
};
&i2c4 {
status = "okay";
variable_eeprom: eeprom@54 {
compatible = "st,24c2048", "atmel,24c2048";
reg = <0x54>;
};
};

1
arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi
View File

@ -165,7 +165,6 @@
"gpio5-24", "UART24-FORCEOFF", "gpio5-26",
"LED-4-GREEN", "gpio5-28", "LED-4-RED", "gpio5-30",
"gpio5-31";
ngpios = <32>;
};
/* Apalis PWM3, MXM3 pin 6 */

1
arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.2.dtsi
View File

@ -212,7 +212,6 @@
"gpio5-24", "UART24-FORCEOFF", "gpio5-26",
"LED-4-GREEN", "gpio5-28", "LED-4-RED", "gpio5-30",
"gpio5-31";
ngpios = <32>;
};
/* Apalis PWM3, MXM3 pin 6 */

11
arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi
View File

@ -264,7 +264,7 @@
reset-assert-us = <2>;
reset-deassert-us = <2>;
reset-gpios = <&lsio_gpio1 11 GPIO_ACTIVE_LOW>;
reset-names = "phy-reset";
reset-names = "phy";
};
};
};
@ -503,15 +503,6 @@
"MXM3_185",
"MXM3_187";
/*
* Add GPIO2_20 as a wakeup source:
* Pin: 101 SC_P_SPI3_CS0 (MXM3_37/WAKE1_MICO)
* Type: 5 SC_PAD_WAKEUP_FALL_EDGE
* Line: 20
*/
pad-wakeup = <IMX8QM_SPI3_CS0 5 20>;
pad-wakeup-num = <1>;
pcie-wifi-hog {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie_wifi_refclk>;

98
arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi
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@ -7,17 +7,74 @@
#include <dt-bindings/clock/imx8-lpcg.h>
#include <dt-bindings/firmware/imx/rsrc.h>
audio_ipg_clk: clock-audio-ipg {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <120000000>;
clock-output-names = "audio_ipg_clk";
};
audio_subsys: bus@59000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x59000000 0x0 0x59000000 0x1000000>;
audio_ipg_clk: clock-audio-ipg {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <120000000>;
clock-output-names = "audio_ipg_clk";
edma0: dma-controller@591f0000 {
compatible = "fsl,imx8qm-edma";
reg = <0x591f0000 0x190000>;
#dma-cells = <3>;
shared-interrupt;
dma-channels = <24>;
dma-channel-mask = <0x5c0c00>;
interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, /* 0 asrc 0 */
<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, /* 1 */
<GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, /* 2 */
<GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, /* 3 */
<GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, /* 4 */
<GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, /* 5 */
<GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, /* 6 esai0 */
<GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, /* 7 */
<GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, /* 8 spdif0 */
<GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, /* 9 */
<GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 10 unused */
<GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 11 unused */
<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* 12 sai0 */
<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* 13 */
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, /* 14 sai1 */
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, /* 15 */
<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, /* 16 sai2 */
<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, /* 17 sai3 */
<GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 18 unused */
<GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 19 unused */
<GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 20 unused */
<GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>, /* 21 */
<GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 22 unused */
<GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>; /* 23 unused */
power-domains = <&pd IMX_SC_R_DMA_0_CH0>,
<&pd IMX_SC_R_DMA_0_CH1>,
<&pd IMX_SC_R_DMA_0_CH2>,
<&pd IMX_SC_R_DMA_0_CH3>,
<&pd IMX_SC_R_DMA_0_CH4>,
<&pd IMX_SC_R_DMA_0_CH5>,
<&pd IMX_SC_R_DMA_0_CH6>,
<&pd IMX_SC_R_DMA_0_CH7>,
<&pd IMX_SC_R_DMA_0_CH8>,
<&pd IMX_SC_R_DMA_0_CH9>,
<&pd IMX_SC_R_DMA_0_CH10>,
<&pd IMX_SC_R_DMA_0_CH11>,
<&pd IMX_SC_R_DMA_0_CH12>,
<&pd IMX_SC_R_DMA_0_CH13>,
<&pd IMX_SC_R_DMA_0_CH14>,
<&pd IMX_SC_R_DMA_0_CH15>,
<&pd IMX_SC_R_DMA_0_CH16>,
<&pd IMX_SC_R_DMA_0_CH17>,
<&pd IMX_SC_R_DMA_0_CH18>,
<&pd IMX_SC_R_DMA_0_CH19>,
<&pd IMX_SC_R_DMA_0_CH20>,
<&pd IMX_SC_R_DMA_0_CH21>,
<&pd IMX_SC_R_DMA_0_CH22>,
<&pd IMX_SC_R_DMA_0_CH23>;
};
dsp_lpcg: clock-controller@59580000 {
@ -65,4 +122,35 @@ audio_subsys: bus@59000000 {
memory-region = <&dsp_reserved>;
status = "disabled";
};
edma1: dma-controller@599f0000 {
compatible = "fsl,imx8qm-edma";
reg = <0x599f0000 0xc0000>;
#dma-cells = <3>;
shared-interrupt;
dma-channels = <11>;
dma-channel-mask = <0xc0>;
interrupts = <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, /* 0 asrc 1 */
<GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, /* 1 */
<GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, /* 2 */
<GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, /* 3 */
<GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, /* 4 */
<GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, /* 5 */
<GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 6 unused */
<GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 7 unused */
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, /* sai4 */
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; /* sai5 */
power-domains = <&pd IMX_SC_R_DMA_1_CH0>,
<&pd IMX_SC_R_DMA_1_CH1>,
<&pd IMX_SC_R_DMA_1_CH2>,
<&pd IMX_SC_R_DMA_1_CH3>,
<&pd IMX_SC_R_DMA_1_CH4>,
<&pd IMX_SC_R_DMA_1_CH5>,
<&pd IMX_SC_R_DMA_1_CH6>,
<&pd IMX_SC_R_DMA_1_CH7>,
<&pd IMX_SC_R_DMA_1_CH8>,
<&pd IMX_SC_R_DMA_1_CH9>,
<&pd IMX_SC_R_DMA_1_CH10>;
};
};

42
arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
View File

@ -7,33 +7,33 @@
#include <dt-bindings/clock/imx8-lpcg.h>
#include <dt-bindings/firmware/imx/rsrc.h>
conn_axi_clk: clock-conn-axi {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <333333333>;
clock-output-names = "conn_axi_clk";
};
conn_ahb_clk: clock-conn-ahb {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <166666666>;
clock-output-names = "conn_ahb_clk";
};
conn_ipg_clk: clock-conn-ipg {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <83333333>;
clock-output-names = "conn_ipg_clk";
};
conn_subsys: bus@5b000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x5b000000 0x0 0x5b000000 0x1000000>;
conn_axi_clk: clock-conn-axi {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <333333333>;
clock-output-names = "conn_axi_clk";
};
conn_ahb_clk: clock-conn-ahb {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <166666666>;
clock-output-names = "conn_ahb_clk";
};
conn_ipg_clk: clock-conn-ipg {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <83333333>;
clock-output-names = "conn_ipg_clk";
};
usbotg1: usb@5b0d0000 {
compatible = "fsl,imx7ulp-usb", "fsl,imx6ul-usb", "fsl,imx27-usb";
reg = <0x5b0d0000 0x200>;

117
arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
View File

@ -7,19 +7,19 @@
#include <dt-bindings/clock/imx8-lpcg.h>
#include <dt-bindings/firmware/imx/rsrc.h>
dma_ipg_clk: clock-dma-ipg {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <120000000>;
clock-output-names = "dma_ipg_clk";
};
dma_subsys: bus@5a000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x5a000000 0x0 0x5a000000 0x1000000>;
dma_ipg_clk: clock-dma-ipg {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <120000000>;
clock-output-names = "dma_ipg_clk";
};
lpspi0: spi@5a000000 {
compatible = "fsl,imx7ulp-spi";
reg = <0x5a000000 0x10000>;
@ -86,52 +86,135 @@ dma_subsys: bus@5a000000 {
lpuart0: serial@5a060000 {
reg = <0x5a060000 0x1000>;
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart0_lpcg IMX_LPCG_CLK_4>,
<&uart0_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "baud";
assigned-clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <80000000>;
power-domains = <&pd IMX_SC_R_UART_0>;
dma-names = "tx","rx";
dmas = <&edma2 9 0 0>, <&edma2 8 0 1>;
status = "disabled";
};
lpuart1: serial@5a070000 {
reg = <0x5a070000 0x1000>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart1_lpcg IMX_LPCG_CLK_4>,
<&uart1_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "baud";
assigned-clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <80000000>;
power-domains = <&pd IMX_SC_R_UART_1>;
dma-names = "tx","rx";
dmas = <&edma2 11 0 0>, <&edma2 10 0 1>;
status = "disabled";
};
lpuart2: serial@5a080000 {
reg = <0x5a080000 0x1000>;
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart2_lpcg IMX_LPCG_CLK_4>,
<&uart2_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "baud";
assigned-clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <80000000>;
power-domains = <&pd IMX_SC_R_UART_2>;
dma-names = "tx","rx";
dmas = <&edma2 13 0 0>, <&edma2 12 0 1>;
status = "disabled";
};
lpuart3: serial@5a090000 {
reg = <0x5a090000 0x1000>;
interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart3_lpcg IMX_LPCG_CLK_4>,
<&uart3_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "baud";
assigned-clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <80000000>;
power-domains = <&pd IMX_SC_R_UART_3>;
dma-names = "tx","rx";
dmas = <&edma2 15 0 0>, <&edma2 14 0 1>;
status = "disabled";
};
adma_pwm: pwm@5a190000 {
compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
reg = <0x5a190000 0x1000>;
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&adma_pwm_lpcg 1>,
<&adma_pwm_lpcg 0>;
clock-names = "ipg", "per";
assigned-clocks = <&clk IMX_SC_R_LCD_0_PWM_0 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>;
#pwm-cells = <2>;
power-domains = <&pd IMX_SC_R_LCD_0_PWM_0>;
};
edma2: dma-controller@5a1f0000 {
compatible = "fsl,imx8qm-edma";
reg = <0x5a1f0000 0x170000>;
#dma-cells = <3>;
dma-channels = <16>;
interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd IMX_SC_R_DMA_2_CH0>,
<&pd IMX_SC_R_DMA_2_CH1>,
<&pd IMX_SC_R_DMA_2_CH2>,
<&pd IMX_SC_R_DMA_2_CH3>,
<&pd IMX_SC_R_DMA_2_CH4>,
<&pd IMX_SC_R_DMA_2_CH5>,
<&pd IMX_SC_R_DMA_2_CH6>,
<&pd IMX_SC_R_DMA_2_CH7>,
<&pd IMX_SC_R_DMA_2_CH8>,
<&pd IMX_SC_R_DMA_2_CH9>,
<&pd IMX_SC_R_DMA_2_CH10>,
<&pd IMX_SC_R_DMA_2_CH11>,
<&pd IMX_SC_R_DMA_2_CH12>,
<&pd IMX_SC_R_DMA_2_CH13>,
<&pd IMX_SC_R_DMA_2_CH14>,
<&pd IMX_SC_R_DMA_2_CH15>;
};
edma3: dma-controller@5a9f0000 {
compatible = "fsl,imx8qm-edma";
reg = <0x5a9f0000 0x90000>;
#dma-cells = <3>;
dma-channels = <8>;
interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd IMX_SC_R_DMA_3_CH0>,
<&pd IMX_SC_R_DMA_3_CH1>,
<&pd IMX_SC_R_DMA_3_CH2>,
<&pd IMX_SC_R_DMA_3_CH3>,
<&pd IMX_SC_R_DMA_3_CH4>,
<&pd IMX_SC_R_DMA_3_CH5>,
<&pd IMX_SC_R_DMA_3_CH6>,
<&pd IMX_SC_R_DMA_3_CH7>;
};
spi0_lpcg: clock-controller@5a400000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5a400000 0x10000>;
@ -228,6 +311,18 @@ dma_subsys: bus@5a000000 {
power-domains = <&pd IMX_SC_R_UART_3>;
};
adma_pwm_lpcg: clock-controller@5a590000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5a590000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_LCD_0_PWM_0 IMX_SC_PM_CLK_PER>,
<&dma_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "adma_pwm_lpcg_clk",
"adma_pwm_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_LCD_0_PWM_0>;
};
i2c0: i2c@5a800000 {
reg = <0x5a800000 0x4000>;
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;

36
arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi
View File

@ -3,25 +3,22 @@
* Copyright 2019-2021 NXP
* Zhou Guoniu <guoniu.zhou@nxp.com>
*/
img_ipg_clk: clock-img-ipg {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
clock-output-names = "img_ipg_clk";
};
img_subsys: bus@58000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x58000000 0x0 0x58000000 0x1000000>;
img_ipg_clk: clock-img-ipg {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
clock-output-names = "img_ipg_clk";
};
jpegdec: jpegdec@58400000 {
reg = <0x58400000 0x00050000>;
interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>,
<&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>;
clock-names = "per", "ipg";
@ -29,18 +26,13 @@ img_subsys: bus@58000000 {
<&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>;
assigned-clock-rates = <200000000>, <200000000>;
power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>,
<&pd IMX_SC_R_MJPEG_DEC_S0>,
<&pd IMX_SC_R_MJPEG_DEC_S1>,
<&pd IMX_SC_R_MJPEG_DEC_S2>,
<&pd IMX_SC_R_MJPEG_DEC_S3>;
<&pd IMX_SC_R_MJPEG_DEC_S0>;
slot = <0>;
};
jpegenc: jpegenc@58450000 {
reg = <0x58450000 0x00050000>;
interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&img_jpeg_enc_lpcg IMX_LPCG_CLK_0>,
<&img_jpeg_enc_lpcg IMX_LPCG_CLK_4>;
clock-names = "per", "ipg";
@ -48,10 +40,8 @@ img_subsys: bus@58000000 {
<&img_jpeg_enc_lpcg IMX_LPCG_CLK_4>;
assigned-clock-rates = <200000000>, <200000000>;
power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>,
<&pd IMX_SC_R_MJPEG_ENC_S0>,
<&pd IMX_SC_R_MJPEG_ENC_S1>,
<&pd IMX_SC_R_MJPEG_ENC_S2>,
<&pd IMX_SC_R_MJPEG_ENC_S3>;
<&pd IMX_SC_R_MJPEG_ENC_S0>;
slot = <0>;
};
img_jpeg_dec_lpcg: clock-controller@585d0000 {

25
arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
View File

@ -7,6 +7,13 @@
#include <dt-bindings/clock/imx8-lpcg.h>
#include <dt-bindings/firmware/imx/rsrc.h>
lsio_bus_clk: clock-lsio-bus {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-output-names = "lsio_bus_clk";
};
lsio_subsys: bus@5d000000 {
compatible = "simple-bus";
#address-cells = <1>;
@ -14,20 +21,6 @@ lsio_subsys: bus@5d000000 {
ranges = <0x5d000000 0x0 0x5d000000 0x1000000>,
<0x08000000 0x0 0x08000000 0x10000000>;
lsio_mem_clk: clock-lsio-mem {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
clock-output-names = "lsio_mem_clk";
};
lsio_bus_clk: clock-lsio-bus {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-output-names = "lsio_bus_clk";
};
lsio_pwm0: pwm@5d000000 {
compatible = "fsl,imx27-pwm";
reg = <0x5d000000 0x10000>;
@ -37,6 +30,7 @@ lsio_subsys: bus@5d000000 {
assigned-clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>;
#pwm-cells = <2>;
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@ -49,6 +43,7 @@ lsio_subsys: bus@5d000000 {
assigned-clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>;
#pwm-cells = <2>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@ -61,6 +56,7 @@ lsio_subsys: bus@5d000000 {
assigned-clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>;
#pwm-cells = <2>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@ -73,6 +69,7 @@ lsio_subsys: bus@5d000000 {
assigned-clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>;
#pwm-cells = <2>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};

2
arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
View File

@ -186,7 +186,6 @@
&flexspi0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexspi0>;
nxp,fspi-dll-slvdly = <4>;
status = "okay";
mt35xu512aba0: flash@0 {
@ -365,7 +364,6 @@
fsl,spi-only-use-cs1-sel;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpspi3>;
pinctrl-assert-gpios = <&pca6416_1 7 GPIO_ACTIVE_HIGH>;
status = "okay";
spidev0: spi@0 {

38
arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
View File

@ -15,23 +15,53 @@
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
};
&edma2 {
interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>;
};
&edma3 {
interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>;
};
&i2c0 {
compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
compatible = "fsl,imx8dxl-lpi2c", "fsl,imx7ulp-lpi2c";
interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
};
&i2c1 {
compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
compatible = "fsl,imx8dxl-lpi2c", "fsl,imx7ulp-lpi2c";
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
};
&i2c2 {
compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
compatible = "fsl,imx8dxl-lpi2c", "fsl,imx7ulp-lpi2c";
interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
};
&i2c3 {
compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
compatible = "fsl,imx8dxl-lpi2c", "fsl,imx7ulp-lpi2c";
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
};

6
arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi
View File

@ -6,14 +6,16 @@
/delete-node/ &enet1_lpcg;
/delete-node/ &fec2;
&conn_subsys {
/ {
conn_enet0_root_clk: clock-conn-enet0-root {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <250000000>;
clock-output-names = "conn_enet0_root_clk";
};
};
&conn_subsys {
eqos: ethernet@5b050000 {
compatible = "nxp,imx8dxl-dwmac-eqos", "snps,dwmac-5.10a";
reg = <0x5b050000 0x10000>;
@ -116,7 +118,7 @@
};
&fec1 {
compatible = "fsl,imx8qm-fec";
compatible = "fsl,imx8dxl-fec", "fsl,imx8qm-fec", "fsl,imx6sx-fec";
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,

8
arch/arm64/boot/dts/freescale/imx8dxl.dtsi
View File

@ -122,10 +122,8 @@
&lsio_mu1 3 3>;
pd: power-controller {
compatible = "fsl,scu-pd";
compatible = "fsl,imx8dl-scu-pd", "fsl,scu-pd";
#power-domain-cells = <1>;
wakeup-irq = <160 163 235 236 237 228 229 230 231 238
239 240 166 169>;
};
clk: clock-controller {
@ -168,12 +166,12 @@
};
watchdog {
compatible = "fsl,imx-sc-wdt";
compatible = "fsl,imx8dxl-sc-wdt", "fsl,imx-sc-wdt";
timeout-sec = <60>;
};
tsens: thermal-sensor {
compatible = "fsl,imx-sc-thermal";
compatible = "fsl,imx8dxl-sc-thermal", "fsl,imx-sc-thermal";
#thermal-sensor-cells = <1>;
};
};

76
arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi
View File

@ -6,6 +6,13 @@
#include <dt-bindings/phy/phy-imx8-pcie.h>
/ {
dmic_codec: dmic-codec {
compatible = "dmic-codec";
num-channels = <1>;
#sound-dai-cells = <0>;
};
leds {
compatible = "gpio-leds";
@ -98,18 +105,46 @@
enable-active-high;
};
sound {
compatible = "fsl,imx-audio-wm8962";
model = "wm8962-audio";
audio-cpu = <&sai3>;
audio-codec = <&wm8962>;
audio-routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
"Ext Spk", "SPKOUTL",
"Ext Spk", "SPKOUTR",
"AMIC", "MICBIAS",
"IN3R", "AMIC";
sound-dmic {
compatible = "simple-audio-card";
simple-audio-card,name = "dmic";
simple-audio-card,format = "pdm";
simple-audio-card,bitclock-master = <&dailink_master>;
simple-audio-card,frame-master = <&dailink_master>;
dailink_master: simple-audio-card,cpu {
sound-dai = <&micfil>;
};
simple-audio-card,codec {
sound-dai = <&dmic_codec>;
};
};
sound-wm8962 {
compatible = "simple-audio-card";
simple-audio-card,name = "wm8962";
simple-audio-card,format = "i2s";
simple-audio-card,widgets = "Headphone", "Headphones",
"Microphone", "Headset Mic",
"Speaker", "Speaker";
simple-audio-card,routing = "Headphones", "HPOUTL",
"Headphones", "HPOUTR",
"Speaker", "SPKOUTL",
"Speaker", "SPKOUTR",
"Headset Mic", "MICBIAS",
"IN3R", "Headset Mic";
simple-audio-card,cpu {
sound-dai = <&sai3>;
};
simple-audio-card,codec {
sound-dai = <&wm8962>;
clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
frame-master;
bitclock-master;
};
};
};
@ -192,6 +227,7 @@
0x0000 /* 4:FN_DMICCDAT */
0x0000 /* 5:Default */
>;
#sound-dai-cells = <0>;
};
pca6416_0: gpio@20 {
@ -215,6 +251,15 @@
};
};
&micfil {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pdm>;
assigned-clocks = <&clk IMX8MM_CLK_PDM>;
assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
assigned-clock-rates = <49152000>;
status = "okay";
};
&mipi_csi {
status = "okay";
ports {
@ -352,6 +397,13 @@
>;
};
pinctrl_pdm: pdmgrp {
fsl,pins = <
MX8MM_IOMUXC_SAI5_RXC_PDM_CLK 0xd6
MX8MM_IOMUXC_SAI5_RXD0_PDM_DATA0 0xd6
>;
};
pinctrl_reg_usb_otg1: usbotg1grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19

1
arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts
View File

@ -23,7 +23,6 @@
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
status = "okay";
};

32
arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
View File

@ -26,7 +26,7 @@
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&adv7533_out>;
remote-endpoint = <&adv7535_out>;
};
};
};
@ -72,6 +72,13 @@
enable-active-high;
};
reg_vddext_3v3: regulator-vddext-3v3 {
compatible = "regulator-fixed";
regulator-name = "VDDEXT_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm1 0 5000000 0>;
@ -317,15 +324,16 @@
hdmi@3d {
compatible = "adi,adv7535";
reg = <0x3d>, <0x3c>, <0x3e>, <0x3f>;
reg-names = "main", "cec", "edid", "packet";
reg = <0x3d>;
interrupt-parent = <&gpio1>;
interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
adi,dsi-lanes = <4>;
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
adi,input-style = <1>;
adi,input-justification = "evenly";
avdd-supply = <&buck5_reg>;
dvdd-supply = <&buck5_reg>;
pvdd-supply = <&buck5_reg>;
a2vdd-supply = <&buck5_reg>;
v3p3-supply = <&reg_vddext_3v3>;
v1p2-supply = <&buck5_reg>;
ports {
#address-cells = <1>;
@ -334,7 +342,7 @@
port@0 {
reg = <0>;
adv7533_in: endpoint {
adv7535_in: endpoint {
remote-endpoint = <&dsi_out>;
};
};
@ -342,7 +350,7 @@
port@1 {
reg = <1>;
adv7533_out: endpoint {
adv7535_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
@ -448,7 +456,7 @@
reg = <1>;
dsi_out: endpoint {
remote-endpoint = <&adv7533_in>;
remote-endpoint = <&adv7535_in>;
data-lanes = <1 2 3 4>;
};
};

5
arch/arm64/boot/dts/freescale/imx8mm-phg.dts
View File

@ -111,6 +111,11 @@
};
};
/* QSPI is not populated on the SoM */
&flexspi {
status = "disabled";
};
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;

489
arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts Normal file
View File

@ -0,0 +1,489 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2023 PHYTEC Messtechnik GmbH
*/
/dts-v1/;
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/leds/common.h>
#include "imx8mm-phycore-som.dtsi"
/ {
model = "PHYTEC phyGATE-Tauri-L-iMX8MM";
compatible = "phytec,imx8mm-phygate-tauri-l",
"phytec,imx8mm-phycore-som", "fsl,imx8mm";
chosen {
stdout-path = &uart3;
};
can_osc_40m: clock-can {
compatible = "fixed-clock";
clock-frequency = <40000000>;
clock-output-names = "can_osc_40m";
#clock-cells = <0>;
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpiokeys>;
key {
gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
label = "KEY-A";
linux,code = <KEY_A>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_leds>;
led-1 {
color = <LED_COLOR_ID_RED>;
gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "none";
};
led-2 {
color = <LED_COLOR_ID_YELLOW>;
gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "none";
};
};
usdhc1_pwrseq: pwr-seq {
compatible = "mmc-pwrseq-simple";
post-power-on-delay-ms = <100>;
power-off-delay-us = <60>;
reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
};
reg_usb_hub_vbus: regulator-hub-otg1 {
compatible = "regulator-fixed";
gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbhubpwr>;
regulator-name = "usb_hub_vbus";
regulator-max-microvolt = <5000000>;
regulator-min-microvolt = <5000000>;
};
reg_usb_otg1_vbus: regulator-usb-otg1 {
compatible = "regulator-fixed";
gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1pwr>;
regulator-name = "usb_otg1_vbus";
regulator-max-microvolt = <5000000>;
regulator-min-microvolt = <5000000>;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
off-on-delay-us = <20000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "VSD_3V3";
};
};
&ecspi1 {
cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>,
<&gpio5 13 GPIO_ACTIVE_LOW>,
<&gpio5 2 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
/* CAN MCP251XFD */
can0: can@0 {
compatible = "microchip,mcp251xfd";
reg = <0>;
clocks = <&can_osc_40m>;
interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&gpio1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can_int>;
spi-max-frequency = <10000000>;
};
tpm: tpm@1 {
compatible = "tcg,tpm_tis-spi";
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&gpio2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tpm>;
reg = <1>;
spi-max-frequency = <38000000>;
};
};
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
temp_sense0: temperature-sensor@49 {
compatible = "ti,tmp102";
reg = <0x49>;
interrupt-parent = <&gpio4>;
interrupts = <31 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tempsense>;
#thermal-sensor-cells = <1>;
};
};
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-1 = <&pinctrl_i2c3_gpio>;
scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
&i2c4 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
pinctrl-1 = <&pinctrl_i2c4_gpio>;
scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
/* PCIe */
&pcie0 {
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
<&clk IMX8MM_CLK_PCIE1_PHY>,
<&clk IMX8MM_CLK_PCIE1_CTRL>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
<&clk IMX8MM_SYS_PLL2_100M>,
<&clk IMX8MM_SYS_PLL2_250M>;
assigned-clock-rates = <10000000>, <100000000>, <250000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio3 22 GPIO_ACTIVE_LOW>;
status = "okay";
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
};
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
};
/* RTC */
&rv3028 {
trickle-resistor-ohms = <3000>;
};
&uart1 {
assigned-clocks = <&clk IMX8MM_CLK_UART1>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
/* UART2 - RS232 */
&uart2 {
assigned-clocks = <&clk IMX8MM_CLK_UART2>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
/* UART - console */
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
/* USB */
&usbotg1 {
adp-disable;
dr_mode = "otg";
over-current-active-low;
samsung,picophy-pre-emp-curr-control = <3>;
samsung,picophy-dc-vol-level-adjust = <7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1>;
srp-disable;
vbus-supply = <&reg_usb_otg1_vbus>;
status = "okay";
};
&usbotg2 {
disable-over-current;
dr_mode = "host";
samsung,picophy-pre-emp-curr-control = <3>;
samsung,picophy-dc-vol-level-adjust = <7>;
vbus-supply = <&reg_usb_hub_vbus>;
status = "okay";
};
/* SD-Card */
&usdhc2 {
assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
assigned-clock-rates = <200000000>;
bus-width = <4>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
disable-wp;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
vmmc-supply = <&reg_usdhc2_vmmc>;
vqmmc-supply = <&reg_nvcc_sd2>;
status = "okay";
};
&iomuxc {
pinctrl_can_int: can-intgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x00
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
>;
};
pinctrl_ecspi1_cs: ecspi1csgrp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x00
MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x00
MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x00
>;
};
pinctrl_gpiokeys: keygrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x00
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c2
MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c2
>;
};
pinctrl_i2c2_gpio: i2c2gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1e0
MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1e0
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c2
MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c2
>;
};
pinctrl_i2c3_gpio: i2c3gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1e0
MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1e0
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c2
MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c2
>;
};
pinctrl_i2c4_gpio: i2c4gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x1e0
MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x1e0
>;
};
pinctrl_leds: leds1grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x00
MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x00
>;
};
pinctrl_pcie: pciegrp {
fsl,pins = <
/* COEX2 */
MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x00
/* COEX1 */
MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x12
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x40
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x40
>;
};
pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO15_PWM4_OUT 0x40
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x40
>;
};
pinctrl_tempsense: tempsensegrp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x00
>;
};
pinctrl_tpm: tpmgrp {
fsl,pins = <
MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x140
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x00
MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x00
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x00
MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x00
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
>;
};
pinctrl_usbhubpwr: usbhubpwrgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x00
>;
};
pinctrl_usbotg1pwr: usbotg1pwrgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x00
>;
};
pinctrl_usbotg1: usbotg1grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x80
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x182
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0xc6
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc6
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc6
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc6
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc6
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x40
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x192
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d2
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d2
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d2
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d2
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d2
>;
};
pinctrl_usdhc2_100mhz: usdhc2100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
>;
};
pinctrl_usdhc2_200mhz: usdhc2200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
>;
};
};

45
arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33.dtso Normal file
View File

@ -0,0 +1,45 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (c) 2022-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Alexander Stein
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
&{/} {
compatible = "tq,imx8mm-tqma8mqml-mba8mx", "tq,imx8mm-tqma8mqml", "fsl,imx8mm";
};
&backlight_lvds {
status = "okay";
};
&dsi_lvds_bridge {
status = "okay";
};
&expander0 {
dsi-mux-oe-hog {
gpio-hog;
gpios = <10 GPIO_ACTIVE_LOW>;
output-high;
line-name = "DSI_MUX_OE#";
};
};
&lcdif {
status = "okay";
};
&mipi_dsi {
status = "okay";
};
&panel {
compatible = "tianma,tm070jvhg33";
status = "okay";
};

5
arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi
View File

@ -230,6 +230,11 @@
};
};
&mipi_dsi {
vddcore-supply = <&ldo4_reg>;
vddio-supply = <&ldo3_reg>;
};
&pcie_phy {
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
fsl,clkreq-unsupported;

1
arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi
View File

@ -96,7 +96,6 @@
st,drdy-int-pin = <1>;
interrupt-parent = <&gpio4>;
interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "INT1";
};
};

1
arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi
View File

@ -118,7 +118,6 @@
st,drdy-int-pin = <1>;
interrupt-parent = <&gpio4>;
interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "INT1";
};
};

11
arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi
View File

@ -104,8 +104,15 @@
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi2>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>,
<&gpio1 10 GPIO_ACTIVE_LOW>;
status = "okay";
tpm@1 {
compatible = "tcg,tpm_tis-spi";
reg = <0x1>;
spi-max-frequency = <36000000>;
};
};
&gpio1 {
@ -138,7 +145,6 @@
st,drdy-int-pin = <1>;
interrupt-parent = <&gpio4>;
interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "INT1";
};
};
@ -362,6 +368,7 @@
MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6
MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6
MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6
MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xd6
>;
};

4
arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
View File

@ -357,6 +357,8 @@
interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
adc {
compatible = "gw,gsc-adc";
@ -642,7 +644,6 @@
pinctrl-0 = <&pinctrl_ksz>;
interrupt-parent = <&gpio4>;
interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
phy-mode = "rgmii-id";
ports {
#address-cells = <1>;
@ -678,7 +679,6 @@
port@5 {
reg = <5>;
label = "cpu";
ethernet = <&fec1>;
phy-mode = "rgmii-id";

3
arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts
View File

@ -314,6 +314,8 @@
interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
adc {
compatible = "gw,gsc-adc";
@ -585,7 +587,6 @@
st,drdy-int-pin = <1>;
interrupt-parent = <&gpio1>;
interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "INT1";
};
};

3
arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts
View File

@ -280,6 +280,8 @@
interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
adc {
compatible = "gw,gsc-adc";
@ -541,7 +543,6 @@
st,drdy-int-pin = <1>;
interrupt-parent = <&gpio1>;
interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "INT1";
};
};

3
arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts
View File

@ -330,6 +330,8 @@
interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
adc {
compatible = "gw,gsc-adc";
@ -585,7 +587,6 @@
st,drdy-int-pin = <1>;
interrupt-parent = <&gpio1>;
interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "INT1";
};
};

1
arch/arm64/boot/dts/freescale/imx8mm.dtsi
View File

@ -399,6 +399,7 @@
"pll8k", "pll11k", "clkext3";
dmas = <&sdma2 24 25 0x80000000>;
dma-names = "rx";
#sound-dai-cells = <0>;
status = "disabled";
};

38
arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi
View File

@ -4,6 +4,12 @@
*/
/ {
dmic_codec: dmic-codec {
compatible = "dmic-codec";
num-channels = <1>;
#sound-dai-cells = <0>;
};
leds {
compatible = "gpio-leds";
@ -74,6 +80,22 @@
enable-active-high;
};
sound-dmic {
compatible = "simple-audio-card";
simple-audio-card,name = "dmic";
simple-audio-card,format = "pdm";
simple-audio-card,bitclock-master = <&dailink_master>;
simple-audio-card,frame-master = <&dailink_master>;
dailink_master: simple-audio-card,cpu {
sound-dai = <&micfil>;
};
simple-audio-card,codec {
sound-dai = <&dmic_codec>;
};
};
sound-wm8962 {
compatible = "simple-audio-card";
simple-audio-card,name = "wm8962";
@ -221,6 +243,15 @@
};
};
&micfil {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pdm>;
assigned-clocks = <&clk IMX8MN_CLK_PDM>;
assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
assigned-clock-rates = <49152000>;
status = "okay";
};
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
@ -311,6 +342,13 @@
>;
};
pinctrl_pdm: pdmgrp {
fsl,pins = <
MX8MN_IOMUXC_SAI5_RXC_PDM_CLK 0xd6
MX8MN_IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0xd6
>;
};
pinctrl_reg_usb_otg: reg-otggrp {
fsl,pins = <
MX8MN_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19

1
arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2.dts
View File

@ -21,7 +21,6 @@
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
status = "okay";
};

2
arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
View File

@ -71,8 +71,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_wlf>;
wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MN_CLK_SAI3_ROOT>;
clock-names = "mclk";
};
sound-bt-sco {

45
arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33.dtso Normal file
View File

@ -0,0 +1,45 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (c) 2022-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Alexander Stein
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
&{/} {
compatible = "tq,imx8mn-tqma8mqnl-mba8mx", "tq,imx8mn-tqma8mqnl", "fsl,imx8mn";
};
&backlight_lvds {
status = "okay";
};
&dsi_lvds_bridge {
status = "okay";
};
&expander0 {
dsi-mux-oe-hog {
gpio-hog;
gpios = <10 GPIO_ACTIVE_LOW>;
output-high;
line-name = "DSI_MUX_OE#";
};
};
&lcdif {
status = "okay";
};
&mipi_dsi {
status = "okay";
};
&panel {
compatible = "tianma,tm070jvhg33";
status = "okay";
};

5
arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi
View File

@ -219,6 +219,11 @@
};
};
&mipi_dsi {
vddcore-supply = <&ldo4_reg>;
vddio-supply = <&ldo3_reg>;
};
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;

3
arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts
View File

@ -312,6 +312,8 @@
interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
adc {
compatible = "gw,gsc-adc";
@ -583,7 +585,6 @@
st,drdy-int-pin = <1>;
interrupt-parent = <&gpio1>;
interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "INT1";
};
};

1
arch/arm64/boot/dts/freescale/imx8mn.dtsi
View File

@ -371,6 +371,7 @@
"pll8k", "pll11k", "clkext3";
dmas = <&sdma2 24 25 0x80000000>;
dma-names = "rx";
#sound-dai-cells = <0>;
status = "disabled";
};

70
arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts
View File

@ -23,6 +23,12 @@
stdout-path = &uart2;
};
clk_xtal25: clock-xtal25 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
connector {
compatible = "usb-c-connector";
label = "USB-C";
@ -49,6 +55,12 @@
};
};
dmic_codec: dmic-codec {
compatible = "dmic-codec";
num-channels = <1>;
#sound-dai-cells = <0>;
};
gpio-keys {
compatible = "gpio-keys";
autorepeat;
@ -112,12 +124,6 @@
};
};
pcie0_refclk: clock-pcie {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
reg_audio: regulator-wm8962 {
compatible = "regulator-fixed";
regulator-name = "3v3_aud";
@ -147,6 +153,22 @@
enable-active-high;
};
sound-dmic {
compatible = "simple-audio-card";
simple-audio-card,name = "sound-pdm";
simple-audio-card,format = "i2s";
simple-audio-card,bitclock-master = <&dailink_master>;
simple-audio-card,frame-master = <&dailink_master>;
dailink_master: simple-audio-card,cpu {
sound-dai = <&micfil>;
};
simple-audio-card,codec {
sound-dai = <&dmic_codec>;
};
};
sound-wm8962 {
compatible = "simple-audio-card";
simple-audio-card,name = "wm8962";
@ -174,6 +196,11 @@
};
};
&audio_blk_ctrl {
assigned-clocks = <&clk IMX8MP_AUDIO_PLL1>, <&clk IMX8MP_AUDIO_PLL2>;
assigned-clock-rates = <393216000>, <135475200>;
};
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
@ -246,6 +273,13 @@
interrupt-controller;
#interrupt-cells = <2>;
};
pcieclk: clock-generator@68 {
compatible = "renesas,9fgv0241";
reg = <0x68>;
clocks = <&clk_xtal25>;
#clock-cells = <1>;
};
};
&i2c3 {
@ -364,6 +398,15 @@
};
};
&micfil {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pdm>;
assigned-clocks = <&clk IMX8MP_CLK_PDM>;
assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
assigned-clock-rates = <49152000>;
status = "okay";
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
@ -372,8 +415,9 @@
};
&pcie_phy {
fsl,clkreq-unsupported;
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
clocks = <&pcie0_refclk>;
clocks = <&pcieclk 1>;
clock-names = "ref";
status = "okay";
};
@ -381,9 +425,10 @@
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
assigned-clocks = <&clk IMX8MP_CLK_SAI3>;
assigned-clocks = <&clk IMX8MP_CLK_SAI3>,
<&clk IMX8MP_AUDIO_PLL2> ;
assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL2_OUT>;
assigned-clock-rates = <12288000>;
assigned-clock-rates = <12288000>, <361267200>;
fsl,sai-mclk-direction-output;
status = "okay";
};
@ -544,6 +589,13 @@
>;
};
pinctrl_pdm: pdmgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_PDM_CLK 0xd6
MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_PDM_BIT_STREAM00 0xd6
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40

2
arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts
View File

@ -362,6 +362,8 @@
};
buck2: BUCK2 { /* VDD_ARM */
nxp,dvs-run-voltage = <950000>;
nxp,dvs-standby-voltage = <850000>;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1000000>;
regulator-ramp-delay = <3125>;

3
arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts
View File

@ -284,7 +284,6 @@
usb_hub_2_x: hub@1 {
compatible = "usbbda,5411";
reg = <1>;
reset-gpios = <&gpio4 25 GPIO_ACTIVE_LOW>;
vdd-supply = <&reg_usb_hub>;
peer-hub = <&usb_hub_3_x>;
};
@ -293,7 +292,6 @@
usb_hub_3_x: hub@2 {
compatible = "usbbda,411";
reg = <2>;
reset-gpios = <&gpio4 25 GPIO_ACTIVE_LOW>;
vdd-supply = <&reg_usb_hub>;
peer-hub = <&usb_hub_2_x>;
};
@ -443,7 +441,6 @@
pinctrl_usb1: usb1grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x10
MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x19
>;
};

2
arch/arm64/boot/dts/freescale/imx8mp-debix-som-a-bmb-08.dts
View File

@ -220,7 +220,7 @@
reg = <0x52>;
pagesize = <16>;
#address-cells = <1>;
#size-cells = <0>;
#size-cells = <1>;
/* MACs stored in ASCII */
ethmac1: mac-address@0 {

4
arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts
View File

@ -186,9 +186,9 @@
&pcie_phy {
clock-names = "ref";
clocks = <&clk IMX8MP_SYS_PLL2_100M>;
clocks = <&hsio_blk_ctrl>;
fsl,clkreq-unsupported;
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_UNUSED>;
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
status = "okay";
};

70
arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts
View File

@ -35,33 +35,6 @@
clock-frequency = <25000000>;
};
connector {
compatible = "usb-c-connector";
label = "USB-C";
data-role = "dual";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usb_c_0_hs_ep: endpoint {
remote-endpoint = <&dwc3_0_hs_ep>;
};
};
port@1 {
reg = <1>;
usb_c_0_ss_ep: endpoint {
remote-endpoint = <&ptn5150_in_ep>;
};
};
};
};
gpio-keys {
compatible = "gpio-keys";
@ -202,33 +175,19 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ptn5150>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port {
port@0 {
reg = <0>;
ptn5150_in_ep: endpoint {
remote-endpoint = <&usb_c_0_ss_ep>;
};
};
port@1 {
reg = <1>;
ptn5150_out_ep: endpoint {
remote-endpoint = <&dwc3_0_ss_ep>;
};
ptn5150_out_ep: endpoint {
remote-endpoint = <&dwc3_0_ep>;
};
};
};
power-sensor@40 {
compatible = "ti,ina238";
reg = <0x40>;
shunt-resistor = <20000>; /* 0.02 R */
ti,shunt-gain = <1>; /* Drop cca. 40mV */
compatible = "ti,ina238";
reg = <0x40>;
shunt-resistor = <20000>; /* 0.02 R */
ti,shunt-gain = <1>; /* Drop cca. 40mV */
};
eeprom_board: eeprom@54 {
@ -253,10 +212,6 @@
};
};
&ethphy0g {
reg = <7>;
};
&fec { /* Second ethernet */
pinctrl-0 = <&pinctrl_fec_rgmii>;
phy-handle = <&ethphypdk>;
@ -310,16 +265,7 @@
usb-role-switch;
port {
#address-cells = <1>;
#size-cells = <0>;
dwc3_0_hs_ep: endpoint@0 {
reg = <0>;
remote-endpoint = <&usb_c_0_hs_ep>;
};
dwc3_0_ss_ep: endpoint@1 {
reg = <1>;
dwc3_0_ep: endpoint {
remote-endpoint = <&ptn5150_out_ep>;
};
};

154
arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi
View File

@ -25,9 +25,7 @@
reg_eth_vio: regulator-eth-vio {
compatible = "regulator-fixed";
gpio = <&gpio2 10 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pinctrl_enet_vio>;
pinctrl-names = "default";
gpio = <&ioexp 2 GPIO_ACTIVE_LOW>;
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
@ -57,6 +55,11 @@
regulator-max-microvolt = <3300000>;
regulator-name = "VDD_3P3V_AWO";
};
wlan_pwrseq: wifi-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&ioexp 1 GPIO_ACTIVE_LOW>;
};
};
&A53_0 {
@ -112,7 +115,7 @@
reg = <0>;
reset-assert-us = <1000>;
reset-deassert-us = <1000>;
reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
reset-gpios = <&ioexp 4 GPIO_ACTIVE_LOW>;
/* Non-default PHY population option. */
status = "disabled";
};
@ -128,7 +131,7 @@
reg = <5>;
reset-assert-us = <1000>;
reset-deassert-us = <1000>;
reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
reset-gpios = <&ioexp 4 GPIO_ACTIVE_LOW>;
/* Default PHY population option. */
status = "okay";
};
@ -293,6 +296,8 @@
};
buck2: BUCK2 { /* VDD_ARM */
nxp,dvs-run-voltage = <950000>;
nxp,dvs-standby-voltage = <850000>;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1000000>;
regulator-ramp-delay = <3125>;
@ -348,8 +353,9 @@
};
adc@48 {
compatible = "ti,tla2024";
compatible = "ti,ads1015";
reg = <0x48>;
interrupts-extended = <&ioexp 7 IRQ_TYPE_EDGE_FALLING>;
#address-cells = <1>;
#size-cells = <0>;
@ -396,24 +402,42 @@
};
eeprom0: eeprom@50 { /* EEPROM with EQoS MAC address */
compatible = "atmel,24c02";
pagesize = <16>;
compatible = "atmel,24c32"; /* M24C32-D */
pagesize = <32>;
reg = <0x50>;
};
rv3032: rtc@51 {
compatible = "microcrystal,rv3032";
reg = <0x51>;
interrupts-extended = <&gpio5 5 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rtc>;
interrupts-extended = <&ioexp 3 IRQ_TYPE_EDGE_FALLING>;
wakeup-source;
};
eeprom1: eeprom@53 { /* EEPROM with FEC MAC address */
compatible = "atmel,24c02";
pagesize = <16>;
compatible = "atmel,24c32"; /* M24C32-D */
pagesize = <32>;
reg = <0x53>;
};
ioexp: gpio@74 {
compatible = "nxp,pca9539";
reg = <0x74>;
gpio-controller;
#gpio-cells = <2>;
interrupts-extended = <&gpio3 20 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ioexp>;
wakeup-source;
gpio-line-names =
"BT_REG_EN", "WL_REG_EN", "VIO_SWITCHED_#EN", "RTC_#INT",
"ENET_QOS_#RST", "RGB_OSZ_ENABLE", "USB1_ID", "ADC_ALTER_RDY",
"DHCOM-W", "DHCOM-V", "DHCOM-U", "DHCOM-T",
"BT_HOST_WAKE", "BT_DEV_WAKE", "", "";
};
};
&i2c4 {
@ -463,6 +487,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
wakeup-source;
};
&uart2 {
@ -484,10 +509,8 @@
assigned-clock-rates = <80000000>;
bluetooth {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2_bt>;
compatible = "cypress,cyw4373a0-bt";
shutdown-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
shutdown-gpios = <&ioexp 0 GPIO_ACTIVE_HIGH>;
max-speed = <4000000>;
};
};
@ -514,8 +537,6 @@
};
&usb_dwc3_0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0_vbus>;
dr_mode = "otg";
status = "okay";
};
@ -541,6 +562,7 @@
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
mmc-pwrseq = <&wlan_pwrseq>;
vmmc-supply = <&buck4>;
bus-width = <4>;
non-removable;
@ -559,7 +581,6 @@
* connected to the SoC, but can be connected on to
* SoC pin on the carrier board.
*/
reset-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
};
};
@ -601,8 +622,9 @@
&pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f
&pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_i
&pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l
/* GPIO_M is connected to CLKOUT1 */
&pinctrl_dhcom_int>;
&pinctrl_dhcom_m &pinctrl_dhcom_n &pinctrl_dhcom_o
&pinctrl_dhcom_p &pinctrl_dhcom_q &pinctrl_dhcom_r
&pinctrl_dhcom_s &pinctrl_dhcom_int>;
pinctrl-names = "default";
pinctrl_dhcom_a: dhcom-a-grp {
@ -689,6 +711,55 @@
>;
};
pinctrl_dhcom_m: dhcom-m-grp {
fsl,pins = <
/* CSIx_MCLK */
MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x2
>;
};
pinctrl_dhcom_n: dhcom-n-grp {
fsl,pins = <
/* CSI2_D3- */
MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x2
>;
};
pinctrl_dhcom_o: dhcom-o-grp {
fsl,pins = <
/* CSI2_D3+ */
MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x2
>;
};
pinctrl_dhcom_p: dhcom-p-grp {
fsl,pins = <
/* CSI2_D2- */
MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x2
>;
};
pinctrl_dhcom_q: dhcom-q-grp {
fsl,pins = <
/* CSI2_D2+ */
MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x2
>;
};
pinctrl_dhcom_r: dhcom-r-grp {
fsl,pins = <
/* CSI2_D1- */
MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x2
>;
};
pinctrl_dhcom_s: dhcom-s-grp {
fsl,pins = <
/* CSI2_D1+ */
MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x2
>;
};
pinctrl_dhcom_int: dhcom-int-grp {
fsl,pins = <
/* INT_HIGHEST_PRIO */
@ -762,16 +833,8 @@
>;
};
pinctrl_enet_vio: dhcom-enet-vio-grp {
fsl,pins = <
MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x22
>;
};
pinctrl_ethphy0: dhcom-ethphy0-grp {
fsl,pins = <
/* ENET_QOS_#RST Reset */
MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x22
/* ENET_QOS_#INT Interrupt */
MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x22
>;
@ -897,6 +960,13 @@
>;
};
pinctrl_ioexp: dhcom-ioexp-grp {
fsl,pins = <
/* #GPIO_EXP_INT */
MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x22
>;
};
pinctrl_pmic: dhcom-pmic-grp {
fsl,pins = <
/* PMIC_nINT */
@ -910,13 +980,6 @@
>;
};
pinctrl_rtc: dhcom-rtc-grp {
fsl,pins = <
/* RTC_#INT Interrupt */
MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x40000080
>;
};
pinctrl_tc9595: dhcom-tc9595-grp {
fsl,pins = <
/* RESET_DSIBRIDGE */
@ -962,13 +1025,6 @@
>;
};
pinctrl_uart2_bt: dhcom-uart2-bt-grp {
fsl,pins = <
/* BT_REG_EN */
MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x144
>;
};
pinctrl_uart3: dhcom-uart3-grp {
fsl,pins = <
MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x49
@ -985,12 +1041,6 @@
>;
};
pinctrl_usb0_vbus: dhcom-usb0-grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO10__USB1_OTG_ID 0x0
>;
};
pinctrl_usb1_vbus: dhcom-usb1-grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x6
@ -1006,8 +1056,6 @@
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
/* WL_REG_EN */
MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144
>;
};
@ -1019,8 +1067,6 @@
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4
/* WL_REG_EN */
MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144
>;
};
@ -1032,8 +1078,6 @@
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6
/* WL_REG_EN */
MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144
>;
};

154
arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
View File

@ -19,6 +19,36 @@
stdout-path = &uart1;
};
reg_can1_stby: regulator-can1-stby {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1_reg>;
gpio = <&gpio3 20 GPIO_ACTIVE_LOW>;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "can1-stby";
};
reg_can2_stby: regulator-can2-stby {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2_reg>;
gpio = <&gpio3 21 GPIO_ACTIVE_LOW>;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "can2-stby";
};
reg_usb1_vbus: regulator-usb1-vbus {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1_vbus>;
gpio = <&gpio1 12 GPIO_ACTIVE_LOW>;
regulator-max-microvolt = <5000000>;
regulator-min-microvolt = <5000000>;
regulator-name = "usb1_host_vbus";
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
@ -57,6 +87,21 @@
};
};
/* CAN FD */
&flexcan1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
xceiver-supply = <&reg_can1_stby>;
status = "okay";
};
&flexcan2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
xceiver-supply = <&reg_can2_stby>;
status = "okay";
};
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
@ -101,6 +146,47 @@
status = "okay";
};
/* USB1 Host mode Type-A */
&usb3_phy0 {
vbus-supply = <&reg_usb1_vbus>;
status = "okay";
};
&usb3_0 {
status = "okay";
};
&usb_dwc3_0 {
dr_mode = "host";
status = "okay";
};
/* USB2 4-port USB3.0 HUB */
&usb3_phy1 {
status = "okay";
};
&usb3_1 {
fsl,permanently-attached;
fsl,disable-port-power-control;
status = "okay";
};
&usb_dwc3_1 {
dr_mode = "host";
status = "okay";
};
/* RS232/RS485 */
&uart2 {
assigned-clocks = <&clk IMX8MP_CLK_UART2>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
uart-has-rtscts;
status = "okay";
};
/* SD-Card */
&usdhc2 {
assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
@ -115,6 +201,33 @@
status = "okay";
};
&gpio1 {
gpio-line-names = "", "", "X_PMIC_WDOG_B", "",
"PMIC_SD_VSEL", "", "", "", "", "",
"", "", "USB1_OTG_PWR", "", "", "X_nETHPHY_INT";
};
&gpio2 {
gpio-line-names = "", "", "", "",
"", "", "", "", "", "",
"", "", "X_SD2_CD_B", "", "", "",
"", "", "", "SD2_RESET_B";
};
&gpio3 {
gpio-line-names = "", "", "", "",
"", "", "", "", "", "",
"", "", "", "", "", "",
"", "", "", "", "nCAN1_EN", "nCAN2_EN";
};
&gpio4 {
gpio-line-names = "", "", "", "",
"", "", "", "", "", "",
"", "", "", "", "", "",
"", "", "X_PMIC_IRQ_B", "", "nENET0_INT_PWDN";
};
&iomuxc {
pinctrl_eqos: eqosgrp {
fsl,pins = <
@ -136,6 +249,32 @@
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x154
MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x154
>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154
MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154
>;
};
pinctrl_flexcan1_reg: flexcan1reggrp {
fsl,pins = <
MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x154
>;
};
pinctrl_flexcan2_reg: flexcan2reggrp {
fsl,pins = <
MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x154
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
@ -163,6 +302,21 @@
>;
};
pinctrl_usb1_vbus: usb1vbusgrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x10
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140
MX8MP_IOMUXC_SAI3_RXC__UART2_DCE_CTS 0x140
MX8MP_IOMUXC_SAI3_RXD__UART2_DCE_RTS 0x140
>;
};
pinctrl_usdhc2_pins: usdhc2-gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4

13
arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
View File

@ -199,6 +199,19 @@
status = "okay";
};
&gpio1 {
gpio-line-names = "", "", "X_PMIC_WDOG_B", "",
"", "", "", "", "", "",
"", "", "", "", "", "X_nETHPHY_INT";
};
&gpio4 {
gpio-line-names = "", "", "", "",
"", "", "", "", "", "",
"", "", "", "", "", "",
"", "", "X_PMIC_IRQ_B";
};
&iomuxc {
pinctrl_fec: fecgrp {
fsl,pins = <

1
arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx.dtsi
View File

@ -78,7 +78,6 @@
st,drdy-int-pin = <1>;
interrupt-parent = <&gpio4>;
interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "INT1";
};
};

1
arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi
View File

@ -113,7 +113,6 @@
st,drdy-int-pin = <1>;
interrupt-parent = <&gpio4>;
interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "INT1";
};
};

10
arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi
View File

@ -95,8 +95,15 @@
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi2>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>,
<&gpio1 10 GPIO_ACTIVE_LOW>;
status = "okay";
tpm@1 {
compatible = "tcg,tpm_tis-spi";
reg = <0x1>;
spi-max-frequency = <36000000>;
};
};
&gpio4 {
@ -125,7 +132,6 @@
st,drdy-int-pin = <1>;
interrupt-parent = <&gpio4>;
interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "INT1";
};
};

80
arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx-imx219.dtso Normal file
View File

@ -0,0 +1,80 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2023 Gateworks Corporation
*/
#include <dt-bindings/gpio/gpio.h>
#include "imx8mp-pinfunc.h"
/dts-v1/;
/plugin/;
&{/} {
compatible = "gw,imx8mp-gw74xx", "fsl,imx8mp";
reg_cam: regulator-cam {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_cam>;
compatible = "regulator-fixed";
regulator-name = "reg_cam";
gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
cam24m: cam24m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "cam24m";
};
};
&i2c4 {
#address-cells = <1>;
#size-cells = <0>;
imx219: sensor@10 {
compatible = "sony,imx219";
reg = <0x10>;
clocks = <&cam24m>;
VDIG-supply = <&reg_cam>;
port {
/* MIPI CSI-2 bus endpoint */
imx219_to_mipi_csi2: endpoint {
remote-endpoint = <&mipi_csi_0_in>;
clock-lanes = <0>;
data-lanes = <1 2>;
link-frequencies = /bits/ 64 <456000000>;
};
};
};
};
&isi_0 {
status = "okay";
};
&mipi_csi_0 {
status = "okay";
ports {
port@0 {
mipi_csi_0_in: endpoint {
remote-endpoint = <&imx219_to_mipi_csi2>;
data-lanes = <1 2>;
};
};
};
};
&iomuxc {
pinctrl_reg_cam: regcamgrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04 0x41
>;
};
};

2
arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts
View File

@ -461,7 +461,6 @@
st,drdy-int-pin = <1>;
interrupt-parent = <&gpio1>;
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "INT1";
};
switch: switch@5f {
@ -512,7 +511,6 @@
port@5 {
reg = <5>;
label = "cpu";
ethernet = <&fec>;
phy-mode = "rgmii-id";

1
arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi
View File

@ -184,7 +184,6 @@
&eqos {
phy-handle = <&ethphy0>;
phy-mode = "rgmii-id";
phy-supply = <&reg_module_eth1phy>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos>;
snps,force_thresh_dma_mode;

154
arch/arm64/boot/dts/freescale/imx8mp.dtsi
View File

@ -202,6 +202,60 @@
clock-output-names = "clk_ext4";
};
funnel {
/*
* non-configurable funnel don't show up on the AMBA
* bus. As such no need to add "arm,primecell".
*/
compatible = "arm,coresight-static-funnel";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
ca_funnel_in_port0: endpoint {
remote-endpoint = <&etm0_out_port>;
};
};
port@1 {
reg = <1>;
ca_funnel_in_port1: endpoint {
remote-endpoint = <&etm1_out_port>;
};
};
port@2 {
reg = <2>;
ca_funnel_in_port2: endpoint {
remote-endpoint = <&etm2_out_port>;
};
};
port@3 {
reg = <3>;
ca_funnel_in_port3: endpoint {
remote-endpoint = <&etm3_out_port>;
};
};
};
out-ports {
port {
ca_funnel_out_port0: endpoint {
remote-endpoint = <&hugo_funnel_in_port0>;
};
};
};
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
@ -368,59 +422,6 @@
};
};
funnel {
/*
* non-configurable funnel don't show up on the AMBA
* bus. As such no need to add "arm,primecell".
*/
compatible = "arm,coresight-static-funnel";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
ca_funnel_in_port0: endpoint {
remote-endpoint = <&etm0_out_port>;
};
};
port@1 {
reg = <1>;
ca_funnel_in_port1: endpoint {
remote-endpoint = <&etm1_out_port>;
};
};
port@2 {
reg = <2>;
ca_funnel_in_port2: endpoint {
remote-endpoint = <&etm2_out_port>;
};
};
port@3 {
reg = <3>;
ca_funnel_in_port3: endpoint {
remote-endpoint = <&etm3_out_port>;
};
};
};
out-ports {
port {
ca_funnel_out_port0: endpoint {
remote-endpoint = <&hugo_funnel_in_port0>;
};
};
};
};
funnel@28c03000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x28c03000 0x1000>;
@ -790,6 +791,12 @@
reg = <IMX8MP_POWER_DOMAIN_AUDIOMIX>;
clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>,
<&clk IMX8MP_CLK_AUDIO_AXI>;
assigned-clocks = <&clk IMX8MP_CLK_AUDIO_AHB>,
<&clk IMX8MP_CLK_AUDIO_AXI_SRC>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
<&clk IMX8MP_SYS_PLL1_800M>;
assigned-clock-rates = <400000000>,
<600000000>;
};
pgc_gpu2d: power-domain@6 {
@ -1453,6 +1460,47 @@
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
easrc: easrc@30c90000 {
compatible = "fsl,imx8mp-easrc", "fsl,imx8mn-easrc";
reg = <0x30c90000 0x10000>;
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_ASRC_IPG>;
clock-names = "mem";
dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>,
<&sdma2 18 23 0> , <&sdma2 19 23 0>,
<&sdma2 20 23 0> , <&sdma2 21 23 0>,
<&sdma2 22 23 0> , <&sdma2 23 23 0>;
dma-names = "ctx0_rx", "ctx0_tx",
"ctx1_rx", "ctx1_tx",
"ctx2_rx", "ctx2_tx",
"ctx3_rx", "ctx3_tx";
firmware-name = "imx/easrc/easrc-imx8mn.bin";
fsl,asrc-rate = <8000>;
fsl,asrc-format = <2>;
status = "disabled";
};
micfil: audio-controller@30ca0000 {
compatible = "fsl,imx8mp-micfil";
reg = <0x30ca0000 0x10000>;
#sound-dai-cells = <0>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_PDM_IPG>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_PDM_SEL>,
<&clk IMX8MP_AUDIO_PLL1_OUT>,
<&clk IMX8MP_AUDIO_PLL2_OUT>,
<&clk IMX8MP_CLK_EXT3>;
clock-names = "ipg_clk", "ipg_clk_app",
"pll8k", "pll11k", "clkext3";
dmas = <&sdma2 24 25 0x80000000>;
dma-names = "rx";
status = "disabled";
};
};
sdma3: dma-controller@30e00000 {

7
arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi
View File

@ -381,7 +381,7 @@
gpio-hog;
gpios = <1 GPIO_ACTIVE_HIGH>;
input;
lane-mapping = "pmic-5v";
line-name = "pmic-5v";
};
};
@ -1001,7 +1001,7 @@
};
regulator@3e {
compatible = "tps65132";
compatible = "ti,tps65132";
reg = <0x3e>;
reg_lcd_avdd: outp {
@ -1154,15 +1154,12 @@
pinctrl-0 = <&pinctrl_charger_in>;
interrupt-parent = <&gpio3>;
interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
phys = <&usb3_phy0>;
ti,battery-regulation-voltage = <4208000>; /* uV */
ti,termination-current = <128000>; /* uA */
ti,precharge-current = <128000>; /* uA */
ti,minimum-sys-voltage = <3700000>; /* uV */
ti,boost-voltage = <5000000>; /* uV */
ti,boost-max-current = <1500000>; /* uA */
ti,use-vinmin-threshold = <1>; /* enable VINDPM */
ti,vinmin-threshold = <3900000>; /* uV */
monitored-battery = <&bat>;
power-supplies = <&typec_pd>;
};

14
arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts
View File

@ -142,7 +142,7 @@
#address-cells = <1>;
#size-cells = <0>;
i2c1a: i2c1@0 {
i2c1a: i2c@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
@ -159,7 +159,7 @@
};
};
i2c1b: i2c1@1 {
i2c1b: i2c@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
@ -176,7 +176,7 @@
};
};
i2c1c: i2c1@2 {
i2c1c: i2c@2 {
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
@ -193,7 +193,7 @@
};
};
i2c1d: i2c1@3 {
i2c1d: i2c@3 {
reg = <3>;
#address-cells = <1>;
#size-cells = <0>;
@ -222,7 +222,7 @@
#address-cells = <1>;
#size-cells = <0>;
i2c4@0 {
i2c@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
@ -257,14 +257,14 @@
};
};
ddc_i2c_bus: i2c4@1 {
ddc_i2c_bus: i2c@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <100000>;
};
i2c4@3 {
i2c@3 {
reg = <3>;
#address-cells = <1>;
#size-cells = <0>;

2
arch/arm64/boot/dts/freescale/imx8mq-pico-pi.dts
View File

@ -67,12 +67,12 @@
compatible = "rohm,bd71837";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
#clock-cells = <0>;
clocks = <&pmic_osc>;
clock-names = "osc";
clock-output-names = "pmic_clk";
interrupt-parent = <&gpio1>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "irq";
regulators {
buck1: BUCK1 {

2
arch/arm64/boot/dts/freescale/imx8mq-thor96.dts
View File

@ -107,7 +107,7 @@
compatible = "mmc-pwrseq-simple";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wifi_reg_on>;
gpio = <&gpio3 3 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>;
};
};

49
arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx-lvds-tm070jvhg33.dtso Normal file
View File

@ -0,0 +1,49 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (c) 2019-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Alexander Stein
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
&{/} {
compatible = "tq,imx8mq-tqma8mq-mba8mx", "tq,imx8mq-tqma8mq", "fsl,imx8mq";
};
&backlight_lvds {
status = "okay";
};
&dphy {
status = "okay";
};
&dsi_lvds_bridge {
status = "okay";
};
&expander0 {
dsi-mux-oe-hog {
gpio-hog;
gpios = <10 GPIO_ACTIVE_LOW>;
output-high;
line-name = "DSI_MUX_OE#";
};
};
&lcdif {
status = "okay";
};
&mipi_dsi {
status = "okay";
};
&panel {
compatible = "tianma,tm070jvhg33";
status = "okay";
};

2
arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi
View File

@ -15,7 +15,7 @@
stdout-path = &uart1;
};
mdio0: bitbang-mdio {
mdio0: mdio {
compatible = "virtual,mdio-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mdio_bitbang>, <&pinctrl_fec1_phy_reset>;

106
arch/arm64/boot/dts/freescale/imx8mq.dtsi
View File

@ -225,6 +225,59 @@
};
};
funnel {
/*
* non-configurable funnel don't show up on the AMBA
* bus. As such no need to add "arm,primecell".
*/
compatible = "arm,coresight-static-funnel";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
ca_funnel_in_port0: endpoint {
remote-endpoint = <&etm0_out_port>;
};
};
port@1 {
reg = <1>;
ca_funnel_in_port1: endpoint {
remote-endpoint = <&etm1_out_port>;
};
};
port@2 {
reg = <2>;
ca_funnel_in_port2: endpoint {
remote-endpoint = <&etm2_out_port>;
};
};
port@3 {
reg = <3>;
ca_funnel_in_port3: endpoint {
remote-endpoint = <&etm3_out_port>;
};
};
};
out-ports {
port {
ca_funnel_out_port0: endpoint {
remote-endpoint = <&hugo_funnel_in_port0>;
};
};
};
};
pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
@ -394,59 +447,6 @@
};
};
funnel {
/*
* non-configurable funnel don't show up on the AMBA
* bus. As such no need to add "arm,primecell".
*/
compatible = "arm,coresight-static-funnel";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
ca_funnel_in_port0: endpoint {
remote-endpoint = <&etm0_out_port>;
};
};
port@1 {
reg = <1>;
ca_funnel_in_port1: endpoint {
remote-endpoint = <&etm1_out_port>;
};
};
port@2 {
reg = <2>;
ca_funnel_in_port2: endpoint {
remote-endpoint = <&etm2_out_port>;
};
};
port@3 {
reg = <3>;
ca_funnel_in_port3: endpoint {
remote-endpoint = <&etm3_out_port>;
};
};
};
out-ports {
port {
ca_funnel_out_port0: endpoint {
remote-endpoint = <&hugo_funnel_in_port0>;
};
};
};
};
funnel@28c03000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x28c03000 0x1000>;

1
arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi
View File

@ -21,7 +21,6 @@
* this PHY model. Use delay on MAC side instead.
*/
&fec1 {
fsl,rgmii_txc_dly;
phy-mode = "rgmii-rxid";
};

26
arch/arm64/boot/dts/freescale/imx8qm-mek.dts
View File

@ -47,6 +47,18 @@
status = "okay";
};
&lpuart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart2>;
status = "okay";
};
&lpuart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart3>;
status = "okay";
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
@ -118,6 +130,20 @@
>;
};
pinctrl_lpuart2: lpuart2grp {
fsl,pins = <
IMX8QM_UART0_RTS_B_DMA_UART2_RX 0x06000020
IMX8QM_UART0_CTS_B_DMA_UART2_TX 0x06000020
>;
};
pinctrl_lpuart3: lpuart3grp {
fsl,pins = <
IMX8QM_M41_GPIO0_00_DMA_UART3_RX 0x06000020
IMX8QM_M41_GPIO0_01_DMA_UART3_TX 0x06000020
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041

56
arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi
View File

@ -44,6 +44,58 @@
};
};
&edma2 {
reg = <0x5a1f0000 0x170000>;
#dma-cells = <3>;
dma-channels = <22>;
dma-channel-mask = <0xf00>;
interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* unused */
<GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* unused */
<GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* unused */
<GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* unused */
<GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd IMX_SC_R_DMA_0_CH0>,
<&pd IMX_SC_R_DMA_0_CH1>,
<&pd IMX_SC_R_DMA_0_CH2>,
<&pd IMX_SC_R_DMA_0_CH3>,
<&pd IMX_SC_R_DMA_0_CH4>,
<&pd IMX_SC_R_DMA_0_CH5>,
<&pd IMX_SC_R_DMA_0_CH6>,
<&pd IMX_SC_R_DMA_0_CH7>,
<&pd IMX_SC_R_DMA_0_CH8>,
<&pd IMX_SC_R_DMA_0_CH9>,
<&pd IMX_SC_R_DMA_0_CH10>,
<&pd IMX_SC_R_DMA_0_CH11>,
<&pd IMX_SC_R_DMA_0_CH12>,
<&pd IMX_SC_R_DMA_0_CH13>,
<&pd IMX_SC_R_DMA_0_CH14>,
<&pd IMX_SC_R_DMA_0_CH15>,
<&pd IMX_SC_R_DMA_0_CH16>,
<&pd IMX_SC_R_DMA_0_CH17>,
<&pd IMX_SC_R_DMA_0_CH18>,
<&pd IMX_SC_R_DMA_0_CH19>,
<&pd IMX_SC_R_DMA_0_CH20>,
<&pd IMX_SC_R_DMA_0_CH21>;
status = "okay";
};
&flexcan1 {
fsl,clk-source = /bits/ 8 <1>;
};
@ -64,18 +116,22 @@
&lpuart0 {
compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
dmas = <&edma2 13 0 0>, <&edma2 12 0 1>;
};
&lpuart1 {
compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
dmas = <&edma2 15 0 0>, <&edma2 14 0 1>;
};
&lpuart2 {
compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
dmas = <&edma2 17 0 0>, <&edma2 16 0 1>;
};
&lpuart3 {
compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
dmas = <&edma2 19 0 0>, <&edma2 18 0 1>;
};
&i2c0 {

2
arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi
View File

@ -8,5 +8,5 @@
};
&jpegenc {
compatible = "nxp,imx8qm-jpgdec", "nxp,imx8qxp-jpgenc";
compatible = "nxp,imx8qm-jpgenc", "nxp,imx8qxp-jpgenc";
};

26
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
View File

@ -187,6 +187,18 @@
status = "okay";
};
&lpuart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart2>;
status = "okay";
};
&lpuart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart3>;
status = "okay";
};
&mu_m0 {
status = "okay";
};
@ -340,6 +352,20 @@
>;
};
pinctrl_lpuart2: lpuart2grp {
fsl,pins = <
IMX8QXP_UART2_TX_ADMA_UART2_TX 0x06000020
IMX8QXP_UART2_RX_ADMA_UART2_RX 0x06000020
>;
};
pinctrl_lpuart3: lpuart3grp {
fsl,pins = <
IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020
IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020
>;
};
pinctrl_typec: typecgrp {
fsl,pins = <
IMX8QXP_SPI2_SCK_LSIO_GPIO1_IO03 0x06000021

23
arch/arm64/boot/dts/freescale/imx8ulp.dtsi
View File

@ -360,7 +360,7 @@
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc4 IMX8ULP_CLK_FLEXSPI2>,
<&pcc4 IMX8ULP_CLK_FLEXSPI2>;
clock-names = "fspi", "fspi_en";
clock-names = "fspi_en", "fspi";
assigned-clocks = <&pcc4 IMX8ULP_CLK_FLEXSPI2>;
assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>;
status = "disabled";
@ -484,11 +484,12 @@
};
gpioe: gpio@2d000080 {
compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
reg = <0x2d000080 0x1000>, <0x2d000040 0x40>;
compatible = "fsl,imx8ulp-gpio";
reg = <0x2d000000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pcc4 IMX8ULP_CLK_RGPIOE>,
@ -498,11 +499,12 @@
};
gpiof: gpio@2d010080 {
compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
reg = <0x2d010080 0x1000>, <0x2d010040 0x40>;
compatible = "fsl,imx8ulp-gpio";
reg = <0x2d010000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pcc4 IMX8ULP_CLK_RGPIOF>,
@ -533,11 +535,12 @@
};
gpiod: gpio@2e200080 {
compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
reg = <0x2e200080 0x1000>, <0x2e200040 0x40>;
compatible = "fsl,imx8ulp-gpio";
reg = <0x2e200000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pcc5 IMX8ULP_CLK_RGPIOD>,

4
arch/arm64/boot/dts/freescale/imx8x-colibri-iris-v2.dtsi
View File

@ -23,11 +23,11 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lvds_converter &pinctrl_gpio_iris>;
pinctrl_enable_3v3_vmmc: enable_3v3_vmmc {
pinctrl_enable_3v3_vmmc: enable-3v3-vmmc-grp {
fsl,pins = <IMX8QXP_SAI1_RXFS_LSIO_GPIO0_IO31 0x20>; /* SODIMM 100 */
};
pinctrl_lvds_converter: lcd-lvds {
pinctrl_lvds_converter: lvds-converter-grp {
fsl,pins = <IMX8QXP_FLEXCAN1_TX_LSIO_GPIO1_IO18 0x20>, /* SODIMM 55 */
/* 6B/8B mode. Select LOW - 8B mode (24bit) */
<IMX8QXP_FLEXCAN1_RX_LSIO_GPIO1_IO17 0x20>, /* SODIMM 63 */

15
arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts
View File

@ -149,6 +149,12 @@
status = "okay";
};
&lpuart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
status = "okay";
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
@ -222,6 +228,15 @@
>;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e
MX93_PAD_DAP_TDI__LPUART5_RX 0x31e
MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e
MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe

2
arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi
View File

@ -81,7 +81,7 @@
&gpio1 {
pmic-irq-hog {
gpio-hog;
gpios = <2 GPIO_ACTIVE_LOW>;
gpios = <3 GPIO_ACTIVE_LOW>;
input;
line-name = "PMIC_IRQ#";
};

159
arch/arm64/boot/dts/freescale/imx93.dtsi
View File

@ -185,6 +185,46 @@
#size-cells = <1>;
ranges;
edma1: dma-controller@44000000 {
compatible = "fsl,imx93-edma3";
reg = <0x44000000 0x200000>;
#dma-cells = <3>;
dma-channels = <31>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, // 0: Reserved
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, // 1: CANFD1
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, // 2: Reserved
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, // 3: GPIO1 CH0
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, // 4: GPIO1 CH1
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, // 5: I3C1 TO Bus
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, // 6: I3C1 From Bus
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, // 7: LPI2C1 M TX
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, // 8: LPI2C1 S TX
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, // 9: LPI2C2 M RX
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, // 10: LPI2C2 S RX
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, // 11: LPSPI1 TX
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, // 12: LPSPI1 RX
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, // 13: LPSPI2 TX
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, // 14: LPSPI2 RX
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, // 15: LPTMR1
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, // 16: LPUART1 TX
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, // 17: LPUART1 RX
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, // 18: LPUART2 TX
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, // 19: LPUART2 RX
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, // 20: S400
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, // 21: SAI TX
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, // 22: SAI RX
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, // 23: TPM1 CH0/CH2
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, // 24: TPM1 CH1/CH3
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, // 25: TPM1 Overflow
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, // 26: TMP2 CH0/CH2
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, // 27: TMP2 CH1/CH3
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, // 28: TMP2 Overflow
<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, // 29: PDM
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; // 30: ADC1
clocks = <&clk IMX93_CLK_EDMA1_GATE>;
clock-names = "dma";
};
anomix_ns_gpr: syscon@44210000 {
compatible = "fsl,imx93-aonmix-ns-syscfg", "syscon";
reg = <0x44210000 0x1000>;
@ -296,6 +336,8 @@
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_LPUART1_GATE>;
clock-names = "ipg";
dmas = <&edma1 17 0 1>, <&edma1 16 0 0>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -305,6 +347,8 @@
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_LPUART2_GATE>;
clock-names = "ipg";
dmas = <&edma1 19 0 1>, <&edma1 18 0 0>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -385,6 +429,7 @@
tmu: tmu@44482000 {
compatible = "fsl,qoriq-tmu";
reg = <0x44482000 0x1000>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_TMC_GATE>;
little-endian;
fsl,tmu-range = <0x800000da 0x800000e9
@ -423,6 +468,80 @@
#size-cells = <1>;
ranges;
edma2: dma-controller@42000000 {
compatible = "fsl,imx93-edma4";
reg = <0x42000000 0x210000>;
#dma-cells = <3>;
shared-interrupt;
dma-channels = <64>;
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_EDMA2_GATE>;
clock-names = "dma";
};
wakeupmix_gpr: syscon@42420000 {
compatible = "fsl,imx93-wakeupmix-syscfg", "syscon";
reg = <0x42420000 0x1000>;
@ -550,6 +669,8 @@
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_LPUART3_GATE>;
clock-names = "ipg";
dmas = <&edma2 18 0 1>, <&edma2 17 0 0>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -559,6 +680,8 @@
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_LPUART4_GATE>;
clock-names = "ipg";
dmas = <&edma2 20 0 1>, <&edma2 19 0 0>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -568,6 +691,8 @@
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_LPUART5_GATE>;
clock-names = "ipg";
dmas = <&edma2 22 0 1>, <&edma2 21 0 0>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -577,6 +702,8 @@
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_LPUART6_GATE>;
clock-names = "ipg";
dmas = <&edma2 24 0 1>, <&edma2 23 0 0>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -615,6 +742,8 @@
interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_LPUART7_GATE>;
clock-names = "ipg";
dmas = <&edma2 88 0 1>, <&edma2 87 0 0>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -624,6 +753,8 @@
interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_LPUART8_GATE>;
clock-names = "ipg";
dmas = <&edma2 90 0 1>, <&edma2 89 0 0>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -825,11 +956,12 @@
};
gpio2: gpio@43810080 {
compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio";
reg = <0x43810080 0x1000>, <0x43810040 0x40>;
compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio";
reg = <0x43810000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clk IMX93_CLK_GPIO2_GATE>,
@ -839,11 +971,12 @@
};
gpio3: gpio@43820080 {
compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio";
reg = <0x43820080 0x1000>, <0x43820040 0x40>;
compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio";
reg = <0x43820000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clk IMX93_CLK_GPIO3_GATE>,
@ -854,11 +987,12 @@
};
gpio4: gpio@43830080 {
compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio";
reg = <0x43830080 0x1000>, <0x43830040 0x40>;
compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio";
reg = <0x43830000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clk IMX93_CLK_GPIO4_GATE>,
@ -868,11 +1002,12 @@
};
gpio1: gpio@47400080 {
compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio";
reg = <0x47400080 0x1000>, <0x47400040 0x40>;
compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio";
reg = <0x47400000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clk IMX93_CLK_GPIO1_GATE>,

93
arch/arm64/boot/dts/freescale/mba8mx.dtsi
View File

@ -8,6 +8,16 @@
/* TQ-Systems GmbH MBa8Mx baseboard */
/ {
backlight_lvds: backlight {
compatible = "pwm-backlight";
pwms = <&pwm3 0 5000000 0>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <7>;
power-supply = <&reg_12v>;
enable-gpios = <&expander2 2 GPIO_ACTIVE_HIGH>;
status = "disabled";
};
beeper {
compatible = "pwm-beeper";
pwms = <&pwm4 0 250000 0>;
@ -65,12 +75,45 @@
};
};
gpio_delays: gpio-delays {
compatible = "gpio-delay";
#gpio-cells = <3>;
gpio-controller;
gpios = <&expander0 6 GPIO_ACTIVE_HIGH>;
gpio-line-names = "LVDS_BRIDGE_EN_1V8";
};
panel: panel-lvds {
/*
* Display is not fixed, so compatible has to be added from
* DT overlay
*/
backlight = <&backlight_lvds>;
power-supply = <&reg_vcc_3v3>;
status = "disabled";
port {
panel_in_lvds: endpoint {
data-lanes = <1 2 3 4>;
remote-endpoint = <&lvds_bridge_out>;
};
};
};
pcie0_refclk: pcie0-refclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
reg_12v: regulator-12v {
compatible = "regulator-fixed";
regulator-name = "MBA8MX_12V";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
regulator-always-on;
};
reg_hub_vbus: regulator-hub-vbus {
compatible = "regulator-fixed";
regulator-name = "MBA8MX_HUB_VBUS";
@ -157,6 +200,10 @@
interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-line-names = "", "", "", "",
"", "", "LVDS_BRIDGE_EN", "",
"", "", "", "",
"", "", "", "";
sd-mux-oe-hog {
gpio-hog;
@ -227,6 +274,52 @@
scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
dsi_lvds_bridge: bridge@2d {
compatible = "ti,sn65dsi84";
reg = <0x2d>;
enable-gpios = <&gpio_delays 0 130000 0>;
vcc-supply = <&reg_sn65dsi83_1v8>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
lvds_bridge_in: endpoint {
data-lanes = <1 2 3 4>;
remote-endpoint = <&mipi_dsi_out>;
};
};
port@2 {
reg = <2>;
lvds_bridge_out: endpoint {
remote-endpoint = <&panel_in_lvds>;
};
};
};
};
};
&mipi_dsi {
samsung,burst-clock-frequency = <891000000>;
samsung,esc-clock-frequency = <20000000>;
ports {
port@1 {
reg = <1>;
mipi_dsi_out: endpoint {
data-lanes = <1 2 3 4>;
remote-endpoint = <&lvds_bridge_in>;
};
};
};
};
&pwm3 {

104
arch/arm64/boot/dts/freescale/tqmls104xa-mbls10xxa-fman.dtsi Normal file
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@ -0,0 +1,104 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (c) 2019,2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Gregor Herburger, Timo Herbrecher
*
* Device Tree Include file for MBLS10xxA from TQ (FMAN related sections)
*/
#include <dt-bindings/net/ti-dp83867.h>
&enet0 {
status = "disabled";
};
&enet1 {
status = "disabled";
};
&enet2 {
phy-handle = <&rgmii_phy1>;
phy-connection-type = "rgmii";
phy-mode = "rgmii-id";
status = "okay";
};
&enet3 {
phy-handle = <&rgmii_phy2>;
phy-connection-type = "rgmii";
phy-mode = "rgmii-id";
status = "okay";
};
&enet4 {
status = "disabled";
};
&enet5 {
status = "disabled";
};
&enet6 {
status = "disabled";
};
&mdio0 {
status = "okay";
qsgmii2_phy1: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x00>;
};
qsgmii2_phy2: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x01>;
};
qsgmii2_phy3: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x02>;
};
qsgmii2_phy4: ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x03>;
};
rgmii_phy2: ethernet-phy@c {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x0c>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
};
rgmii_phy1: ethernet-phy@e {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x0e>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
};
qsgmii1_phy1: ethernet-phy@1c {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x1c>;
};
qsgmii1_phy2: ethernet-phy@1d {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x1d>;
};
qsgmii1_phy3: ethernet-phy@1e {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x1e>;
};
qsgmii1_phy4: ethernet-phy@1f {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x1f>;
};
};

146
arch/arm64/boot/dts/freescale/tqmls1088a-mbls10xxa-mc.dtsi Normal file
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@ -0,0 +1,146 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (c) 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Gregor Herburger, Timo Herbrecher
*
* Device Tree Include file for MBLS10xxA from TQ (MC related sections)
*/
#include <dt-bindings/net/ti-dp83867.h>
/ {
sfp1: sfp1 {
compatible = "sff,sfp";
i2c-bus = <&sfp1_i2c>;
mod-def0-gpios = <&gpioexp2 2 GPIO_ACTIVE_LOW>;
los-gpios = <&gpioexp2 3 GPIO_ACTIVE_HIGH>;
tx-fault-gpios = <&gpioexp2 0 GPIO_ACTIVE_HIGH>;
tx-disable-gpios = <&gpioexp2 1 GPIO_ACTIVE_HIGH>;
};
sfp2: sfp2 {
compatible = "sff,sfp";
i2c-bus = <&sfp2_i2c>;
mod-def0-gpios = <&gpioexp2 10 GPIO_ACTIVE_LOW>;
los-gpios = <&gpioexp2 11 GPIO_ACTIVE_HIGH>;
tx-fault-gpios = <&gpioexp2 8 GPIO_ACTIVE_HIGH>;
tx-disable-gpios = <&gpioexp2 9 GPIO_ACTIVE_HIGH>;
};
};
&dpmac1 {
pcs-handle = <&pcs1>;
};
&dpmac2 {
pcs-handle = <&pcs2>;
};
&dpmac3 {
pcs-handle = <&pcs3_0>;
};
&dpmac4 {
pcs-handle = <&pcs3_1>;
};
&dpmac5 {
pcs-handle = <&pcs3_2>;
};
&dpmac6 {
pcs-handle = <&pcs3_3>;
};
&dpmac7 {
pcs-handle = <&pcs7_0>;
};
&dpmac8 {
pcs-handle = <&pcs7_1>;
};
&dpmac9 {
pcs-handle = <&pcs7_2>;
};
&dpmac10 {
pcs-handle = <&pcs7_3>;
};
&emdio1 {
status = "okay";
qsgmii2_phy1: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x00>;
};
qsgmii2_phy2: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x01>;
};
qsgmii2_phy3: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x02>;
};
qsgmii2_phy4: ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x03>;
};
rgmii_phy2: ethernet-phy@c {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x0c>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
};
rgmii_phy1: ethernet-phy@e {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x0e>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
};
qsgmii1_phy1: ethernet-phy@1c {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x1c>;
};
qsgmii1_phy2: ethernet-phy@1d {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x1d>;
};
qsgmii1_phy3: ethernet-phy@1e {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x1e>;
};
qsgmii1_phy4: ethernet-phy@1f {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x1f>;
};
};
&pcs_mdio1 {
status = "okay";
};
&pcs_mdio2 {
status = "okay";
};
&pcs_mdio3 {
status = "okay";
};
&pcs_mdio7 {
status = "okay";
};

136
arch/arm64/boot/dts/freescale/tqmls10xxa-mbls10xxa.dtsi Normal file
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@ -0,0 +1,136 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (c) 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Gregor Herburger, Timo Herbrecher
*
* Device Tree Include file for MBLS10xxA from TQ
*/
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
/ {
gpio-keys-polled {
compatible = "gpio-keys-polled";
poll-interval = <100>;
autorepeat;
button-0 {
label = "button0";
gpios = <&gpioexp3 5 GPIO_ACTIVE_LOW>;
linux,code = <KEY_F1>;
};
button-1 {
label = "button1";
gpios = <&gpioexp3 6 GPIO_ACTIVE_LOW>;
linux,code = <KEY_F2>;
};
};
leds {
compatible = "gpio-leds";
led-user {
gpios = <&gpioexp3 13 GPIO_ACTIVE_LOW>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_HEARTBEAT;
linux,default-trigger = "heartbeat";
};
};
reg_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "V_3V3_MB";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
&duart0 {
status = "okay";
};
&duart1 {
status = "okay";
};
&esdhc {
status = "okay";
};
&i2c3 {
status = "okay";
i2c-mux@70 {
compatible = "nxp,pca9544";
reg = <0x70>;
#address-cells = <1>;
#size-cells = <0>;
i2c@0 {
reg = <0x0>;
#address-cells = <1>;
#size-cells = <0>;
gpioexp1: gpio@20 {
compatible = "nxp,pca9555";
reg = <0x20>;
vcc-supply = <&reg_3v3>;
gpio-controller;
#gpio-cells = <2>;
};
gpioexp2: gpio@21 {
compatible = "nxp,pca9555";
reg = <0x21>;
vcc-supply = <&reg_3v3>;
gpio-controller;
#gpio-cells = <2>;
};
gpioexp3: gpio@22 {
compatible = "nxp,pca9555";
reg = <0x22>;
vcc-supply = <&reg_3v3>;
gpio-controller;
#gpio-cells = <2>;
};
};
sfp1_i2c: i2c@1 {
reg = <0x1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
sfp2_i2c: i2c@2 {
reg = <0x2>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c@3 {
reg = <0x3>;
#address-cells = <1>;
#size-cells = <0>;
};
};
};
&sata {
status = "okay";
};
&usb0 {
status = "okay";
};
&usb1 {
dr_mode = "otg";
status = "okay";
};

58
arch/arm64/boot/dts/freescale/tqmls10xxa.dtsi Normal file
View File

@ -0,0 +1,58 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (c) 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Gregor Herburger, Timo Herbrecher
*
* Device Tree Include file for TQMLs10xxA SoM of TQ
*/
/ {
reg_vcc3v3: regulator-vcc3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
&i2c0 {
status = "okay";
temperature-sensor@18 {
compatible = "nxp,se97b", "jedec,jc-42.4-temp";
reg = <0x18>;
};
eeprom@50 {
compatible = "nxp,se97b", "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
vcc-supply = <&reg_vcc3v3>;
read-only;
};
rtc@51 {
compatible = "nxp,pcf85063a";
reg = <0x51>;
};
eeprom@57 {
compatible = "atmel,24c64";
reg = <0x57>;
pagesize = <32>;
vcc-supply = <&reg_vcc3v3>;
};
};
&esdhc {
/* eSDHC or eMMC: set by bootloader */
non-removable;
disable-wp;
mmc-hs200-1_8v;
sd-uhs-sdr104;
sd-uhs-sdr50;
sd-uhs-sdr25;
sd-uhs-sdr12;
};

1
drivers/firmware/imx/imx-dsp.c
View File

@ -114,6 +114,7 @@ static int imx_dsp_setup_channels(struct imx_dsp_ipc *dsp_ipc)
dsp_chan->idx = i % 2;
dsp_chan->ch = mbox_request_channel_byname(cl, chan_name);
if (IS_ERR(dsp_chan->ch)) {
kfree(dsp_chan->name);
ret = PTR_ERR(dsp_chan->ch);
if (ret != -EPROBE_DEFER)
dev_err(dev, "Failed to request mbox chan %s ret %d\n",

10
drivers/soc/imx/soc-imx8m.c
View File

@ -100,6 +100,7 @@ static void __init imx8mm_soc_uid(void)
{
void __iomem *ocotp_base;
struct device_node *np;
struct clk *clk;
u32 offset = of_machine_is_compatible("fsl,imx8mp") ?
IMX8MP_OCOTP_UID_OFFSET : 0;
@ -109,11 +110,20 @@ static void __init imx8mm_soc_uid(void)
ocotp_base = of_iomap(np, 0);
WARN_ON(!ocotp_base);
clk = of_clk_get_by_name(np, NULL);
if (IS_ERR(clk)) {
WARN_ON(IS_ERR(clk));
return;
}
clk_prepare_enable(clk);
soc_uid = readl_relaxed(ocotp_base + OCOTP_UID_HIGH + offset);
soc_uid <<= 32;
soc_uid |= readl_relaxed(ocotp_base + OCOTP_UID_LOW + offset);
clk_disable_unprepare(clk);
clk_put(clk);
iounmap(ocotp_base);
of_node_put(np);
}