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[ARM] Remove LOADREGS macro

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As for RETINSTR, LOADREGS is a left-over from the 26-bit days.
Remove it.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King 2006-06-25 11:23:45 +01:00 committed by Russell King
parent 7999d8d7a6
commit 1b93a71755
15 changed files with 30 additions and 41 deletions
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6
arch/arm/boot/compressed/ll_char_wr.S
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@ -77,7 +77,7 @@ Lrow4bpplp:
subne r1, r1, #1
ldrneb r7, [r6, r1]
bne Lrow4bpplp
LOADREGS(fd, sp!, {r4 - r7, pc})
ldmfd sp!, {r4 - r7, pc}
@
@ Smashable regs: {r0 - r3}, [r4], {r5 - r7}, (r8 - fp), [ip], (sp), {lr}, (pc)
@ -105,7 +105,7 @@ Lrow8bpplp:
subne r1, r1, #1
ldrneb r7, [r6, r1]
bne Lrow8bpplp
LOADREGS(fd, sp!, {r4 - r7, pc})
ldmfd sp!, {r4 - r7, pc}
@
@ Smashable regs: {r0 - r3}, [r4], {r5, r6}, [r7], (r8 - fp), [ip], (sp), [lr], (pc)
@ -127,7 +127,7 @@ Lrow1bpp:
strb r7, [r0], r5
mov r7, r7, lsr #8
strb r7, [r0], r5
LOADREGS(fd, sp!, {r4 - r7, pc})
ldmfd sp!, {r4 - r7, pc}
.bss
ENTRY(con_charconvtable)

8
arch/arm/lib/backtrace.S
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@ -41,7 +41,7 @@ ENTRY(c_backtrace)
movne r0, #0
movs frame, r0
1: moveq r0, #-2
LOADREGS(eqfd, sp!, {r4 - r8, pc})
ldmeqfd sp!, {r4 - r8, pc}
2: stmfd sp!, {pc} @ calculate offset of PC in STMIA instruction
ldr r0, [sp], #4
@ -85,7 +85,7 @@ ENTRY(c_backtrace)
* A zero next framepointer means we're done.
*/
teq next, #0
LOADREGS(eqfd, sp!, {r4 - r8, pc})
ldmeqfd sp!, {r4 - r8, pc}
/*
* The next framepointer must be above the
@ -104,7 +104,7 @@ ENTRY(c_backtrace)
1007: ldr r0, =.Lbad
mov r1, frame
bl printk
LOADREGS(fd, sp!, {r4 - r8, pc})
ldmfd sp!, {r4 - r8, pc}
.ltorg
.previous
@ -145,7 +145,7 @@ ENTRY(c_backtrace)
adrne r0, .Lcr
blne printk
mov r0, stack
LOADREGS(fd, sp!, {instr, reg, stack, r7, r8, pc})
ldmfd sp!, {instr, reg, stack, r7, r8, pc}
.Lfp: .asciz " r%d = %08X%c"
.Lcr: .asciz "\n"

4
arch/arm/lib/clear_user.S
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@ -43,10 +43,10 @@ USER( strnebt r2, [r0], #1)
tst r1, #1 @ x1 x0 x1 x0 x1 x0 x1
USER( strnebt r2, [r0], #1)
mov r0, #0
LOADREGS(fd,sp!, {r1, pc})
ldmfd sp!, {r1, pc}
.section .fixup,"ax"
.align 0
9001: LOADREGS(fd,sp!, {r0, pc})
9001: ldmfd sp!, {r0, pc}
.previous

2
arch/arm/lib/copy_page.S
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@ -43,4 +43,4 @@ ENTRY(copy_page)
bgt 1b @ 1
PLD( ldmeqia r1!, {r3, r4, ip, lr} )
PLD( beq 2b )
LOADREGS(fd, sp!, {r4, pc}) @ 3
ldmfd sp!, {r4, pc} @ 3

2
arch/arm/lib/csumipv6.S
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@ -28,5 +28,5 @@ ENTRY(__csum_ipv6_magic)
adcs r0, r0, r3
adcs r0, r0, r2
adcs r0, r0, #0
LOADREGS(fd, sp!, {pc})
ldmfd sp!, {pc}

4
arch/arm/lib/ecard.S
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@ -29,7 +29,7 @@ ENTRY(ecard_loader_read)
CPSR2SPSR(r0)
mov lr, pc
mov pc, r2
LOADREGS(fd, sp!, {r4 - r12, pc})
ldmfd sp!, {r4 - r12, pc}
@ Purpose: call an expansion card loader to reset the card
@ Proto : void read_loader(int card_base, char *loader);
@ -41,5 +41,5 @@ ENTRY(ecard_loader_reset)
CPSR2SPSR(r0)
mov lr, pc
add pc, r1, #8
LOADREGS(fd, sp!, {r4 - r12, pc})
ldmfd sp!, {r4 - r12, pc}

6
arch/arm/lib/io-readsb.S
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@ -72,7 +72,7 @@ ENTRY(__raw_readsb)
bpl .Linsb_16_lp
tst r2, #15
LOADREGS(eqfd, sp!, {r4 - r6, pc})
ldmeqfd sp!, {r4 - r6, pc}
.Linsb_no_16: tst r2, #8
beq .Linsb_no_8
@ -109,7 +109,7 @@ ENTRY(__raw_readsb)
str r3, [r1], #4
.Linsb_no_4: ands r2, r2, #3
LOADREGS(eqfd, sp!, {r4 - r6, pc})
ldmeqfd sp!, {r4 - r6, pc}
cmp r2, #2
ldrb r3, [r0]
@ -119,4 +119,4 @@ ENTRY(__raw_readsb)
ldrgtb r3, [r0]
strgtb r3, [r1]
LOADREGS(fd, sp!, {r4 - r6, pc})
ldmfd sp!, {r4 - r6, pc}

4
arch/arm/lib/io-readsw-armv3.S
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@ -69,7 +69,7 @@ ENTRY(__raw_readsw)
bpl .Linsw_8_lp
tst r2, #7
LOADREGS(eqfd, sp!, {r4, r5, r6, pc})
ldmeqfd sp!, {r4, r5, r6, pc}
.Lno_insw_8: tst r2, #4
beq .Lno_insw_4
@ -102,6 +102,6 @@ ENTRY(__raw_readsw)
movne r3, r3, lsr #8
strneb r3, [r1]
LOADREGS(fd, sp!, {r4, r5, r6, pc})
ldmfd sp!, {r4, r5, r6, pc}

6
arch/arm/lib/io-writesb.S
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@ -64,7 +64,7 @@ ENTRY(__raw_writesb)
bpl .Loutsb_16_lp
tst r2, #15
LOADREGS(eqfd, sp!, {r4, r5, pc})
ldmeqfd sp!, {r4, r5, pc}
.Loutsb_no_16: tst r2, #8
beq .Loutsb_no_8
@ -80,7 +80,7 @@ ENTRY(__raw_writesb)
outword r3
.Loutsb_no_4: ands r2, r2, #3
LOADREGS(eqfd, sp!, {r4, r5, pc})
ldmeqfd sp!, {r4, r5, pc}
cmp r2, #2
ldrb r3, [r1], #1
@ -90,4 +90,4 @@ ENTRY(__raw_writesb)
ldrgtb r3, [r1]
strgtb r3, [r0]
LOADREGS(fd, sp!, {r4, r5, pc})
ldmfd sp!, {r4, r5, pc}

4
arch/arm/lib/io-writesw-armv3.S
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@ -80,7 +80,7 @@ ENTRY(__raw_writesw)
bpl .Loutsw_8_lp
tst r2, #7
LOADREGS(eqfd, sp!, {r4, r5, r6, pc})
ldmeqfd sp!, {r4, r5, r6, pc}
.Lno_outsw_8: tst r2, #4
beq .Lno_outsw_4
@ -124,4 +124,4 @@ ENTRY(__raw_writesw)
orrne ip, ip, ip, lsr #16
strne ip, [r0]
LOADREGS(fd, sp!, {r4, r5, r6, pc})
ldmfd sp!, {r4, r5, r6, pc}

2
arch/arm/lib/memset.S
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@ -53,7 +53,7 @@ ENTRY(memset)
stmgeia r0!, {r1, r3, ip, lr}
stmgeia r0!, {r1, r3, ip, lr}
bgt 2b
LOADREGS(eqfd, sp!, {pc}) @ Now <64 bytes to go.
ldmeqfd sp!, {pc} @ Now <64 bytes to go.
/*
* No need to correct the count; we're only testing bits from now on
*/

2
arch/arm/lib/memzero.S
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@ -53,7 +53,7 @@ ENTRY(__memzero)
stmgeia r0!, {r2, r3, ip, lr} @ 4
stmgeia r0!, {r2, r3, ip, lr} @ 4
bgt 3b @ 1
LOADREGS(eqfd, sp!, {pc}) @ 1/2 quick exit
ldmeqfd sp!, {pc} @ 1/2 quick exit
/*
* No need to correct the count; we're only testing bits from now on
*/

8
arch/arm/lib/uaccess.S
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@ -105,7 +105,7 @@ USER( strgtbt r3, [r0], #1) @ May fault
movs ip, r2
bne .Lc2u_nowords
.Lc2u_finished: mov r0, #0
LOADREGS(fd,sp!,{r2, r4 - r7, pc})
ldmfd sp!, {r2, r4 - r7, pc}
.Lc2u_src_not_aligned:
bic r1, r1, #3
@ -280,7 +280,7 @@ USER( strgtbt r3, [r0], #1) @ May fault
.section .fixup,"ax"
.align 0
9001: LOADREGS(fd,sp!, {r0, r4 - r7, pc})
9001: ldmfd sp!, {r0, r4 - r7, pc}
.previous
/* Prototype: unsigned long __arch_copy_from_user(void *to,const void *from,unsigned long n);
@ -369,7 +369,7 @@ USER( ldrgtbt r3, [r1], #1) @ May fault
bne .Lcfu_nowords
.Lcfu_finished: mov r0, #0
add sp, sp, #8
LOADREGS(fd,sp!,{r4 - r7, pc})
ldmfd sp!, {r4 - r7, pc}
.Lcfu_src_not_aligned:
bic r1, r1, #3
@ -556,6 +556,6 @@ USER( ldrgtbt r3, [r1], #1) @ May fault
movne r1, r4
blne __memzero
mov r0, r4
LOADREGS(fd,sp!, {r4 - r7, pc})
ldmfd sp!, {r4 - r7, pc}
.previous

2
arch/arm/mm/copypage-v3.S
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@ -35,7 +35,7 @@ ENTRY(v3_copy_user_page)
stmia r0!, {r3, r4, ip, lr} @ 4
ldmneia r1!, {r3, r4, ip, lr} @ 4
bne 1b @ 1
LOADREGS(fd, sp!, {r4, pc}) @ 3
ldmfd sp!, {r4, pc} @ 3
.align 5
/*

11
include/asm-arm/assembler.h
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@ -62,17 +62,6 @@
#define DEFAULT_FIQ MODE_FIQ
/*
* LOADREGS - ldm with PC in register list (eg, ldmfd sp!, {pc})
*/
#ifdef __STDC__
#define LOADREGS(cond, base, reglist...)\
ldm##cond base,reglist
#else
#define LOADREGS(cond, base, reglist...)\
ldm/**/cond base,reglist
#endif
/*
* Enable and disable interrupts
*/