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interconnect changes for 5.17

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Here are the interconnect changes for the 5.17-rc1 merge window
 consisting of new drivers, minor changes and fixes.
 
 New drivers:
  - New driver for MSM8996 platforms
  - New driver for SC7280 EPSS L3 hardware
  - New driver for QCM2290 platforms
  - New driver for SM8450 platforms
 
 Driver changes:
  - dt-bindings: interconnect: Combine SDM660 bindings into RPM schema
  - icc-rpm: Add support for bus power domain
  - icc-rpm: Use NOC_QOS_MODE_INVALID for qos_mode check
  - icc-rpm: Define ICC device type
  - icc-rpm: Add QNOC type QoS support
  - icc-rpm: Support child NoC device probe
  - icc-rpm: Prevent integer overflow in rate
  - icc-rpmh: Add BCMs to commit list in pre_aggregate
 
 Signed-off-by: Georgi Djakov <djakov@kernel.org>
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Merge tag 'icc-5.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc into char-misc-next

Georgi writes:

interconnect changes for 5.17

Here are the interconnect changes for the 5.17-rc1 merge window
consisting of new drivers, minor changes and fixes.

New drivers:
 - New driver for MSM8996 platforms
 - New driver for SC7280 EPSS L3 hardware
 - New driver for QCM2290 platforms
 - New driver for SM8450 platforms

Driver changes:
 - dt-bindings: interconnect: Combine SDM660 bindings into RPM schema
 - icc-rpm: Add support for bus power domain
 - icc-rpm: Use NOC_QOS_MODE_INVALID for qos_mode check
 - icc-rpm: Define ICC device type
 - icc-rpm: Add QNOC type QoS support
 - icc-rpm: Support child NoC device probe
 - icc-rpm: Prevent integer overflow in rate
 - icc-rpmh: Add BCMs to commit list in pre_aggregate

Signed-off-by: Georgi Djakov <djakov@kernel.org>

* tag 'icc-5.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc:
  interconnect: qcom: Add QCM2290 driver support
  dt-bindings: interconnect: Add Qualcomm QCM2290 NoC support
  interconnect: icc-rpm: Support child NoC device probe
  interconnect: icc-rpm: Add QNOC type QoS support
  interconnect: icc-rpm: Define ICC device type
  interconnect: qcom: Add SM8450 interconnect provider driver
  dt-bindings: interconnect: Add Qualcomm SM8450 DT bindings
  interconnect: qcom: rpm: Prevent integer overflow in rate
  interconnect: icc-rpm: Use NOC_QOS_MODE_INVALID for qos_mode check
  interconnect: qcom: icc-rpmh: Add BCMs to commit list in pre_aggregate
  interconnect: qcom: Add MSM8996 interconnect provider driver
  dt-bindings: interconnect: Add Qualcomm MSM8996 DT bindings
  interconnect: icc-rpm: Add support for bus power domain
  dt-bindings: interconnect: Combine SDM660 bindings into RPM schema
  interconnect: qcom: Add EPSS L3 support on SC7280
  dt-bindings: interconnect: Add EPSS L3 DT binding on SC7280
This commit is contained in:
Greg Kroah-Hartman 2021-12-27 10:23:35 +01:00
commit 1bc4deedc2
26 changed files with 6633 additions and 215 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
View File

@ -18,6 +18,7 @@ properties:
compatible:
enum:
- qcom,sc7180-osm-l3
- qcom,sc7280-epss-l3
- qcom,sc8180x-osm-l3
- qcom,sdm845-osm-l3
- qcom,sm8150-osm-l3

137
Documentation/devicetree/bindings/interconnect/qcom,qcm2290.yaml Normal file
View File

@ -0,0 +1,137 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interconnect/qcom,qcm2290.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm QCM2290 Network-On-Chip interconnect
maintainers:
- Shawn Guo <shawn.guo@linaro.org>
description: |
The Qualcomm QCM2290 interconnect providers support adjusting the
bandwidth requirements between the various NoC fabrics.
properties:
reg:
maxItems: 1
compatible:
enum:
- qcom,qcm2290-bimc
- qcom,qcm2290-cnoc
- qcom,qcm2290-snoc
'#interconnect-cells':
const: 1
clock-names:
items:
- const: bus
- const: bus_a
clocks:
items:
- description: Bus Clock
- description: Bus A Clock
# Child node's properties
patternProperties:
'^interconnect-[a-z0-9]+$':
type: object
description:
The interconnect providers do not have a separate QoS register space,
but share parent's space.
properties:
compatible:
enum:
- qcom,qcm2290-qup-virt
- qcom,qcm2290-mmrt-virt
- qcom,qcm2290-mmnrt-virt
'#interconnect-cells':
const: 1
clock-names:
items:
- const: bus
- const: bus_a
clocks:
items:
- description: Bus Clock
- description: Bus A Clock
required:
- compatible
- '#interconnect-cells'
- clock-names
- clocks
additionalProperties: false
required:
- compatible
- reg
- '#interconnect-cells'
- clock-names
- clocks
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmcc.h>
snoc: interconnect@1880000 {
compatible = "qcom,qcm2290-snoc";
reg = <0x01880000 0x60200>;
#interconnect-cells = <1>;
clock-names = "bus", "bus_a";
clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
<&rpmcc RPM_SMD_SNOC_A_CLK>;
qup_virt: interconnect-qup {
compatible = "qcom,qcm2290-qup-virt";
#interconnect-cells = <1>;
clock-names = "bus", "bus_a";
clocks = <&rpmcc RPM_SMD_QUP_CLK>,
<&rpmcc RPM_SMD_QUP_A_CLK>;
};
mmnrt_virt: interconnect-mmnrt {
compatible = "qcom,qcm2290-mmnrt-virt";
#interconnect-cells = <1>;
clock-names = "bus", "bus_a";
clocks = <&rpmcc RPM_SMD_MMNRT_CLK>,
<&rpmcc RPM_SMD_MMNRT_A_CLK>;
};
mmrt_virt: interconnect-mmrt {
compatible = "qcom,qcm2290-mmrt-virt";
#interconnect-cells = <1>;
clock-names = "bus", "bus_a";
clocks = <&rpmcc RPM_SMD_MMRT_CLK>,
<&rpmcc RPM_SMD_MMRT_A_CLK>;
};
};
cnoc: interconnect@1900000 {
compatible = "qcom,qcm2290-cnoc";
reg = <0x01900000 0x8200>;
#interconnect-cells = <1>;
clock-names = "bus", "bus_a";
clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
<&rpmcc RPM_SMD_CNOC_A_CLK>;
};
bimc: interconnect@4480000 {
compatible = "qcom,qcm2290-bimc";
reg = <0x04480000 0x80000>;
#interconnect-cells = <1>;
clock-names = "bus", "bus_a";
clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
<&rpmcc RPM_SMD_BIMC_A_CLK>;
};

145
Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml
View File

@ -27,22 +27,37 @@ properties:
- qcom,msm8939-pcnoc
- qcom,msm8939-snoc
- qcom,msm8939-snoc-mm
- qcom,msm8996-a0noc
- qcom,msm8996-a1noc
- qcom,msm8996-a2noc
- qcom,msm8996-bimc
- qcom,msm8996-cnoc
- qcom,msm8996-mnoc
- qcom,msm8996-pnoc
- qcom,msm8996-snoc
- qcom,qcs404-bimc
- qcom,qcs404-pcnoc
- qcom,qcs404-snoc
- qcom,sdm660-a2noc
- qcom,sdm660-bimc
- qcom,sdm660-cnoc
- qcom,sdm660-gnoc
- qcom,sdm660-mnoc
- qcom,sdm660-snoc
'#interconnect-cells':
const: 1
clock-names:
items:
- const: bus
- const: bus_a
clocks:
items:
- description: Bus Clock
- description: Bus A Clock
minItems: 2
maxItems: 7
clock-names:
minItems: 2
maxItems: 7
power-domains:
maxItems: 1
required:
- compatible
@ -53,6 +68,120 @@ required:
additionalProperties: false
allOf:
- if:
properties:
compatible:
contains:
enum:
- qcom,msm8916-bimc
- qcom,msm8916-pcnoc
- qcom,msm8916-snoc
- qcom,msm8939-bimc
- qcom,msm8939-pcnoc
- qcom,msm8939-snoc
- qcom,msm8939-snoc-mm
- qcom,msm8996-a1noc
- qcom,msm8996-a2noc
- qcom,msm8996-bimc
- qcom,msm8996-cnoc
- qcom,msm8996-pnoc
- qcom,msm8996-snoc
- qcom,qcs404-bimc
- qcom,qcs404-pcnoc
- qcom,qcs404-snoc
- qcom,sdm660-bimc
- qcom,sdm660-cnoc
- qcom,sdm660-gnoc
- qcom,sdm660-snoc
then:
properties:
clock-names:
items:
- const: bus
- const: bus_a
clocks:
items:
- description: Bus Clock
- description: Bus A Clock
- if:
properties:
compatible:
contains:
enum:
- qcom,msm8996-mnoc
- qcom,sdm660-mnoc
then:
properties:
clock-names:
items:
- const: bus
- const: bus_a
- const: iface
clocks:
items:
- description: Bus Clock.
- description: Bus A Clock.
- description: CPU-NoC High-performance Bus Clock.
- if:
properties:
compatible:
contains:
enum:
- qcom,msm8996-a0noc
then:
properties:
clock-names:
items:
- const: aggre0_snoc_axi
- const: aggre0_cnoc_ahb
- const: aggre0_noc_mpu_cfg
clocks:
items:
- description: Aggregate0 System NoC AXI Clock.
- description: Aggregate0 Config NoC AHB Clock.
- description: Aggregate0 NoC MPU Clock.
required:
- power-domains
- if:
properties:
compatible:
contains:
enum:
- qcom,sdm660-a2noc
then:
properties:
clock-names:
items:
- const: bus
- const: bus_a
- const: ipa
- const: ufs_axi
- const: aggre2_ufs_axi
- const: aggre2_usb3_axi
- const: cfg_noc_usb2_axi
clocks:
items:
- description: Bus Clock.
- description: Bus A Clock.
- description: IPA Clock.
- description: UFS AXI Clock.
- description: Aggregate2 UFS AXI Clock.
- description: Aggregate2 USB3 AXI Clock.
- description: Config NoC USB2 AXI Clock.
examples:
- |
#include <dt-bindings/clock/qcom,rpmcc.h>

11
Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml
View File

@ -104,6 +104,17 @@ properties:
- qcom,sm8350-mmss-noc
- qcom,sm8350-compute-noc
- qcom,sm8350-system-noc
- qcom,sm8450-aggre1-noc
- qcom,sm8450-aggre2-noc
- qcom,sm8450-clk-virt
- qcom,sm8450-config-noc
- qcom,sm8450-gem-noc
- qcom,sm8450-lpass-ag-noc
- qcom,sm8450-mc-virt
- qcom,sm8450-mmss-noc
- qcom,sm8450-nsp-noc
- qcom,sm8450-pcie-anoc
- qcom,sm8450-system-noc
'#interconnect-cells':
enum: [ 1, 2 ]

185
Documentation/devicetree/bindings/interconnect/qcom,sdm660.yaml
View File

@ -1,185 +0,0 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interconnect/qcom,sdm660.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SDM660 Network-On-Chip interconnect
maintainers:
- AngeloGioacchino Del Regno <kholk11@gmail.com>
description: |
The Qualcomm SDM660 interconnect providers support adjusting the
bandwidth requirements between the various NoC fabrics.
properties:
reg:
maxItems: 1
compatible:
enum:
- qcom,sdm660-a2noc
- qcom,sdm660-bimc
- qcom,sdm660-cnoc
- qcom,sdm660-gnoc
- qcom,sdm660-mnoc
- qcom,sdm660-snoc
'#interconnect-cells':
const: 1
clocks:
minItems: 1
maxItems: 7
clock-names:
minItems: 1
maxItems: 7
required:
- compatible
- reg
- '#interconnect-cells'
- clock-names
- clocks
additionalProperties: false
allOf:
- if:
properties:
compatible:
contains:
enum:
- qcom,sdm660-mnoc
then:
properties:
clocks:
items:
- description: Bus Clock.
- description: Bus A Clock.
- description: CPU-NoC High-performance Bus Clock.
clock-names:
items:
- const: bus
- const: bus_a
- const: iface
- if:
properties:
compatible:
contains:
enum:
- qcom,sdm660-a2noc
then:
properties:
clocks:
items:
- description: Bus Clock.
- description: Bus A Clock.
- description: IPA Clock.
- description: UFS AXI Clock.
- description: Aggregate2 UFS AXI Clock.
- description: Aggregate2 USB3 AXI Clock.
- description: Config NoC USB2 AXI Clock.
clock-names:
items:
- const: bus
- const: bus_a
- const: ipa
- const: ufs_axi
- const: aggre2_ufs_axi
- const: aggre2_usb3_axi
- const: cfg_noc_usb2_axi
- if:
properties:
compatible:
contains:
enum:
- qcom,sdm660-bimc
- qcom,sdm660-cnoc
- qcom,sdm660-gnoc
- qcom,sdm660-snoc
then:
properties:
clocks:
items:
- description: Bus Clock.
- description: Bus A Clock.
clock-names:
items:
- const: bus
- const: bus_a
examples:
- |
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/clock/qcom,mmcc-sdm660.h>
#include <dt-bindings/clock/qcom,gcc-sdm660.h>
bimc: interconnect@1008000 {
compatible = "qcom,sdm660-bimc";
reg = <0x01008000 0x78000>;
#interconnect-cells = <1>;
clock-names = "bus", "bus_a";
clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
<&rpmcc RPM_SMD_BIMC_A_CLK>;
};
cnoc: interconnect@1500000 {
compatible = "qcom,sdm660-cnoc";
reg = <0x01500000 0x10000>;
#interconnect-cells = <1>;
clock-names = "bus", "bus_a";
clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
<&rpmcc RPM_SMD_CNOC_A_CLK>;
};
snoc: interconnect@1626000 {
compatible = "qcom,sdm660-snoc";
reg = <0x01626000 0x7090>;
#interconnect-cells = <1>;
clock-names = "bus", "bus_a";
clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
<&rpmcc RPM_SMD_SNOC_A_CLK>;
};
a2noc: interconnect@1704000 {
compatible = "qcom,sdm660-a2noc";
reg = <0x01704000 0xc100>;
#interconnect-cells = <1>;
clock-names = "bus",
"bus_a",
"ipa",
"ufs_axi",
"aggre2_ufs_axi",
"aggre2_usb3_axi",
"cfg_noc_usb2_axi";
clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>,
<&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>,
<&rpmcc RPM_SMD_IPA_CLK>,
<&gcc GCC_UFS_AXI_CLK>,
<&gcc GCC_AGGRE2_UFS_AXI_CLK>,
<&gcc GCC_AGGRE2_USB3_AXI_CLK>,
<&gcc GCC_CFG_NOC_USB2_AXI_CLK>;
};
mnoc: interconnect@1745000 {
compatible = "qcom,sdm660-mnoc";
reg = <0x01745000 0xa010>;
#interconnect-cells = <1>;
clock-names = "bus", "bus_a", "iface";
clocks = <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK>,
<&rpmcc RPM_SMD_MMSSNOC_AXI_CLK_A>,
<&mmcc AHB_CLK_SRC>;
};
gnoc: interconnect@17900000 {
compatible = "qcom,sdm660-gnoc";
reg = <0x17900000 0xe000>;
#interconnect-cells = <1>;
clock-names = "bus", "bus_a";
clocks = <&xo_board>, <&xo_board>;
};

27
drivers/interconnect/qcom/Kconfig
View File

@ -35,6 +35,15 @@ config INTERCONNECT_QCOM_MSM8974
This is a driver for the Qualcomm Network-on-Chip on msm8974-based
platforms.
config INTERCONNECT_QCOM_MSM8996
tristate "Qualcomm MSM8996 interconnect driver"
depends on INTERCONNECT_QCOM
depends on QCOM_SMD_RPM
select INTERCONNECT_QCOM_SMD_RPM
help
This is a driver for the Qualcomm Network-on-Chip on msm8996-based
platforms.
config INTERCONNECT_QCOM_OSM_L3
tristate "Qualcomm OSM L3 interconnect driver"
depends on INTERCONNECT_QCOM || COMPILE_TEST
@ -42,6 +51,15 @@ config INTERCONNECT_QCOM_OSM_L3
Say y here to support the Operating State Manager (OSM) interconnect
driver which controls the scaling of L3 caches on Qualcomm SoCs.
config INTERCONNECT_QCOM_QCM2290
tristate "Qualcomm QCM2290 interconnect driver"
depends on INTERCONNECT_QCOM
depends on QCOM_SMD_RPM
select INTERCONNECT_QCOM_SMD_RPM
help
This is a driver for the Qualcomm Network-on-Chip on qcm2290-based
platforms.
config INTERCONNECT_QCOM_QCS404
tristate "Qualcomm QCS404 interconnect driver"
depends on INTERCONNECT_QCOM
@ -146,5 +164,14 @@ config INTERCONNECT_QCOM_SM8350
This is a driver for the Qualcomm Network-on-Chip on SM8350-based
platforms.
config INTERCONNECT_QCOM_SM8450
tristate "Qualcomm SM8450 interconnect driver"
depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
select INTERCONNECT_QCOM_RPMH
select INTERCONNECT_QCOM_BCM_VOTER
help
This is a driver for the Qualcomm Network-on-Chip on SM8450-based
platforms.
config INTERCONNECT_QCOM_SMD_RPM
tristate

6
drivers/interconnect/qcom/Makefile
View File

@ -4,7 +4,9 @@ icc-bcm-voter-objs := bcm-voter.o
qnoc-msm8916-objs := msm8916.o
qnoc-msm8939-objs := msm8939.o
qnoc-msm8974-objs := msm8974.o
qnoc-msm8996-objs := msm8996.o
icc-osm-l3-objs := osm-l3.o
qnoc-qcm2290-objs := qcm2290.o
qnoc-qcs404-objs := qcs404.o
icc-rpmh-obj := icc-rpmh.o
qnoc-sc7180-objs := sc7180.o
@ -16,13 +18,16 @@ qnoc-sdx55-objs := sdx55.o
qnoc-sm8150-objs := sm8150.o
qnoc-sm8250-objs := sm8250.o
qnoc-sm8350-objs := sm8350.o
qnoc-sm8450-objs := sm8450.o
icc-smd-rpm-objs := smd-rpm.o icc-rpm.o
obj-$(CONFIG_INTERCONNECT_QCOM_BCM_VOTER) += icc-bcm-voter.o
obj-$(CONFIG_INTERCONNECT_QCOM_MSM8916) += qnoc-msm8916.o
obj-$(CONFIG_INTERCONNECT_QCOM_MSM8939) += qnoc-msm8939.o
obj-$(CONFIG_INTERCONNECT_QCOM_MSM8974) += qnoc-msm8974.o
obj-$(CONFIG_INTERCONNECT_QCOM_MSM8996) += qnoc-msm8996.o
obj-$(CONFIG_INTERCONNECT_QCOM_OSM_L3) += icc-osm-l3.o
obj-$(CONFIG_INTERCONNECT_QCOM_QCM2290) += qnoc-qcm2290.o
obj-$(CONFIG_INTERCONNECT_QCOM_QCS404) += qnoc-qcs404.o
obj-$(CONFIG_INTERCONNECT_QCOM_RPMH) += icc-rpmh.o
obj-$(CONFIG_INTERCONNECT_QCOM_SC7180) += qnoc-sc7180.o
@ -34,4 +39,5 @@ obj-$(CONFIG_INTERCONNECT_QCOM_SDX55) += qnoc-sdx55.o
obj-$(CONFIG_INTERCONNECT_QCOM_SM8150) += qnoc-sm8150.o
obj-$(CONFIG_INTERCONNECT_QCOM_SM8250) += qnoc-sm8250.o
obj-$(CONFIG_INTERCONNECT_QCOM_SM8350) += qnoc-sm8350.o
obj-$(CONFIG_INTERCONNECT_QCOM_SM8450) += qnoc-sm8450.o
obj-$(CONFIG_INTERCONNECT_QCOM_SMD_RPM) += icc-smd-rpm.o

64
drivers/interconnect/qcom/icc-rpm.c
View File

@ -11,12 +11,20 @@
#include <linux/of_device.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include "smd-rpm.h"
#include "icc-rpm.h"
/* QNOC QoS */
#define QNOC_QOS_MCTL_LOWn_ADDR(n) (0x8 + (n * 0x1000))
#define QNOC_QOS_MCTL_DFLT_PRIO_MASK 0x70
#define QNOC_QOS_MCTL_DFLT_PRIO_SHIFT 4
#define QNOC_QOS_MCTL_URGFWD_EN_MASK 0x8
#define QNOC_QOS_MCTL_URGFWD_EN_SHIFT 3
/* BIMC QoS */
#define M_BKE_REG_BASE(n) (0x300 + (0x4000 * n))
#define M_BKE_EN_ADDR(n) (M_BKE_REG_BASE(n))
@ -39,6 +47,27 @@
#define NOC_QOS_MODEn_ADDR(n) (0xc + (n * 0x1000))
#define NOC_QOS_MODEn_MASK 0x3
static int qcom_icc_set_qnoc_qos(struct icc_node *src, u64 max_bw)
{
struct icc_provider *provider = src->provider;
struct qcom_icc_provider *qp = to_qcom_provider(provider);
struct qcom_icc_node *qn = src->data;
struct qcom_icc_qos *qos = &qn->qos;
int rc;
rc = regmap_update_bits(qp->regmap,
qp->qos_offset + QNOC_QOS_MCTL_LOWn_ADDR(qos->qos_port),
QNOC_QOS_MCTL_DFLT_PRIO_MASK,
qos->areq_prio << QNOC_QOS_MCTL_DFLT_PRIO_SHIFT);
if (rc)
return rc;
return regmap_update_bits(qp->regmap,
qp->qos_offset + QNOC_QOS_MCTL_LOWn_ADDR(qos->qos_port),
QNOC_QOS_MCTL_URGFWD_EN_MASK,
!!qos->urg_fwd_en << QNOC_QOS_MCTL_URGFWD_EN_SHIFT);
}
static int qcom_icc_bimc_set_qos_health(struct qcom_icc_provider *qp,
struct qcom_icc_qos *qos,
int regnum)
@ -76,7 +105,7 @@ static int qcom_icc_set_bimc_qos(struct icc_node *src, u64 max_bw)
provider = src->provider;
qp = to_qcom_provider(provider);
if (qn->qos.qos_mode != -1)
if (qn->qos.qos_mode != NOC_QOS_MODE_INVALID)
mode = qn->qos.qos_mode;
/* QoS Priority: The QoS Health parameters are getting considered
@ -137,7 +166,7 @@ static int qcom_icc_set_noc_qos(struct icc_node *src, u64 max_bw)
return 0;
}
if (qn->qos.qos_mode != -1)
if (qn->qos.qos_mode != NOC_QOS_MODE_INVALID)
mode = qn->qos.qos_mode;
if (mode == NOC_QOS_MODE_FIXED) {
@ -163,10 +192,14 @@ static int qcom_icc_qos_set(struct icc_node *node, u64 sum_bw)
dev_dbg(node->provider->dev, "Setting QoS for %s\n", qn->name);
if (qp->is_bimc_node)
switch (qp->type) {
case QCOM_ICC_BIMC:
return qcom_icc_set_bimc_qos(node, sum_bw);
return qcom_icc_set_noc_qos(node, sum_bw);
case QCOM_ICC_QNOC:
return qcom_icc_set_qnoc_qos(node, sum_bw);
default:
return qcom_icc_set_noc_qos(node, sum_bw);
}
}
static int qcom_icc_rpm_set(int mas_rpm_id, int slv_rpm_id, u64 sum_bw)
@ -239,6 +272,7 @@ static int qcom_icc_set(struct icc_node *src, struct icc_node *dst)
rate = max(sum_bw, max_peak_bw);
do_div(rate, qn->buswidth);
rate = min_t(u64, rate, LONG_MAX);
if (qn->rate == rate)
return 0;
@ -307,7 +341,7 @@ int qnoc_probe(struct platform_device *pdev)
qp->bus_clks[i].id = cds[i];
qp->num_clks = cd_num;
qp->is_bimc_node = desc->is_bimc_node;
qp->type = desc->type;
qp->qos_offset = desc->qos_offset;
if (desc->regmap_cfg) {
@ -315,8 +349,13 @@ int qnoc_probe(struct platform_device *pdev)
void __iomem *mmio;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res)
if (!res) {
/* Try parent's regmap */
qp->regmap = dev_get_regmap(dev->parent, NULL);
if (qp->regmap)
goto regmap_done;
return -ENODEV;
}
mmio = devm_ioremap_resource(dev, res);
@ -332,6 +371,7 @@ int qnoc_probe(struct platform_device *pdev)
}
}
regmap_done:
ret = devm_clk_bulk_get(dev, qp->num_clks, qp->bus_clks);
if (ret)
return ret;
@ -340,6 +380,12 @@ int qnoc_probe(struct platform_device *pdev)
if (ret)
return ret;
if (desc->has_bus_pd) {
ret = dev_pm_domain_attach(dev, true);
if (ret)
return ret;
}
provider = &qp->provider;
INIT_LIST_HEAD(&provider->nodes);
provider->dev = dev;
@ -377,6 +423,10 @@ int qnoc_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, qp);
/* Populate child NoC devices if any */
if (of_get_child_count(dev->of_node) > 0)
return of_platform_populate(dev->of_node, NULL, NULL, dev);
return 0;
err:
icc_nodes_remove(provider);

15
drivers/interconnect/qcom/icc-rpm.h
View File

@ -12,19 +12,25 @@
#define to_qcom_provider(_provider) \
container_of(_provider, struct qcom_icc_provider, provider)
enum qcom_icc_type {
QCOM_ICC_NOC,
QCOM_ICC_BIMC,
QCOM_ICC_QNOC,
};
/**
* struct qcom_icc_provider - Qualcomm specific interconnect provider
* @provider: generic interconnect provider
* @bus_clks: the clk_bulk_data table of bus clocks
* @num_clks: the total number of clk_bulk_data entries
* @is_bimc_node: indicates whether to use bimc specific setting
* @type: the ICC provider type
* @qos_offset: offset to QoS registers
* @regmap: regmap for QoS registers read/write access
*/
struct qcom_icc_provider {
struct icc_provider provider;
int num_clks;
bool is_bimc_node;
enum qcom_icc_type type;
struct regmap *regmap;
unsigned int qos_offset;
struct clk_bulk_data bus_clks[];
@ -38,6 +44,7 @@ struct qcom_icc_provider {
* @ap_owned: indicates if the node is owned by the AP or by the RPM
* @qos_mode: default qos mode for this node
* @qos_port: qos port number for finding qos registers of this node
* @urg_fwd_en: enable urgent forwarding
*/
struct qcom_icc_qos {
u32 areq_prio;
@ -46,6 +53,7 @@ struct qcom_icc_qos {
bool ap_owned;
int qos_mode;
int qos_port;
bool urg_fwd_en;
};
/**
@ -77,7 +85,8 @@ struct qcom_icc_desc {
size_t num_nodes;
const char * const *clocks;
size_t num_clocks;
bool is_bimc_node;
bool has_bus_pd;
enum qcom_icc_type type;
const struct regmap_config *regmap_cfg;
unsigned int qos_offset;
};

10
drivers/interconnect/qcom/icc-rpmh.c
View File

@ -21,13 +21,18 @@ void qcom_icc_pre_aggregate(struct icc_node *node)
{
size_t i;
struct qcom_icc_node *qn;
struct qcom_icc_provider *qp;
qn = node->data;
qp = to_qcom_provider(node->provider);
for (i = 0; i < QCOM_ICC_NUM_BUCKETS; i++) {
qn->sum_avg[i] = 0;
qn->max_peak[i] = 0;
}
for (i = 0; i < qn->num_bcms; i++)
qcom_icc_bcm_voter_add(qp->voter, qn->bcms[i]);
}
EXPORT_SYMBOL_GPL(qcom_icc_pre_aggregate);
@ -45,10 +50,8 @@ int qcom_icc_aggregate(struct icc_node *node, u32 tag, u32 avg_bw,
{
size_t i;
struct qcom_icc_node *qn;
struct qcom_icc_provider *qp;
qn = node->data;
qp = to_qcom_provider(node->provider);
if (!tag)
tag = QCOM_ICC_TAG_ALWAYS;
@ -68,9 +71,6 @@ int qcom_icc_aggregate(struct icc_node *node, u32 tag, u32 avg_bw,
*agg_avg += avg_bw;
*agg_peak = max_t(u32, *agg_peak, peak_bw);
for (i = 0; i < qn->num_bcms; i++)
qcom_icc_bcm_voter_add(qp->voter, qn->bcms[i]);
return 0;
}
EXPORT_SYMBOL_GPL(qcom_icc_aggregate);

4
drivers/interconnect/qcom/msm8916.c
View File

@ -1229,6 +1229,7 @@ static const struct regmap_config msm8916_snoc_regmap_config = {
};
static struct qcom_icc_desc msm8916_snoc = {
.type = QCOM_ICC_NOC,
.nodes = msm8916_snoc_nodes,
.num_nodes = ARRAY_SIZE(msm8916_snoc_nodes),
.regmap_cfg = &msm8916_snoc_regmap_config,
@ -1256,9 +1257,9 @@ static const struct regmap_config msm8916_bimc_regmap_config = {
};
static struct qcom_icc_desc msm8916_bimc = {
.type = QCOM_ICC_BIMC,
.nodes = msm8916_bimc_nodes,
.num_nodes = ARRAY_SIZE(msm8916_bimc_nodes),
.is_bimc_node = true,
.regmap_cfg = &msm8916_bimc_regmap_config,
.qos_offset = 0x8000,
};
@ -1325,6 +1326,7 @@ static const struct regmap_config msm8916_pcnoc_regmap_config = {
};
static struct qcom_icc_desc msm8916_pcnoc = {
.type = QCOM_ICC_NOC,
.nodes = msm8916_pcnoc_nodes,
.num_nodes = ARRAY_SIZE(msm8916_pcnoc_nodes),
.regmap_cfg = &msm8916_pcnoc_regmap_config,

5
drivers/interconnect/qcom/msm8939.c
View File

@ -1282,6 +1282,7 @@ static const struct regmap_config msm8939_snoc_regmap_config = {
};
static struct qcom_icc_desc msm8939_snoc = {
.type = QCOM_ICC_NOC,
.nodes = msm8939_snoc_nodes,
.num_nodes = ARRAY_SIZE(msm8939_snoc_nodes),
.regmap_cfg = &msm8939_snoc_regmap_config,
@ -1309,6 +1310,7 @@ static const struct regmap_config msm8939_snoc_mm_regmap_config = {
};
static struct qcom_icc_desc msm8939_snoc_mm = {
.type = QCOM_ICC_NOC,
.nodes = msm8939_snoc_mm_nodes,
.num_nodes = ARRAY_SIZE(msm8939_snoc_mm_nodes),
.regmap_cfg = &msm8939_snoc_mm_regmap_config,
@ -1336,9 +1338,9 @@ static const struct regmap_config msm8939_bimc_regmap_config = {
};
static struct qcom_icc_desc msm8939_bimc = {
.type = QCOM_ICC_BIMC,
.nodes = msm8939_bimc_nodes,
.num_nodes = ARRAY_SIZE(msm8939_bimc_nodes),
.is_bimc_node = true,
.regmap_cfg = &msm8939_bimc_regmap_config,
.qos_offset = 0x8000,
};
@ -1407,6 +1409,7 @@ static const struct regmap_config msm8939_pcnoc_regmap_config = {
};
static struct qcom_icc_desc msm8939_pcnoc = {
.type = QCOM_ICC_NOC,
.nodes = msm8939_pcnoc_nodes,
.num_nodes = ARRAY_SIZE(msm8939_pcnoc_nodes),
.regmap_cfg = &msm8939_pcnoc_regmap_config,

2110
drivers/interconnect/qcom/msm8996.c Normal file
View File

File diff suppressed because it is too large Load Diff

149
drivers/interconnect/qcom/msm8996.h Normal file
View File

@ -0,0 +1,149 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Qualcomm MSM8996 interconnect IDs
*
* Copyright (c) 2021 Yassine Oudjana <y.oudjana@protonmail.com>
*/
#ifndef __DRIVERS_INTERCONNECT_QCOM_MSM8996_H__
#define __DRIVERS_INTERCONNECT_QCOM_MSM8996_H__
#define MSM8996_MASTER_PCIE_0 1
#define MSM8996_MASTER_PCIE_1 2
#define MSM8996_MASTER_PCIE_2 3
#define MSM8996_MASTER_CNOC_A1NOC 4
#define MSM8996_MASTER_CRYPTO_CORE0 5
#define MSM8996_MASTER_PNOC_A1NOC 6
#define MSM8996_MASTER_USB3 7
#define MSM8996_MASTER_IPA 8
#define MSM8996_MASTER_UFS 9
#define MSM8996_MASTER_AMPSS_M0 10
#define MSM8996_MASTER_GRAPHICS_3D 11
#define MSM8996_MASTER_MNOC_BIMC 12
#define MSM8996_MASTER_SNOC_BIMC 13
#define MSM8996_MASTER_SNOC_CNOC 14
#define MSM8996_MASTER_QDSS_DAP 15
#define MSM8996_MASTER_CNOC_MNOC_MMSS_CFG 16
#define MSM8996_MASTER_CNOC_MNOC_CFG 17
#define MSM8996_MASTER_CPP 18
#define MSM8996_MASTER_JPEG 19
#define MSM8996_MASTER_MDP_PORT0 20
#define MSM8996_MASTER_MDP_PORT1 21
#define MSM8996_MASTER_ROTATOR 22
#define MSM8996_MASTER_VIDEO_P0 23
#define MSM8996_MASTER_VFE 24
#define MSM8996_MASTER_SNOC_VMEM 25
#define MSM8996_MASTER_VIDEO_P0_OCMEM 26
#define MSM8996_MASTER_SNOC_PNOC 27
#define MSM8996_MASTER_SDCC_1 28
#define MSM8996_MASTER_SDCC_2 29
#define MSM8996_MASTER_SDCC_4 30
#define MSM8996_MASTER_USB_HS 31
#define MSM8996_MASTER_BLSP_1 32
#define MSM8996_MASTER_BLSP_2 33
#define MSM8996_MASTER_TSIF 34
#define MSM8996_MASTER_HMSS 35
#define MSM8996_MASTER_QDSS_BAM 36
#define MSM8996_MASTER_SNOC_CFG 37
#define MSM8996_MASTER_BIMC_SNOC_0 38
#define MSM8996_MASTER_BIMC_SNOC_1 39
#define MSM8996_MASTER_A0NOC_SNOC 40
#define MSM8996_MASTER_A1NOC_SNOC 41
#define MSM8996_MASTER_A2NOC_SNOC 42
#define MSM8996_MASTER_QDSS_ETR 43
#define MSM8996_SLAVE_A0NOC_SNOC 44
#define MSM8996_SLAVE_A1NOC_SNOC 45
#define MSM8996_SLAVE_A2NOC_SNOC 46
#define MSM8996_SLAVE_EBI_CH0 47
#define MSM8996_SLAVE_HMSS_L3 48
#define MSM8996_SLAVE_BIMC_SNOC_0 49
#define MSM8996_SLAVE_BIMC_SNOC_1 50
#define MSM8996_SLAVE_CNOC_A1NOC 51
#define MSM8996_SLAVE_CLK_CTL 52
#define MSM8996_SLAVE_TCSR 53
#define MSM8996_SLAVE_TLMM 54
#define MSM8996_SLAVE_CRYPTO_0_CFG 55
#define MSM8996_SLAVE_MPM 56
#define MSM8996_SLAVE_PIMEM_CFG 57
#define MSM8996_SLAVE_IMEM_CFG 58
#define MSM8996_SLAVE_MESSAGE_RAM 59
#define MSM8996_SLAVE_BIMC_CFG 60
#define MSM8996_SLAVE_PMIC_ARB 61
#define MSM8996_SLAVE_PRNG 62
#define MSM8996_SLAVE_DCC_CFG 63
#define MSM8996_SLAVE_RBCPR_MX 64
#define MSM8996_SLAVE_QDSS_CFG 65
#define MSM8996_SLAVE_RBCPR_CX 66
#define MSM8996_SLAVE_QDSS_RBCPR_APU_CFG 67
#define MSM8996_SLAVE_CNOC_MNOC_CFG 68
#define MSM8996_SLAVE_SNOC_CFG 69
#define MSM8996_SLAVE_SNOC_MPU_CFG 70
#define MSM8996_SLAVE_EBI1_PHY_CFG 71
#define MSM8996_SLAVE_A0NOC_CFG 72
#define MSM8996_SLAVE_PCIE_1_CFG 73
#define MSM8996_SLAVE_PCIE_2_CFG 74
#define MSM8996_SLAVE_PCIE_0_CFG 75
#define MSM8996_SLAVE_PCIE20_AHB2PHY 76
#define MSM8996_SLAVE_A0NOC_MPU_CFG 77
#define MSM8996_SLAVE_UFS_CFG 78
#define MSM8996_SLAVE_A1NOC_CFG 79
#define MSM8996_SLAVE_A1NOC_MPU_CFG 80
#define MSM8996_SLAVE_A2NOC_CFG 81
#define MSM8996_SLAVE_A2NOC_MPU_CFG 82
#define MSM8996_SLAVE_SSC_CFG 83
#define MSM8996_SLAVE_A0NOC_SMMU_CFG 84
#define MSM8996_SLAVE_A1NOC_SMMU_CFG 85
#define MSM8996_SLAVE_A2NOC_SMMU_CFG 86
#define MSM8996_SLAVE_LPASS_SMMU_CFG 87
#define MSM8996_SLAVE_CNOC_MNOC_MMSS_CFG 88
#define MSM8996_SLAVE_MMAGIC_CFG 89
#define MSM8996_SLAVE_CPR_CFG 90
#define MSM8996_SLAVE_MISC_CFG 91
#define MSM8996_SLAVE_VENUS_THROTTLE_CFG 92
#define MSM8996_SLAVE_VENUS_CFG 93
#define MSM8996_SLAVE_VMEM_CFG 94
#define MSM8996_SLAVE_DSA_CFG 95
#define MSM8996_SLAVE_MMSS_CLK_CFG 96
#define MSM8996_SLAVE_DSA_MPU_CFG 97
#define MSM8996_SLAVE_MNOC_MPU_CFG 98
#define MSM8996_SLAVE_DISPLAY_CFG 99
#define MSM8996_SLAVE_DISPLAY_THROTTLE_CFG 100
#define MSM8996_SLAVE_CAMERA_CFG 101
#define MSM8996_SLAVE_CAMERA_THROTTLE_CFG 102
#define MSM8996_SLAVE_GRAPHICS_3D_CFG 103
#define MSM8996_SLAVE_SMMU_MDP_CFG 104
#define MSM8996_SLAVE_SMMU_ROTATOR_CFG 105
#define MSM8996_SLAVE_SMMU_VENUS_CFG 106
#define MSM8996_SLAVE_SMMU_CPP_CFG 107
#define MSM8996_SLAVE_SMMU_JPEG_CFG 108
#define MSM8996_SLAVE_SMMU_VFE_CFG 109
#define MSM8996_SLAVE_MNOC_BIMC 110
#define MSM8996_SLAVE_VMEM 111
#define MSM8996_SLAVE_SERVICE_MNOC 112
#define MSM8996_SLAVE_PNOC_A1NOC 113
#define MSM8996_SLAVE_USB_HS 114
#define MSM8996_SLAVE_SDCC_2 115
#define MSM8996_SLAVE_SDCC_4 116
#define MSM8996_SLAVE_TSIF 117
#define MSM8996_SLAVE_BLSP_2 118
#define MSM8996_SLAVE_SDCC_1 119
#define MSM8996_SLAVE_BLSP_1 120
#define MSM8996_SLAVE_PDM 121
#define MSM8996_SLAVE_AHB2PHY 122
#define MSM8996_SLAVE_APPSS 123
#define MSM8996_SLAVE_LPASS 124
#define MSM8996_SLAVE_USB3 125
#define MSM8996_SLAVE_SNOC_BIMC 126
#define MSM8996_SLAVE_SNOC_CNOC 127
#define MSM8996_SLAVE_OCIMEM 128
#define MSM8996_SLAVE_PIMEM 129
#define MSM8996_SLAVE_SNOC_VMEM 130
#define MSM8996_SLAVE_SNOC_PNOC 131
#define MSM8996_SLAVE_QDSS_STM 132
#define MSM8996_SLAVE_PCIE_0 133
#define MSM8996_SLAVE_PCIE_1 134
#define MSM8996_SLAVE_PCIE_2 135
#define MSM8996_SLAVE_SERVICE_SNOC 136
#endif /* __DRIVERS_INTERCONNECT_QCOM_MSM8996_H__ */

20
drivers/interconnect/qcom/osm-l3.c
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
*/
#include <linux/bitfield.h>
@ -15,6 +15,7 @@
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include "sc7180.h"
#include "sc7280.h"
#include "sc8180x.h"
#include "sdm845.h"
#include "sm8150.h"
@ -114,6 +115,22 @@ static const struct qcom_osm_l3_desc sc7180_icc_osm_l3 = {
.reg_perf_state = OSM_REG_PERF_STATE,
};
DEFINE_QNODE(sc7280_epss_apps_l3, SC7280_MASTER_EPSS_L3_APPS, 32, SC7280_SLAVE_EPSS_L3);
DEFINE_QNODE(sc7280_epss_l3, SC7280_SLAVE_EPSS_L3, 32);
static const struct qcom_osm_l3_node *sc7280_epss_l3_nodes[] = {
[MASTER_EPSS_L3_APPS] = &sc7280_epss_apps_l3,
[SLAVE_EPSS_L3_SHARED] = &sc7280_epss_l3,
};
static const struct qcom_osm_l3_desc sc7280_icc_epss_l3 = {
.nodes = sc7280_epss_l3_nodes,
.num_nodes = ARRAY_SIZE(sc7280_epss_l3_nodes),
.lut_row_size = EPSS_LUT_ROW_SIZE,
.reg_freq_lut = EPSS_REG_FREQ_LUT,
.reg_perf_state = EPSS_REG_PERF_STATE,
};
DEFINE_QNODE(sc8180x_osm_apps_l3, SC8180X_MASTER_OSM_L3_APPS, 32, SC8180X_SLAVE_OSM_L3);
DEFINE_QNODE(sc8180x_osm_l3, SC8180X_SLAVE_OSM_L3, 32);
@ -326,6 +343,7 @@ err:
static const struct of_device_id osm_l3_of_match[] = {
{ .compatible = "qcom,sc7180-osm-l3", .data = &sc7180_icc_osm_l3 },
{ .compatible = "qcom,sc7280-epss-l3", .data = &sc7280_icc_epss_l3 },
{ .compatible = "qcom,sdm845-osm-l3", .data = &sdm845_icc_osm_l3 },
{ .compatible = "qcom,sm8150-osm-l3", .data = &sm8150_icc_osm_l3 },
{ .compatible = "qcom,sc8180x-osm-l3", .data = &sc8180x_icc_osm_l3 },

1363
drivers/interconnect/qcom/qcm2290.c Normal file
View File

File diff suppressed because it is too large Load Diff

2
drivers/interconnect/qcom/sc7280.h
View File

@ -150,5 +150,7 @@
#define SC7280_SLAVE_PCIE_1 139
#define SC7280_SLAVE_QDSS_STM 140
#define SC7280_SLAVE_TCU 141
#define SC7280_MASTER_EPSS_L3_APPS 142
#define SC7280_SLAVE_EPSS_L3 143
#endif

7
drivers/interconnect/qcom/sdm660.c
View File

@ -1513,6 +1513,7 @@ static const struct regmap_config sdm660_a2noc_regmap_config = {
};
static struct qcom_icc_desc sdm660_a2noc = {
.type = QCOM_ICC_NOC,
.nodes = sdm660_a2noc_nodes,
.num_nodes = ARRAY_SIZE(sdm660_a2noc_nodes),
.clocks = bus_a2noc_clocks,
@ -1540,9 +1541,9 @@ static const struct regmap_config sdm660_bimc_regmap_config = {
};
static struct qcom_icc_desc sdm660_bimc = {
.type = QCOM_ICC_BIMC,
.nodes = sdm660_bimc_nodes,
.num_nodes = ARRAY_SIZE(sdm660_bimc_nodes),
.is_bimc_node = true,
.regmap_cfg = &sdm660_bimc_regmap_config,
};
@ -1594,6 +1595,7 @@ static const struct regmap_config sdm660_cnoc_regmap_config = {
};
static struct qcom_icc_desc sdm660_cnoc = {
.type = QCOM_ICC_NOC,
.nodes = sdm660_cnoc_nodes,
.num_nodes = ARRAY_SIZE(sdm660_cnoc_nodes),
.regmap_cfg = &sdm660_cnoc_regmap_config,
@ -1614,6 +1616,7 @@ static const struct regmap_config sdm660_gnoc_regmap_config = {
};
static struct qcom_icc_desc sdm660_gnoc = {
.type = QCOM_ICC_NOC,
.nodes = sdm660_gnoc_nodes,
.num_nodes = ARRAY_SIZE(sdm660_gnoc_nodes),
.regmap_cfg = &sdm660_gnoc_regmap_config,
@ -1653,6 +1656,7 @@ static const struct regmap_config sdm660_mnoc_regmap_config = {
};
static struct qcom_icc_desc sdm660_mnoc = {
.type = QCOM_ICC_NOC,
.nodes = sdm660_mnoc_nodes,
.num_nodes = ARRAY_SIZE(sdm660_mnoc_nodes),
.clocks = bus_mm_clocks,
@ -1689,6 +1693,7 @@ static const struct regmap_config sdm660_snoc_regmap_config = {
};
static struct qcom_icc_desc sdm660_snoc = {
.type = QCOM_ICC_NOC,
.nodes = sdm660_snoc_nodes,
.num_nodes = ARRAY_SIZE(sdm660_snoc_nodes),
.regmap_cfg = &sdm660_snoc_regmap_config,

1
drivers/interconnect/qcom/sm8150.c
View File

@ -535,7 +535,6 @@ static struct platform_driver qnoc_driver = {
.driver = {
.name = "qnoc-sm8150",
.of_match_table = qnoc_of_match,
.sync_state = icc_sync_state,
},
};
module_platform_driver(qnoc_driver);

1
drivers/interconnect/qcom/sm8250.c
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@ -551,7 +551,6 @@ static struct platform_driver qnoc_driver = {
.driver = {
.name = "qnoc-sm8250",
.of_match_table = qnoc_of_match,
.sync_state = icc_sync_state,
},
};
module_platform_driver(qnoc_driver);

1
drivers/interconnect/qcom/sm8350.c
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@ -531,7 +531,6 @@ static struct platform_driver qnoc_driver = {
.driver = {
.name = "qnoc-sm8350",
.of_match_table = qnoc_of_match,
.sync_state = icc_sync_state,
},
};
module_platform_driver(qnoc_driver);

1987
drivers/interconnect/qcom/sm8450.c Normal file
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169
drivers/interconnect/qcom/sm8450.h Normal file
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@ -0,0 +1,169 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* SM8450 interconnect IDs
*
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2021, Linaro Limited
*/
#ifndef __DRIVERS_INTERCONNECT_QCOM_SM8450_H
#define __DRIVERS_INTERCONNECT_QCOM_SM8450_H
#define SM8450_MASTER_GPU_TCU 0
#define SM8450_MASTER_SYS_TCU 1
#define SM8450_MASTER_APPSS_PROC 2
#define SM8450_MASTER_LLCC 3
#define SM8450_MASTER_CNOC_LPASS_AG_NOC 4
#define SM8450_MASTER_GIC_AHB 5
#define SM8450_MASTER_CDSP_NOC_CFG 6
#define SM8450_MASTER_QDSS_BAM 7
#define SM8450_MASTER_QSPI_0 8
#define SM8450_MASTER_QUP_0 9
#define SM8450_MASTER_QUP_1 10
#define SM8450_MASTER_QUP_2 11
#define SM8450_MASTER_A1NOC_CFG 12
#define SM8450_MASTER_A2NOC_CFG 13
#define SM8450_MASTER_A1NOC_SNOC 14
#define SM8450_MASTER_A2NOC_SNOC 15
#define SM8450_MASTER_CAMNOC_HF 16
#define SM8450_MASTER_CAMNOC_ICP 17
#define SM8450_MASTER_CAMNOC_SF 18
#define SM8450_MASTER_GEM_NOC_CNOC 19
#define SM8450_MASTER_GEM_NOC_PCIE_SNOC 20
#define SM8450_MASTER_GFX3D 21
#define SM8450_MASTER_LPASS_ANOC 22
#define SM8450_MASTER_MDP 23
#define SM8450_MASTER_MDP0 SM8450_MASTER_MDP
#define SM8450_MASTER_MDP1 SM8450_MASTER_MDP
#define SM8450_MASTER_MSS_PROC 24
#define SM8450_MASTER_CNOC_MNOC_CFG 25
#define SM8450_MASTER_MNOC_HF_MEM_NOC 26
#define SM8450_MASTER_MNOC_SF_MEM_NOC 27
#define SM8450_MASTER_COMPUTE_NOC 28
#define SM8450_MASTER_ANOC_PCIE_GEM_NOC 29
#define SM8450_MASTER_PCIE_ANOC_CFG 30
#define SM8450_MASTER_ROTATOR 31
#define SM8450_MASTER_SNOC_CFG 32
#define SM8450_MASTER_SNOC_GC_MEM_NOC 33
#define SM8450_MASTER_SNOC_SF_MEM_NOC 34
#define SM8450_MASTER_CDSP_HCP 35
#define SM8450_MASTER_VIDEO 36
#define SM8450_MASTER_VIDEO_P0 SM8450_MASTER_VIDEO
#define SM8450_MASTER_VIDEO_P1 SM8450_MASTER_VIDEO
#define SM8450_MASTER_VIDEO_CV_PROC 37
#define SM8450_MASTER_VIDEO_PROC 38
#define SM8450_MASTER_VIDEO_V_PROC 39
#define SM8450_MASTER_QUP_CORE_0 40
#define SM8450_MASTER_QUP_CORE_1 41
#define SM8450_MASTER_QUP_CORE_2 42
#define SM8450_MASTER_CRYPTO 43
#define SM8450_MASTER_IPA 44
#define SM8450_MASTER_LPASS_PROC 45
#define SM8450_MASTER_CDSP_PROC 46
#define SM8450_MASTER_PIMEM 47
#define SM8450_MASTER_SENSORS_PROC 48
#define SM8450_MASTER_SP 49
#define SM8450_MASTER_GIC 50
#define SM8450_MASTER_PCIE_0 51
#define SM8450_MASTER_PCIE_1 52
#define SM8450_MASTER_QDSS_ETR 53
#define SM8450_MASTER_QDSS_ETR_1 54
#define SM8450_MASTER_SDCC_2 55
#define SM8450_MASTER_SDCC_4 56
#define SM8450_MASTER_UFS_MEM 57
#define SM8450_MASTER_USB3_0 58
#define SM8450_SLAVE_EBI1 512
#define SM8450_SLAVE_AHB2PHY_SOUTH 513
#define SM8450_SLAVE_AHB2PHY_NORTH 514
#define SM8450_SLAVE_AOSS 515
#define SM8450_SLAVE_CAMERA_CFG 516
#define SM8450_SLAVE_CLK_CTL 517
#define SM8450_SLAVE_CDSP_CFG 518
#define SM8450_SLAVE_RBCPR_CX_CFG 519
#define SM8450_SLAVE_RBCPR_MMCX_CFG 520
#define SM8450_SLAVE_RBCPR_MXA_CFG 521
#define SM8450_SLAVE_RBCPR_MXC_CFG 522
#define SM8450_SLAVE_CRYPTO_0_CFG 523
#define SM8450_SLAVE_CX_RDPM 524
#define SM8450_SLAVE_DISPLAY_CFG 525
#define SM8450_SLAVE_GFX3D_CFG 526
#define SM8450_SLAVE_IMEM_CFG 527
#define SM8450_SLAVE_IPA_CFG 528
#define SM8450_SLAVE_IPC_ROUTER_CFG 529
#define SM8450_SLAVE_LPASS 530
#define SM8450_SLAVE_LPASS_CORE_CFG 531
#define SM8450_SLAVE_LPASS_LPI_CFG 532
#define SM8450_SLAVE_LPASS_MPU_CFG 533
#define SM8450_SLAVE_LPASS_TOP_CFG 534
#define SM8450_SLAVE_CNOC_MSS 535
#define SM8450_SLAVE_MX_RDPM 536
#define SM8450_SLAVE_PCIE_0_CFG 537
#define SM8450_SLAVE_PCIE_1_CFG 538
#define SM8450_SLAVE_PDM 539
#define SM8450_SLAVE_PIMEM_CFG 540
#define SM8450_SLAVE_PRNG 541
#define SM8450_SLAVE_QDSS_CFG 542
#define SM8450_SLAVE_QSPI_0 543
#define SM8450_SLAVE_QUP_0 544
#define SM8450_SLAVE_QUP_1 545
#define SM8450_SLAVE_QUP_2 546
#define SM8450_SLAVE_SDCC_2 547
#define SM8450_SLAVE_SDCC_4 548
#define SM8450_SLAVE_SPSS_CFG 549
#define SM8450_SLAVE_TCSR 550
#define SM8450_SLAVE_TLMM 551
#define SM8450_SLAVE_TME_CFG 552
#define SM8450_SLAVE_UFS_MEM_CFG 553
#define SM8450_SLAVE_USB3_0 554
#define SM8450_SLAVE_VENUS_CFG 555
#define SM8450_SLAVE_VSENSE_CTRL_CFG 556
#define SM8450_SLAVE_A1NOC_CFG 557
#define SM8450_SLAVE_A1NOC_SNOC 558
#define SM8450_SLAVE_A2NOC_CFG 559
#define SM8450_SLAVE_A2NOC_SNOC 560
#define SM8450_SLAVE_DDRSS_CFG 561
#define SM8450_SLAVE_GEM_NOC_CNOC 562
#define SM8450_SLAVE_SNOC_GEM_NOC_GC 563
#define SM8450_SLAVE_SNOC_GEM_NOC_SF 564
#define SM8450_SLAVE_LLCC 565
#define SM8450_SLAVE_MNOC_HF_MEM_NOC 566
#define SM8450_SLAVE_MNOC_SF_MEM_NOC 567
#define SM8450_SLAVE_CNOC_MNOC_CFG 568
#define SM8450_SLAVE_CDSP_MEM_NOC 569
#define SM8450_SLAVE_MEM_NOC_PCIE_SNOC 570
#define SM8450_SLAVE_PCIE_ANOC_CFG 571
#define SM8450_SLAVE_ANOC_PCIE_GEM_NOC 572
#define SM8450_SLAVE_SNOC_CFG 573
#define SM8450_SLAVE_LPASS_SNOC 574
#define SM8450_SLAVE_QUP_CORE_0 575
#define SM8450_SLAVE_QUP_CORE_1 576
#define SM8450_SLAVE_QUP_CORE_2 577
#define SM8450_SLAVE_IMEM 578
#define SM8450_SLAVE_PIMEM 579
#define SM8450_SLAVE_SERVICE_NSP_NOC 580
#define SM8450_SLAVE_SERVICE_A1NOC 581
#define SM8450_SLAVE_SERVICE_A2NOC 582
#define SM8450_SLAVE_SERVICE_CNOC 583
#define SM8450_SLAVE_SERVICE_MNOC 584
#define SM8450_SLAVE_SERVICES_LPASS_AML_NOC 585
#define SM8450_SLAVE_SERVICE_LPASS_AG_NOC 586
#define SM8450_SLAVE_SERVICE_PCIE_ANOC 587
#define SM8450_SLAVE_SERVICE_SNOC 588
#define SM8450_SLAVE_PCIE_0 589
#define SM8450_SLAVE_PCIE_1 590
#define SM8450_SLAVE_QDSS_STM 591
#define SM8450_SLAVE_TCU 592
#define SM8450_MASTER_LLCC_DISP 1000
#define SM8450_MASTER_MDP_DISP 1001
#define SM8450_MASTER_MDP0_DISP SM8450_MASTER_MDP_DISP
#define SM8450_MASTER_MDP1_DISP SM8450_MASTER_MDP_DISP
#define SM8450_MASTER_MNOC_HF_MEM_NOC_DISP 1002
#define SM8450_MASTER_MNOC_SF_MEM_NOC_DISP 1003
#define SM8450_MASTER_ANOC_PCIE_GEM_NOC_DISP 1004
#define SM8450_MASTER_ROTATOR_DISP 1005
#define SM8450_SLAVE_EBI1_DISP 1512
#define SM8450_SLAVE_LLCC_DISP 1513
#define SM8450_SLAVE_MNOC_HF_MEM_NOC_DISP 1514
#define SM8450_SLAVE_MNOC_SF_MEM_NOC_DISP 1515
#endif

163
include/dt-bindings/interconnect/qcom,msm8996.h Normal file
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@ -0,0 +1,163 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
/*
* Qualcomm MSM8996 interconnect IDs
*
* Copyright (c) 2021 Yassine Oudjana <y.oudjana@protonmail.com>
*/
#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MSM8996_H
#define __DT_BINDINGS_INTERCONNECT_QCOM_MSM8996_H
/* A0NOC */
#define MASTER_PCIE_0 0
#define MASTER_PCIE_1 1
#define MASTER_PCIE_2 2
/* A1NOC */
#define MASTER_CNOC_A1NOC 0
#define MASTER_CRYPTO_CORE0 1
#define MASTER_PNOC_A1NOC 2
/* A2NOC */
#define MASTER_USB3 0
#define MASTER_IPA 1
#define MASTER_UFS 2
/* BIMC */
#define MASTER_AMPSS_M0 0
#define MASTER_GRAPHICS_3D 1
#define MASTER_MNOC_BIMC 2
#define MASTER_SNOC_BIMC 3
#define SLAVE_EBI_CH0 4
#define SLAVE_HMSS_L3 5
#define SLAVE_BIMC_SNOC_0 6
#define SLAVE_BIMC_SNOC_1 7
/* CNOC */
#define MASTER_SNOC_CNOC 0
#define MASTER_QDSS_DAP 1
#define SLAVE_CNOC_A1NOC 2
#define SLAVE_CLK_CTL 3
#define SLAVE_TCSR 4
#define SLAVE_TLMM 5
#define SLAVE_CRYPTO_0_CFG 6
#define SLAVE_MPM 7
#define SLAVE_PIMEM_CFG 8
#define SLAVE_IMEM_CFG 9
#define SLAVE_MESSAGE_RAM 10
#define SLAVE_BIMC_CFG 11
#define SLAVE_PMIC_ARB 12
#define SLAVE_PRNG 13
#define SLAVE_DCC_CFG 14
#define SLAVE_RBCPR_MX 15
#define SLAVE_QDSS_CFG 16
#define SLAVE_RBCPR_CX 17
#define SLAVE_QDSS_RBCPR_APU 18
#define SLAVE_CNOC_MNOC_CFG 19
#define SLAVE_SNOC_CFG 20
#define SLAVE_SNOC_MPU_CFG 21
#define SLAVE_EBI1_PHY_CFG 22
#define SLAVE_A0NOC_CFG 23
#define SLAVE_PCIE_1_CFG 24
#define SLAVE_PCIE_2_CFG 25
#define SLAVE_PCIE_0_CFG 26
#define SLAVE_PCIE20_AHB2PHY 27
#define SLAVE_A0NOC_MPU_CFG 28
#define SLAVE_UFS_CFG 29
#define SLAVE_A1NOC_CFG 30
#define SLAVE_A1NOC_MPU_CFG 31
#define SLAVE_A2NOC_CFG 32
#define SLAVE_A2NOC_MPU_CFG 33
#define SLAVE_SSC_CFG 34
#define SLAVE_A0NOC_SMMU_CFG 35
#define SLAVE_A1NOC_SMMU_CFG 36
#define SLAVE_A2NOC_SMMU_CFG 37
#define SLAVE_LPASS_SMMU_CFG 38
#define SLAVE_CNOC_MNOC_MMSS_CFG 39
/* MNOC */
#define MASTER_CNOC_MNOC_CFG 0
#define MASTER_CPP 1
#define MASTER_JPEG 2
#define MASTER_MDP_PORT0 3
#define MASTER_MDP_PORT1 4
#define MASTER_ROTATOR 5
#define MASTER_VIDEO_P0 6
#define MASTER_VFE 7
#define MASTER_SNOC_VMEM 8
#define MASTER_VIDEO_P0_OCMEM 9
#define MASTER_CNOC_MNOC_MMSS_CFG 10
#define SLAVE_MNOC_BIMC 11
#define SLAVE_VMEM 12
#define SLAVE_SERVICE_MNOC 13
#define SLAVE_MMAGIC_CFG 14
#define SLAVE_CPR_CFG 15
#define SLAVE_MISC_CFG 16
#define SLAVE_VENUS_THROTTLE_CFG 17
#define SLAVE_VENUS_CFG 18
#define SLAVE_VMEM_CFG 19
#define SLAVE_DSA_CFG 20
#define SLAVE_MMSS_CLK_CFG 21
#define SLAVE_DSA_MPU_CFG 22
#define SLAVE_MNOC_MPU_CFG 23
#define SLAVE_DISPLAY_CFG 24
#define SLAVE_DISPLAY_THROTTLE_CFG 25
#define SLAVE_CAMERA_CFG 26
#define SLAVE_CAMERA_THROTTLE_CFG 27
#define SLAVE_GRAPHICS_3D_CFG 28
#define SLAVE_SMMU_MDP_CFG 29
#define SLAVE_SMMU_ROT_CFG 30
#define SLAVE_SMMU_VENUS_CFG 31
#define SLAVE_SMMU_CPP_CFG 32
#define SLAVE_SMMU_JPEG_CFG 33
#define SLAVE_SMMU_VFE_CFG 34
/* PNOC */
#define MASTER_SNOC_PNOC 0
#define MASTER_SDCC_1 1
#define MASTER_SDCC_2 2
#define MASTER_SDCC_4 3
#define MASTER_USB_HS 4
#define MASTER_BLSP_1 5
#define MASTER_BLSP_2 6
#define MASTER_TSIF 7
#define SLAVE_PNOC_A1NOC 8
#define SLAVE_USB_HS 9
#define SLAVE_SDCC_2 10
#define SLAVE_SDCC_4 11
#define SLAVE_TSIF 12
#define SLAVE_BLSP_2 13
#define SLAVE_SDCC_1 14
#define SLAVE_BLSP_1 15
#define SLAVE_PDM 16
#define SLAVE_AHB2PHY 17
/* SNOC */
#define MASTER_HMSS 0
#define MASTER_QDSS_BAM 1
#define MASTER_SNOC_CFG 2
#define MASTER_BIMC_SNOC_0 3
#define MASTER_BIMC_SNOC_1 4
#define MASTER_A0NOC_SNOC 5
#define MASTER_A1NOC_SNOC 6
#define MASTER_A2NOC_SNOC 7
#define MASTER_QDSS_ETR 8
#define SLAVE_A0NOC_SNOC 9
#define SLAVE_A1NOC_SNOC 10
#define SLAVE_A2NOC_SNOC 11
#define SLAVE_HMSS 12
#define SLAVE_LPASS 13
#define SLAVE_USB3 14
#define SLAVE_SNOC_BIMC 15
#define SLAVE_SNOC_CNOC 16
#define SLAVE_IMEM 17
#define SLAVE_PIMEM 18
#define SLAVE_SNOC_VMEM 19
#define SLAVE_SNOC_PNOC 20
#define SLAVE_QDSS_STM 21
#define SLAVE_PCIE_0 22
#define SLAVE_PCIE_1 23
#define SLAVE_PCIE_2 24
#define SLAVE_SERVICE_SNOC 25
#endif

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include/dt-bindings/interconnect/qcom,qcm2290.h Normal file
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/* SPDX-License-Identifier: GPL-2.0 */
/* QCM2290 interconnect IDs */
#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_QCM2290_H
#define __DT_BINDINGS_INTERCONNECT_QCOM_QCM2290_H
/* BIMC */
#define MASTER_APPSS_PROC 0
#define MASTER_SNOC_BIMC_RT 1
#define MASTER_SNOC_BIMC_NRT 2
#define MASTER_SNOC_BIMC 3
#define MASTER_TCU_0 4
#define MASTER_GFX3D 5
#define SLAVE_EBI1 6
#define SLAVE_BIMC_SNOC 7
/* CNOC */
#define MASTER_SNOC_CNOC 0
#define MASTER_QDSS_DAP 1
#define SLAVE_BIMC_CFG 2
#define SLAVE_CAMERA_NRT_THROTTLE_CFG 3
#define SLAVE_CAMERA_RT_THROTTLE_CFG 4
#define SLAVE_CAMERA_CFG 5
#define SLAVE_CLK_CTL 6
#define SLAVE_CRYPTO_0_CFG 7
#define SLAVE_DISPLAY_CFG 8
#define SLAVE_DISPLAY_THROTTLE_CFG 9
#define SLAVE_GPU_CFG 10
#define SLAVE_HWKM 11
#define SLAVE_IMEM_CFG 12
#define SLAVE_IPA_CFG 13
#define SLAVE_LPASS 14
#define SLAVE_MESSAGE_RAM 15
#define SLAVE_PDM 16
#define SLAVE_PIMEM_CFG 17
#define SLAVE_PKA_WRAPPER 18
#define SLAVE_PMIC_ARB 19
#define SLAVE_PRNG 20
#define SLAVE_QDSS_CFG 21
#define SLAVE_QM_CFG 22
#define SLAVE_QM_MPU_CFG 23
#define SLAVE_QPIC 24
#define SLAVE_QUP_0 25
#define SLAVE_SDCC_1 26
#define SLAVE_SDCC_2 27
#define SLAVE_SNOC_CFG 28
#define SLAVE_TCSR 29
#define SLAVE_USB3 30
#define SLAVE_VENUS_CFG 31
#define SLAVE_VENUS_THROTTLE_CFG 32
#define SLAVE_VSENSE_CTRL_CFG 33
#define SLAVE_SERVICE_CNOC 34
/* SNOC */
#define MASTER_CRYPTO_CORE0 0
#define MASTER_SNOC_CFG 1
#define MASTER_TIC 2
#define MASTER_ANOC_SNOC 3
#define MASTER_BIMC_SNOC 4
#define MASTER_PIMEM 5
#define MASTER_QDSS_BAM 6
#define MASTER_QUP_0 7
#define MASTER_IPA 8
#define MASTER_QDSS_ETR 9
#define MASTER_SDCC_1 10
#define MASTER_SDCC_2 11
#define MASTER_QPIC 12
#define MASTER_USB3_0 13
#define SLAVE_APPSS 14
#define SLAVE_SNOC_CNOC 15
#define SLAVE_IMEM 16
#define SLAVE_PIMEM 17
#define SLAVE_SNOC_BIMC 18
#define SLAVE_SERVICE_SNOC 19
#define SLAVE_QDSS_STM 20
#define SLAVE_TCU 21
#define SLAVE_ANOC_SNOC 22
/* QUP Virtual */
#define MASTER_QUP_CORE_0 0
#define SLAVE_QUP_CORE_0 1
/* MMNRT Virtual */
#define MASTER_CAMNOC_SF 0
#define MASTER_VIDEO_P0 1
#define MASTER_VIDEO_PROC 2
#define SLAVE_SNOC_BIMC_NRT 3
/* MMRT Virtual */
#define MASTER_CAMNOC_HF 0
#define MASTER_MDP0 1
#define SLAVE_SNOC_BIMC_RT 2
#endif

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include/dt-bindings/interconnect/qcom,sm8450.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2021, Linaro Limited
*/
#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SM8450_H
#define __DT_BINDINGS_INTERCONNECT_QCOM_SM8450_H
#define MASTER_QSPI_0 0
#define MASTER_QUP_1 1
#define MASTER_A1NOC_CFG 2
#define MASTER_SDCC_4 3
#define MASTER_UFS_MEM 4
#define MASTER_USB3_0 5
#define SLAVE_A1NOC_SNOC 6
#define SLAVE_SERVICE_A1NOC 7
#define MASTER_QDSS_BAM 0
#define MASTER_QUP_0 1
#define MASTER_QUP_2 2
#define MASTER_A2NOC_CFG 3
#define MASTER_CRYPTO 4
#define MASTER_IPA 5
#define MASTER_SENSORS_PROC 6
#define MASTER_SP 7
#define MASTER_QDSS_ETR 8
#define MASTER_QDSS_ETR_1 9
#define MASTER_SDCC_2 10
#define SLAVE_A2NOC_SNOC 11
#define SLAVE_SERVICE_A2NOC 12
#define MASTER_QUP_CORE_0 0
#define MASTER_QUP_CORE_1 1
#define MASTER_QUP_CORE_2 2
#define SLAVE_QUP_CORE_0 3
#define SLAVE_QUP_CORE_1 4
#define SLAVE_QUP_CORE_2 5
#define MASTER_GEM_NOC_CNOC 0
#define MASTER_GEM_NOC_PCIE_SNOC 1
#define SLAVE_AHB2PHY_SOUTH 2
#define SLAVE_AHB2PHY_NORTH 3
#define SLAVE_AOSS 4
#define SLAVE_CAMERA_CFG 5
#define SLAVE_CLK_CTL 6
#define SLAVE_CDSP_CFG 7
#define SLAVE_RBCPR_CX_CFG 8
#define SLAVE_RBCPR_MMCX_CFG 9
#define SLAVE_RBCPR_MXA_CFG 10
#define SLAVE_RBCPR_MXC_CFG 11
#define SLAVE_CRYPTO_0_CFG 12
#define SLAVE_CX_RDPM 13
#define SLAVE_DISPLAY_CFG 14
#define SLAVE_GFX3D_CFG 15
#define SLAVE_IMEM_CFG 16
#define SLAVE_IPA_CFG 17
#define SLAVE_IPC_ROUTER_CFG 18
#define SLAVE_LPASS 19
#define SLAVE_CNOC_MSS 20
#define SLAVE_MX_RDPM 21
#define SLAVE_PCIE_0_CFG 22
#define SLAVE_PCIE_1_CFG 23
#define SLAVE_PDM 24
#define SLAVE_PIMEM_CFG 25
#define SLAVE_PRNG 26
#define SLAVE_QDSS_CFG 27
#define SLAVE_QSPI_0 28
#define SLAVE_QUP_0 29
#define SLAVE_QUP_1 30
#define SLAVE_QUP_2 31
#define SLAVE_SDCC_2 32
#define SLAVE_SDCC_4 33
#define SLAVE_SPSS_CFG 34
#define SLAVE_TCSR 35
#define SLAVE_TLMM 36
#define SLAVE_TME_CFG 37
#define SLAVE_UFS_MEM_CFG 38
#define SLAVE_USB3_0 39
#define SLAVE_VENUS_CFG 40
#define SLAVE_VSENSE_CTRL_CFG 41
#define SLAVE_A1NOC_CFG 42
#define SLAVE_A2NOC_CFG 43
#define SLAVE_DDRSS_CFG 44
#define SLAVE_CNOC_MNOC_CFG 45
#define SLAVE_PCIE_ANOC_CFG 46
#define SLAVE_SNOC_CFG 47
#define SLAVE_IMEM 48
#define SLAVE_PIMEM 49
#define SLAVE_SERVICE_CNOC 50
#define SLAVE_PCIE_0 51
#define SLAVE_PCIE_1 52
#define SLAVE_QDSS_STM 53
#define SLAVE_TCU 54
#define MASTER_GPU_TCU 0
#define MASTER_SYS_TCU 1
#define MASTER_APPSS_PROC 2
#define MASTER_GFX3D 3
#define MASTER_MSS_PROC 4
#define MASTER_MNOC_HF_MEM_NOC 5
#define MASTER_MNOC_SF_MEM_NOC 6
#define MASTER_COMPUTE_NOC 7
#define MASTER_ANOC_PCIE_GEM_NOC 8
#define MASTER_SNOC_GC_MEM_NOC 9
#define MASTER_SNOC_SF_MEM_NOC 10
#define SLAVE_GEM_NOC_CNOC 11
#define SLAVE_LLCC 12
#define SLAVE_MEM_NOC_PCIE_SNOC 13
#define MASTER_MNOC_HF_MEM_NOC_DISP 14
#define MASTER_MNOC_SF_MEM_NOC_DISP 15
#define MASTER_ANOC_PCIE_GEM_NOC_DISP 16
#define SLAVE_LLCC_DISP 17
#define MASTER_CNOC_LPASS_AG_NOC 0
#define MASTER_LPASS_PROC 1
#define SLAVE_LPASS_CORE_CFG 2
#define SLAVE_LPASS_LPI_CFG 3
#define SLAVE_LPASS_MPU_CFG 4
#define SLAVE_LPASS_TOP_CFG 5
#define SLAVE_LPASS_SNOC 6
#define SLAVE_SERVICES_LPASS_AML_NOC 7
#define SLAVE_SERVICE_LPASS_AG_NOC 8
#define MASTER_LLCC 0
#define SLAVE_EBI1 1
#define MASTER_LLCC_DISP 2
#define SLAVE_EBI1_DISP 3
#define MASTER_CAMNOC_HF 0
#define MASTER_CAMNOC_ICP 1
#define MASTER_CAMNOC_SF 2
#define MASTER_MDP 3
#define MASTER_CNOC_MNOC_CFG 4
#define MASTER_ROTATOR 5
#define MASTER_CDSP_HCP 6
#define MASTER_VIDEO 7
#define MASTER_VIDEO_CV_PROC 8
#define MASTER_VIDEO_PROC 9
#define MASTER_VIDEO_V_PROC 10
#define SLAVE_MNOC_HF_MEM_NOC 11
#define SLAVE_MNOC_SF_MEM_NOC 12
#define SLAVE_SERVICE_MNOC 13
#define MASTER_MDP_DISP 14
#define MASTER_ROTATOR_DISP 15
#define SLAVE_MNOC_HF_MEM_NOC_DISP 16
#define SLAVE_MNOC_SF_MEM_NOC_DISP 17
#define MASTER_CDSP_NOC_CFG 0
#define MASTER_CDSP_PROC 1
#define SLAVE_CDSP_MEM_NOC 2
#define SLAVE_SERVICE_NSP_NOC 3
#define MASTER_PCIE_ANOC_CFG 0
#define MASTER_PCIE_0 1
#define MASTER_PCIE_1 2
#define SLAVE_ANOC_PCIE_GEM_NOC 3
#define SLAVE_SERVICE_PCIE_ANOC 4
#define MASTER_GIC_AHB 0
#define MASTER_A1NOC_SNOC 1
#define MASTER_A2NOC_SNOC 2
#define MASTER_LPASS_ANOC 3
#define MASTER_SNOC_CFG 4
#define MASTER_PIMEM 5
#define MASTER_GIC 6
#define SLAVE_SNOC_GEM_NOC_GC 7
#define SLAVE_SNOC_GEM_NOC_SF 8
#define SLAVE_SERVICE_SNOC 9
#endif