KVM: x86: Do not block APIC write for non ICR registers
The commit 5413bcba7ed5 ("KVM: x86: Add support for vICR APIC-write VM-Exits in x2APIC mode") introduces logic to prevent APIC write for offset other than ICR in kvm_apic_write_nodecode() function. This breaks x2AVIC support, which requires KVM to trap and emulate x2APIC MSR writes. Therefore, removes the warning and modify to logic to allow MSR write. Fixes: 5413bcba7ed5 ("KVM: x86: Add support for vICR APIC-write VM-Exits in x2APIC mode") Cc: Zeng Guang <guang.zeng@intel.com> Suggested-by: Sean Christopherson <seanjc@google.com> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Message-Id: <20220725053356.4275-1-suravee.suthikulpanit@amd.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@ -69,6 +69,7 @@ static bool lapic_timer_advance_dynamic __read_mostly;
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/* step-by-step approximation to mitigate fluctuation */
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#define LAPIC_TIMER_ADVANCE_ADJUST_STEP 8
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static int kvm_lapic_msr_read(struct kvm_lapic *apic, u32 reg, u64 *data);
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static int kvm_lapic_msr_write(struct kvm_lapic *apic, u32 reg, u64 data);
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static inline void __kvm_lapic_set_reg(char *regs, int reg_off, u32 val)
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{
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@ -2283,21 +2284,20 @@ void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
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struct kvm_lapic *apic = vcpu->arch.apic;
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u64 val;
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if (apic_x2apic_mode(apic)) {
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/*
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* When guest APIC is in x2APIC mode and IPI virtualization
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* is enabled, accessing APIC_ICR may cause trap-like VM-exit
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* on Intel hardware. Other offsets are not possible.
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*/
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if (WARN_ON_ONCE(offset != APIC_ICR))
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return;
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if (apic_x2apic_mode(apic))
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kvm_lapic_msr_read(apic, offset, &val);
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else
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val = kvm_lapic_get_reg(apic, offset);
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/*
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* ICR is a single 64-bit register when x2APIC is enabled. For legacy
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* xAPIC, ICR writes need to go down the common (slightly slower) path
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* to get the upper half from ICR2.
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*/
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if (apic_x2apic_mode(apic) && offset == APIC_ICR) {
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kvm_apic_send_ipi(apic, (u32)val, (u32)(val >> 32));
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trace_kvm_apic_write(APIC_ICR, val);
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} else {
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val = kvm_lapic_get_reg(apic, offset);
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/* TODO: optimize to just emulate side effect w/o one more write */
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kvm_lapic_reg_write(apic, offset, (u32)val);
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}
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