From 21c11421db1fdd5ed7c8ea7048178b365185cd3a Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 30 Aug 2023 17:25:55 +0200 Subject: [PATCH 1/4] pinctrl: renesas: r8a7779: s/LSBC/LBSC/ Fix a misspelling of "LBSC" (Local Bus State Controller). Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/129f08c4246f88fd5a25ca5b82c255919b71ca6c.1693409115.git.geert+renesas@glider.be --- drivers/pinctrl/renesas/pfc-r8a7779.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/renesas/pfc-r8a7779.c b/drivers/pinctrl/renesas/pfc-r8a7779.c index 1172a359384d..e1a8cb669120 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7779.c +++ b/drivers/pinctrl/renesas/pfc-r8a7779.c @@ -1942,7 +1942,7 @@ static const unsigned int intc_irq3_b_pins[] = { static const unsigned int intc_irq3_b_mux[] = { IRQ3_B_MARK, }; -/* - LSBC ------------------------------------------------------------------- */ +/* - LBSC ------------------------------------------------------------------- */ static const unsigned int lbsc_cs0_pins[] = { /* CS */ RCAR_GP_PIN(0, 13), From 84c580e9695084d688904a18bfdc129aeca78144 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Tue, 12 Sep 2023 07:51:48 +0300 Subject: [PATCH 2/4] pinctrl: renesas: rzg2l: Make struct rzg2l_pinctrl_data::dedicated_pins constant struct rzg2l_pinctrl_data::dedicated_pins is constant thus mark it so. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230912045157.177966-29-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 37cdfe4b04f9..b884f53557db 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -133,7 +133,7 @@ struct rzg2l_pinctrl_data { const char * const *port_pins; const u32 *port_pin_configs; unsigned int n_ports; - struct rzg2l_dedicated_configs *dedicated_pins; + const struct rzg2l_dedicated_configs *dedicated_pins; unsigned int n_port_pins; unsigned int n_dedicated_pins; }; @@ -1059,7 +1059,7 @@ static const u32 r9a07g043_gpio_configs[] = { RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS), }; -static struct { +static const struct { struct rzg2l_dedicated_configs common[35]; struct rzg2l_dedicated_configs rzg2l_pins[7]; } rzg2l_dedicated_pins = { From dd462cf53e4dff0f4eba5e6650e31ceddec74c6f Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 18 Sep 2023 13:33:54 +0100 Subject: [PATCH 3/4] pinctrl: renesas: rzg2l: Make reverse order of enable() for disable() We usually do reverse order of enable() for disable(). Currently, the ordering of irq_chip_disable_parent() is not correct in rzg2l_gpio_irq_disable(). Fix the incorrect order. Fixes: db2e5f21a48e ("pinctrl: renesas: pinctrl-rzg2l: Add IRQ domain to handle GPIO interrupt") Signed-off-by: Biju Das Tested-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230918123355.262115-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index b884f53557db..23c2a1044089 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -1175,6 +1175,8 @@ static void rzg2l_gpio_irq_disable(struct irq_data *d) u32 port; u8 bit; + irq_chip_disable_parent(d); + port = RZG2L_PIN_ID_TO_PORT(hwirq); bit = RZG2L_PIN_ID_TO_PIN(hwirq); @@ -1189,7 +1191,6 @@ static void rzg2l_gpio_irq_disable(struct irq_data *d) spin_unlock_irqrestore(&pctrl->lock, flags); gpiochip_disable_irq(gc, hwirq); - irq_chip_disable_parent(d); } static void rzg2l_gpio_irq_enable(struct irq_data *d) From c385256611b1af79d180e35c07992b43e1be5067 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 22 Sep 2023 09:53:11 +0200 Subject: [PATCH 4/4] pinctrl: renesas: rzg2l: Rename rzg2l_gpio_configs[] The rzg2l_gpio_configs array is really related to the RZ/G2L (R9A07G044) Soc only. Hence rename it to r9a07g044_gpio_configs[]. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/19958e63a2b793be5182640c4301ec5a77a507f6.1695369116.git.geert+renesas@glider.be --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 23c2a1044089..03b36c6b2b6d 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -985,7 +985,7 @@ static const char * const rzg2l_gpio_names[] = { "P48_0", "P48_1", "P48_2", "P48_3", "P48_4", "P48_5", "P48_6", "P48_7", }; -static const u32 rzg2l_gpio_configs[] = { +static const u32 r9a07g044_gpio_configs[] = { RZG2L_GPIO_PORT_PACK(2, 0x10, RZG2L_MPXED_PIN_FUNCS), RZG2L_GPIO_PORT_PACK(2, 0x11, RZG2L_MPXED_PIN_FUNCS), RZG2L_GPIO_PORT_PACK(2, 0x12, RZG2L_MPXED_PIN_FUNCS), @@ -1485,7 +1485,7 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev) struct clk *clk; int ret; - BUILD_BUG_ON(ARRAY_SIZE(rzg2l_gpio_configs) * RZG2L_PINS_PER_PORT > + BUILD_BUG_ON(ARRAY_SIZE(r9a07g044_gpio_configs) * RZG2L_PINS_PER_PORT > ARRAY_SIZE(rzg2l_gpio_names)); BUILD_BUG_ON(ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT > @@ -1535,10 +1535,10 @@ static struct rzg2l_pinctrl_data r9a07g043_data = { static struct rzg2l_pinctrl_data r9a07g044_data = { .port_pins = rzg2l_gpio_names, - .port_pin_configs = rzg2l_gpio_configs, - .n_ports = ARRAY_SIZE(rzg2l_gpio_configs), + .port_pin_configs = r9a07g044_gpio_configs, + .n_ports = ARRAY_SIZE(r9a07g044_gpio_configs), .dedicated_pins = rzg2l_dedicated_pins.common, - .n_port_pins = ARRAY_SIZE(rzg2l_gpio_configs) * RZG2L_PINS_PER_PORT, + .n_port_pins = ARRAY_SIZE(r9a07g044_gpio_configs) * RZG2L_PINS_PER_PORT, .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common) + ARRAY_SIZE(rzg2l_dedicated_pins.rzg2l_pins), };