Merge branches 'pci/host-rcar', 'pci/hotplug', 'pci/iommu', 'pci/misc' and 'pci/msi' into next
* pci/host-rcar: PCI: rcar: Remove rcar_pcie_setup_window() resource argument PCI: rcar: Cleanup style and formatting PCI: rcar: Use correct initial HW settings PCI: rcar: Remove redundant config accessor register number checks * pci/hotplug: PCI: cpqphp: Remove unnecessary null test before debugfs_remove() PCI: pciehp: Clear Data Link Layer State Changed during init PCI: pciehp: Remove struct controller.no_cmd_complete PCI: pciehp: Remove assumptions about which commands cause completion events PCI: pciehp: Compute timeout from hotplug command start time PCI: pciehp: Wait for hotplug command completion lazily PCI: pciehp: Make pcie_wait_cmd() self-contained PCI: Prevent NULL dereference during pciehp probe * pci/iommu: PCI: Add bridge DMA alias quirk for Intel 82801 bridge * pci/misc: ACPI / PCI: Fix sysfs acpi_index and label errors PCI/portdrv: Remove warning about invalid IRQ for hot-added PCIe ports * pci/msi: PCI/MSI: Cache Multiple Message Capable in struct msi_desc PCI/MSI: Remove unused msi_enabled_mask() PCI/MSI: Add internal msix_clear_and_set_ctrl() function
This commit is contained in:
Bjorn Helgaas
commit
1d0df48692
@ -105,7 +105,7 @@
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#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 19)
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#define PCIE_CONF_FUNC(f) (((f) & 0x7) << 16)
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#define PCI_MAX_RESOURCES 4
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#define RCAR_PCI_MAX_RESOURCES 4
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#define MAX_NR_INBOUND_MAPS 6
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struct rcar_msi {
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@ -127,7 +127,7 @@ static inline struct rcar_msi *to_rcar_msi(struct msi_chip *chip)
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struct rcar_pcie {
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struct device *dev;
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void __iomem *base;
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struct resource res[PCI_MAX_RESOURCES];
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struct resource res[RCAR_PCI_MAX_RESOURCES];
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struct resource busn;
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int root_bus_nr;
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struct clk *clk;
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@ -140,36 +140,37 @@ static inline struct rcar_pcie *sys_to_pcie(struct pci_sys_data *sys)
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return sys->private_data;
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}
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static void pci_write_reg(struct rcar_pcie *pcie, unsigned long val,
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static void rcar_pci_write_reg(struct rcar_pcie *pcie, unsigned long val,
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unsigned long reg)
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{
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writel(val, pcie->base + reg);
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}
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static unsigned long pci_read_reg(struct rcar_pcie *pcie, unsigned long reg)
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static unsigned long rcar_pci_read_reg(struct rcar_pcie *pcie,
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unsigned long reg)
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{
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return readl(pcie->base + reg);
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}
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enum {
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PCI_ACCESS_READ,
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PCI_ACCESS_WRITE,
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RCAR_PCI_ACCESS_READ,
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RCAR_PCI_ACCESS_WRITE,
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};
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static void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data)
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{
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int shift = 8 * (where & 3);
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u32 val = pci_read_reg(pcie, where & ~3);
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u32 val = rcar_pci_read_reg(pcie, where & ~3);
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val &= ~(mask << shift);
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val |= data << shift;
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pci_write_reg(pcie, val, where & ~3);
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rcar_pci_write_reg(pcie, val, where & ~3);
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}
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static u32 rcar_read_conf(struct rcar_pcie *pcie, int where)
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{
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int shift = 8 * (where & 3);
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u32 val = pci_read_reg(pcie, where & ~3);
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u32 val = rcar_pci_read_reg(pcie, where & ~3);
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return val >> shift;
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}
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@ -205,14 +206,14 @@ static int rcar_pcie_config_access(struct rcar_pcie *pcie,
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if (dev != 0)
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (access_type == PCI_ACCESS_READ) {
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*data = pci_read_reg(pcie, PCICONF(index));
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if (access_type == RCAR_PCI_ACCESS_READ) {
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*data = rcar_pci_read_reg(pcie, PCICONF(index));
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} else {
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/* Keep an eye out for changes to the root bus number */
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if (pci_is_root_bus(bus) && (reg == PCI_PRIMARY_BUS))
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pcie->root_bus_nr = *data & 0xff;
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pci_write_reg(pcie, *data, PCICONF(index));
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rcar_pci_write_reg(pcie, *data, PCICONF(index));
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}
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return PCIBIOS_SUCCESSFUL;
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@ -222,20 +223,20 @@ static int rcar_pcie_config_access(struct rcar_pcie *pcie,
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return PCIBIOS_DEVICE_NOT_FOUND;
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/* Clear errors */
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pci_write_reg(pcie, pci_read_reg(pcie, PCIEERRFR), PCIEERRFR);
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rcar_pci_write_reg(pcie, rcar_pci_read_reg(pcie, PCIEERRFR), PCIEERRFR);
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/* Set the PIO address */
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pci_write_reg(pcie, PCIE_CONF_BUS(bus->number) | PCIE_CONF_DEV(dev) |
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PCIE_CONF_FUNC(func) | reg, PCIECAR);
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rcar_pci_write_reg(pcie, PCIE_CONF_BUS(bus->number) |
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PCIE_CONF_DEV(dev) | PCIE_CONF_FUNC(func) | reg, PCIECAR);
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/* Enable the configuration access */
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if (bus->parent->number == pcie->root_bus_nr)
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pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE0, PCIECCTLR);
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rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE0, PCIECCTLR);
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else
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pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE1, PCIECCTLR);
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rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE1, PCIECCTLR);
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/* Check for errors */
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if (pci_read_reg(pcie, PCIEERRFR) & UNSUPPORTED_REQUEST)
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if (rcar_pci_read_reg(pcie, PCIEERRFR) & UNSUPPORTED_REQUEST)
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return PCIBIOS_DEVICE_NOT_FOUND;
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/* Check for master and target aborts */
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@ -243,13 +244,13 @@ static int rcar_pcie_config_access(struct rcar_pcie *pcie,
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(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT))
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (access_type == PCI_ACCESS_READ)
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*data = pci_read_reg(pcie, PCIECDR);
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if (access_type == RCAR_PCI_ACCESS_READ)
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*data = rcar_pci_read_reg(pcie, PCIECDR);
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else
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pci_write_reg(pcie, *data, PCIECDR);
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rcar_pci_write_reg(pcie, *data, PCIECDR);
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/* Disable the configuration access */
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pci_write_reg(pcie, 0, PCIECCTLR);
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rcar_pci_write_reg(pcie, 0, PCIECCTLR);
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return PCIBIOS_SUCCESSFUL;
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}
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@ -260,12 +261,7 @@ static int rcar_pcie_read_conf(struct pci_bus *bus, unsigned int devfn,
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struct rcar_pcie *pcie = sys_to_pcie(bus->sysdata);
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int ret;
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if ((size == 2) && (where & 1))
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return PCIBIOS_BAD_REGISTER_NUMBER;
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else if ((size == 4) && (where & 3))
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return PCIBIOS_BAD_REGISTER_NUMBER;
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ret = rcar_pcie_config_access(pcie, PCI_ACCESS_READ,
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ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_READ,
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bus, devfn, where, val);
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if (ret != PCIBIOS_SUCCESSFUL) {
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*val = 0xffffffff;
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@ -291,12 +287,7 @@ static int rcar_pcie_write_conf(struct pci_bus *bus, unsigned int devfn,
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int shift, ret;
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u32 data;
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if ((size == 2) && (where & 1))
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return PCIBIOS_BAD_REGISTER_NUMBER;
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else if ((size == 4) && (where & 3))
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return PCIBIOS_BAD_REGISTER_NUMBER;
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ret = rcar_pcie_config_access(pcie, PCI_ACCESS_READ,
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ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_READ,
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bus, devfn, where, &data);
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if (ret != PCIBIOS_SUCCESSFUL)
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return ret;
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@ -315,7 +306,7 @@ static int rcar_pcie_write_conf(struct pci_bus *bus, unsigned int devfn,
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} else
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data = val;
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ret = rcar_pcie_config_access(pcie, PCI_ACCESS_WRITE,
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ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_WRITE,
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bus, devfn, where, &data);
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return ret;
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@ -326,14 +317,15 @@ static struct pci_ops rcar_pcie_ops = {
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.write = rcar_pcie_write_conf,
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};
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static void rcar_pcie_setup_window(int win, struct resource *res,
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struct rcar_pcie *pcie)
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static void rcar_pcie_setup_window(int win, struct rcar_pcie *pcie)
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{
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struct resource *res = &pcie->res[win];
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/* Setup PCIe address space mappings for each resource */
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resource_size_t size;
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u32 mask;
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pci_write_reg(pcie, 0x00000000, PCIEPTCTLR(win));
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rcar_pci_write_reg(pcie, 0x00000000, PCIEPTCTLR(win));
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/*
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* The PAMR mask is calculated in units of 128Bytes, which
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@ -341,17 +333,17 @@ static void rcar_pcie_setup_window(int win, struct resource *res,
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*/
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size = resource_size(res);
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mask = (roundup_pow_of_two(size) / SZ_128) - 1;
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pci_write_reg(pcie, mask << 7, PCIEPAMR(win));
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rcar_pci_write_reg(pcie, mask << 7, PCIEPAMR(win));
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pci_write_reg(pcie, upper_32_bits(res->start), PCIEPARH(win));
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pci_write_reg(pcie, lower_32_bits(res->start), PCIEPARL(win));
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rcar_pci_write_reg(pcie, upper_32_bits(res->start), PCIEPARH(win));
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rcar_pci_write_reg(pcie, lower_32_bits(res->start), PCIEPARL(win));
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/* First resource is for IO */
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mask = PAR_ENABLE;
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if (res->flags & IORESOURCE_IO)
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mask |= IO_SPACE;
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pci_write_reg(pcie, mask, PCIEPTCTLR(win));
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rcar_pci_write_reg(pcie, mask, PCIEPTCTLR(win));
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}
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static int rcar_pcie_setup(int nr, struct pci_sys_data *sys)
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@ -363,13 +355,13 @@ static int rcar_pcie_setup(int nr, struct pci_sys_data *sys)
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pcie->root_bus_nr = -1;
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/* Setup PCI resources */
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for (i = 0; i < PCI_MAX_RESOURCES; i++) {
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for (i = 0; i < RCAR_PCI_MAX_RESOURCES; i++) {
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res = &pcie->res[i];
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if (!res->flags)
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continue;
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rcar_pcie_setup_window(i, res, pcie);
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rcar_pcie_setup_window(i, pcie);
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if (res->flags & IORESOURCE_IO)
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pci_ioremap_io(nr * SZ_64K, res->start);
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@ -415,7 +407,7 @@ static int phy_wait_for_ack(struct rcar_pcie *pcie)
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unsigned int timeout = 100;
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while (timeout--) {
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if (pci_read_reg(pcie, H1_PCIEPHYADRR) & PHY_ACK)
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if (rcar_pci_read_reg(pcie, H1_PCIEPHYADRR) & PHY_ACK)
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return 0;
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udelay(100);
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@ -438,15 +430,15 @@ static void phy_write_reg(struct rcar_pcie *pcie,
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((addr & 0xff) << ADR_POS);
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/* Set write data */
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pci_write_reg(pcie, data, H1_PCIEPHYDOUTR);
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pci_write_reg(pcie, phyaddr, H1_PCIEPHYADRR);
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rcar_pci_write_reg(pcie, data, H1_PCIEPHYDOUTR);
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rcar_pci_write_reg(pcie, phyaddr, H1_PCIEPHYADRR);
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/* Ignore errors as they will be dealt with if the data link is down */
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phy_wait_for_ack(pcie);
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/* Clear command */
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pci_write_reg(pcie, 0, H1_PCIEPHYDOUTR);
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pci_write_reg(pcie, 0, H1_PCIEPHYADRR);
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rcar_pci_write_reg(pcie, 0, H1_PCIEPHYDOUTR);
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rcar_pci_write_reg(pcie, 0, H1_PCIEPHYADRR);
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/* Ignore errors as they will be dealt with if the data link is down */
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phy_wait_for_ack(pcie);
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@ -457,7 +449,7 @@ static int rcar_pcie_wait_for_dl(struct rcar_pcie *pcie)
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unsigned int timeout = 10;
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while (timeout--) {
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if ((pci_read_reg(pcie, PCIETSTR) & DATA_LINK_ACTIVE))
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if ((rcar_pci_read_reg(pcie, PCIETSTR) & DATA_LINK_ACTIVE))
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return 0;
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msleep(5);
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@ -471,17 +463,17 @@ static int rcar_pcie_hw_init(struct rcar_pcie *pcie)
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int err;
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/* Begin initialization */
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pci_write_reg(pcie, 0, PCIETCTLR);
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rcar_pci_write_reg(pcie, 0, PCIETCTLR);
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/* Set mode */
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pci_write_reg(pcie, 1, PCIEMSR);
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rcar_pci_write_reg(pcie, 1, PCIEMSR);
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/*
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* Initial header for port config space is type 1, set the device
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* class to match. Hardware takes care of propagating the IDSETR
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* settings, so there is no need to bother with a quirk.
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*/
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pci_write_reg(pcie, PCI_CLASS_BRIDGE_PCI << 16, IDSETR1);
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rcar_pci_write_reg(pcie, PCI_CLASS_BRIDGE_PCI << 16, IDSETR1);
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/*
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* Setup Secondary Bus Number & Subordinate Bus Number, even though
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@ -491,14 +483,15 @@ static int rcar_pcie_hw_init(struct rcar_pcie *pcie)
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rcar_rmw32(pcie, RCONF(PCI_SUBORDINATE_BUS), 0xff, 1);
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/* Initialize default capabilities. */
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rcar_rmw32(pcie, REXPCAP(0), 0, PCI_CAP_ID_EXP);
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rcar_rmw32(pcie, REXPCAP(0), 0xff, PCI_CAP_ID_EXP);
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rcar_rmw32(pcie, REXPCAP(PCI_EXP_FLAGS),
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PCI_EXP_FLAGS_TYPE, PCI_EXP_TYPE_ROOT_PORT << 4);
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rcar_rmw32(pcie, RCONF(PCI_HEADER_TYPE), 0x7f,
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PCI_HEADER_TYPE_BRIDGE);
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/* Enable data link layer active state reporting */
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rcar_rmw32(pcie, REXPCAP(PCI_EXP_LNKCAP), 0, PCI_EXP_LNKCAP_DLLLARC);
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rcar_rmw32(pcie, REXPCAP(PCI_EXP_LNKCAP), PCI_EXP_LNKCAP_DLLLARC,
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PCI_EXP_LNKCAP_DLLLARC);
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/* Write out the physical slot number = 0 */
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rcar_rmw32(pcie, REXPCAP(PCI_EXP_SLTCAP), PCI_EXP_SLTCAP_PSN, 0);
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@ -507,17 +500,14 @@ static int rcar_pcie_hw_init(struct rcar_pcie *pcie)
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rcar_rmw32(pcie, TLCTLR + 1, 0x3f, 50);
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/* Terminate list of capabilities (Next Capability Offset=0) */
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rcar_rmw32(pcie, RVCCAP(0), 0xfff0, 0);
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/* Enable MAC data scrambling. */
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rcar_rmw32(pcie, MACCTLR, SCRAMBLE_DISABLE, 0);
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rcar_rmw32(pcie, RVCCAP(0), 0xfff00000, 0);
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/* Enable MSI */
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if (IS_ENABLED(CONFIG_PCI_MSI))
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pci_write_reg(pcie, 0x101f0000, PCIEMSITXR);
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rcar_pci_write_reg(pcie, 0x101f0000, PCIEMSITXR);
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/* Finish initialization - establish a PCI Express link */
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pci_write_reg(pcie, CFINIT, PCIETCTLR);
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rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR);
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/* This will timeout if we don't have a link. */
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err = rcar_pcie_wait_for_dl(pcie);
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@ -527,11 +517,6 @@ static int rcar_pcie_hw_init(struct rcar_pcie *pcie)
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/* Enable INTx interrupts */
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rcar_rmw32(pcie, PCIEINTXR, 0, 0xF << 8);
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/* Enable slave Bus Mastering */
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rcar_rmw32(pcie, RCONF(PCI_STATUS), PCI_STATUS_DEVSEL_MASK,
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PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
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PCI_STATUS_CAP_LIST | PCI_STATUS_DEVSEL_FAST);
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wmb();
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return 0;
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@ -560,7 +545,7 @@ static int rcar_pcie_hw_init_h1(struct rcar_pcie *pcie)
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phy_write_reg(pcie, 0, 0x66, 0x1, 0x00008000);
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while (timeout--) {
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if (pci_read_reg(pcie, H1_PCIEPHYSR))
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if (rcar_pci_read_reg(pcie, H1_PCIEPHYSR))
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return rcar_pcie_hw_init(pcie);
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msleep(5);
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@ -599,7 +584,7 @@ static irqreturn_t rcar_pcie_msi_irq(int irq, void *data)
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struct rcar_msi *msi = &pcie->msi;
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unsigned long reg;
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reg = pci_read_reg(pcie, PCIEMSIFR);
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reg = rcar_pci_read_reg(pcie, PCIEMSIFR);
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/* MSI & INTx share an interrupt - we only handle MSI here */
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if (!reg)
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@ -610,7 +595,7 @@ static irqreturn_t rcar_pcie_msi_irq(int irq, void *data)
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unsigned int irq;
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/* clear the interrupt */
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pci_write_reg(pcie, 1 << index, PCIEMSIFR);
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rcar_pci_write_reg(pcie, 1 << index, PCIEMSIFR);
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irq = irq_find_mapping(msi->domain, index);
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if (irq) {
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@ -624,7 +609,7 @@ static irqreturn_t rcar_pcie_msi_irq(int irq, void *data)
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}
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/* see if there's any more pending in this vector */
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reg = pci_read_reg(pcie, PCIEMSIFR);
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reg = rcar_pci_read_reg(pcie, PCIEMSIFR);
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}
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return IRQ_HANDLED;
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@ -651,8 +636,8 @@ static int rcar_msi_setup_irq(struct msi_chip *chip, struct pci_dev *pdev,
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irq_set_msi_desc(irq, desc);
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msg.address_lo = pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE;
|
||||
msg.address_hi = pci_read_reg(pcie, PCIEMSIAUR);
|
||||
msg.address_lo = rcar_pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE;
|
||||
msg.address_hi = rcar_pci_read_reg(pcie, PCIEMSIAUR);
|
||||
msg.data = hwirq;
|
||||
|
||||
write_msi_msg(irq, &msg);
|
||||
@ -729,11 +714,11 @@ static int rcar_pcie_enable_msi(struct rcar_pcie *pcie)
|
||||
msi->pages = __get_free_pages(GFP_KERNEL, 0);
|
||||
base = virt_to_phys((void *)msi->pages);
|
||||
|
||||
pci_write_reg(pcie, base | MSIFE, PCIEMSIALR);
|
||||
pci_write_reg(pcie, 0, PCIEMSIAUR);
|
||||
rcar_pci_write_reg(pcie, base | MSIFE, PCIEMSIALR);
|
||||
rcar_pci_write_reg(pcie, 0, PCIEMSIAUR);
|
||||
|
||||
/* enable all MSI interrupts */
|
||||
pci_write_reg(pcie, 0xffffffff, PCIEMSIIER);
|
||||
rcar_pci_write_reg(pcie, 0xffffffff, PCIEMSIIER);
|
||||
|
||||
return 0;
|
||||
|
||||
@ -826,6 +811,7 @@ static int rcar_pcie_inbound_ranges(struct rcar_pcie *pcie,
|
||||
if (cpu_addr > 0) {
|
||||
unsigned long nr_zeros = __ffs64(cpu_addr);
|
||||
u64 alignment = 1ULL << nr_zeros;
|
||||
|
||||
size = min(range->size, alignment);
|
||||
} else {
|
||||
size = range->size;
|
||||
@ -841,13 +827,13 @@ static int rcar_pcie_inbound_ranges(struct rcar_pcie *pcie,
|
||||
* Set up 64-bit inbound regions as the range parser doesn't
|
||||
* distinguish between 32 and 64-bit types.
|
||||
*/
|
||||
pci_write_reg(pcie, lower_32_bits(pci_addr), PCIEPRAR(idx));
|
||||
pci_write_reg(pcie, lower_32_bits(cpu_addr), PCIELAR(idx));
|
||||
pci_write_reg(pcie, lower_32_bits(mask) | flags, PCIELAMR(idx));
|
||||
rcar_pci_write_reg(pcie, lower_32_bits(pci_addr), PCIEPRAR(idx));
|
||||
rcar_pci_write_reg(pcie, lower_32_bits(cpu_addr), PCIELAR(idx));
|
||||
rcar_pci_write_reg(pcie, lower_32_bits(mask) | flags, PCIELAMR(idx));
|
||||
|
||||
pci_write_reg(pcie, upper_32_bits(pci_addr), PCIEPRAR(idx+1));
|
||||
pci_write_reg(pcie, upper_32_bits(cpu_addr), PCIELAR(idx+1));
|
||||
pci_write_reg(pcie, 0, PCIELAMR(idx+1));
|
||||
rcar_pci_write_reg(pcie, upper_32_bits(pci_addr), PCIEPRAR(idx+1));
|
||||
rcar_pci_write_reg(pcie, upper_32_bits(cpu_addr), PCIELAR(idx+1));
|
||||
rcar_pci_write_reg(pcie, 0, PCIELAMR(idx + 1));
|
||||
|
||||
pci_addr += size;
|
||||
cpu_addr += size;
|
||||
@ -952,7 +938,7 @@ static int rcar_pcie_probe(struct platform_device *pdev)
|
||||
of_pci_range_to_resource(&range, pdev->dev.of_node,
|
||||
&pcie->res[win++]);
|
||||
|
||||
if (win > PCI_MAX_RESOURCES)
|
||||
if (win > RCAR_PCI_MAX_RESOURCES)
|
||||
break;
|
||||
}
|
||||
|
||||
@ -982,7 +968,7 @@ static int rcar_pcie_probe(struct platform_device *pdev)
|
||||
return 0;
|
||||
}
|
||||
|
||||
data = pci_read_reg(pcie, MACSR);
|
||||
data = rcar_pci_read_reg(pcie, MACSR);
|
||||
dev_info(&pdev->dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f);
|
||||
|
||||
rcar_pcie_enable(pcie);
|
||||
|
||||
@ -216,7 +216,6 @@ void cpqhp_create_debugfs_files(struct controller *ctrl)
|
||||
|
||||
void cpqhp_remove_debugfs_files(struct controller *ctrl)
|
||||
{
|
||||
if (ctrl->dentry)
|
||||
debugfs_remove(ctrl->dentry);
|
||||
ctrl->dentry = NULL;
|
||||
}
|
||||
|
||||
@ -92,9 +92,10 @@ struct controller {
|
||||
struct slot *slot;
|
||||
wait_queue_head_t queue; /* sleep & wake process */
|
||||
u32 slot_cap;
|
||||
u32 slot_ctrl;
|
||||
struct timer_list poll_timer;
|
||||
unsigned long cmd_started; /* jiffies */
|
||||
unsigned int cmd_busy:1;
|
||||
unsigned int no_cmd_complete:1;
|
||||
unsigned int link_active_reporting:1;
|
||||
unsigned int notification_enabled:1;
|
||||
unsigned int power_fault_detected;
|
||||
|
||||
@ -255,6 +255,13 @@ static int pciehp_probe(struct pcie_device *dev)
|
||||
else if (pciehp_acpi_slot_detection_check(dev->port))
|
||||
goto err_out_none;
|
||||
|
||||
if (!dev->port->subordinate) {
|
||||
/* Can happen if we run out of bus numbers during probe */
|
||||
dev_err(&dev->device,
|
||||
"Hotplug bridge without secondary bus, ignoring\n");
|
||||
goto err_out_none;
|
||||
}
|
||||
|
||||
ctrl = pcie_init(dev);
|
||||
if (!ctrl) {
|
||||
dev_err(&dev->device, "Controller initialization failed\n");
|
||||
|
||||
@ -104,11 +104,10 @@ static inline void pciehp_free_irq(struct controller *ctrl)
|
||||
free_irq(ctrl->pcie->irq, ctrl);
|
||||
}
|
||||
|
||||
static int pcie_poll_cmd(struct controller *ctrl)
|
||||
static int pcie_poll_cmd(struct controller *ctrl, int timeout)
|
||||
{
|
||||
struct pci_dev *pdev = ctrl_dev(ctrl);
|
||||
u16 slot_status;
|
||||
int timeout = 1000;
|
||||
|
||||
pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
|
||||
if (slot_status & PCI_EXP_SLTSTA_CC) {
|
||||
@ -129,18 +128,52 @@ static int pcie_poll_cmd(struct controller *ctrl)
|
||||
return 0; /* timeout */
|
||||
}
|
||||
|
||||
static void pcie_wait_cmd(struct controller *ctrl, int poll)
|
||||
static void pcie_wait_cmd(struct controller *ctrl)
|
||||
{
|
||||
unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
|
||||
unsigned long timeout = msecs_to_jiffies(msecs);
|
||||
unsigned long duration = msecs_to_jiffies(msecs);
|
||||
unsigned long cmd_timeout = ctrl->cmd_started + duration;
|
||||
unsigned long now, timeout;
|
||||
int rc;
|
||||
|
||||
if (poll)
|
||||
rc = pcie_poll_cmd(ctrl);
|
||||
/*
|
||||
* If the controller does not generate notifications for command
|
||||
* completions, we never need to wait between writes.
|
||||
*/
|
||||
if (NO_CMD_CMPL(ctrl))
|
||||
return;
|
||||
|
||||
if (!ctrl->cmd_busy)
|
||||
return;
|
||||
|
||||
/*
|
||||
* Even if the command has already timed out, we want to call
|
||||
* pcie_poll_cmd() so it can clear PCI_EXP_SLTSTA_CC.
|
||||
*/
|
||||
now = jiffies;
|
||||
if (time_before_eq(cmd_timeout, now))
|
||||
timeout = 1;
|
||||
else
|
||||
timeout = cmd_timeout - now;
|
||||
|
||||
if (ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE &&
|
||||
ctrl->slot_ctrl & PCI_EXP_SLTCTL_CCIE)
|
||||
rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
|
||||
else
|
||||
rc = pcie_poll_cmd(ctrl, timeout);
|
||||
|
||||
/*
|
||||
* Controllers with errata like Intel CF118 don't generate
|
||||
* completion notifications unless the power/indicator/interlock
|
||||
* control bits are changed. On such controllers, we'll emit this
|
||||
* timeout message when we wait for completion of commands that
|
||||
* don't change those bits, e.g., commands that merely enable
|
||||
* interrupts.
|
||||
*/
|
||||
if (!rc)
|
||||
ctrl_dbg(ctrl, "Command not completed in 1000 msec\n");
|
||||
ctrl_info(ctrl, "Timeout on hotplug command %#010x (issued %u msec ago)\n",
|
||||
ctrl->slot_ctrl,
|
||||
jiffies_to_msecs(now - ctrl->cmd_started));
|
||||
}
|
||||
|
||||
/**
|
||||
@ -152,34 +185,12 @@ static void pcie_wait_cmd(struct controller *ctrl, int poll)
|
||||
static void pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
|
||||
{
|
||||
struct pci_dev *pdev = ctrl_dev(ctrl);
|
||||
u16 slot_status;
|
||||
u16 slot_ctrl;
|
||||
|
||||
mutex_lock(&ctrl->ctrl_lock);
|
||||
|
||||
pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
|
||||
if (slot_status & PCI_EXP_SLTSTA_CC) {
|
||||
pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
|
||||
PCI_EXP_SLTSTA_CC);
|
||||
if (!ctrl->no_cmd_complete) {
|
||||
/*
|
||||
* After 1 sec and CMD_COMPLETED still not set, just
|
||||
* proceed forward to issue the next command according
|
||||
* to spec. Just print out the error message.
|
||||
*/
|
||||
ctrl_dbg(ctrl, "CMD_COMPLETED not clear after 1 sec\n");
|
||||
} else if (!NO_CMD_CMPL(ctrl)) {
|
||||
/*
|
||||
* This controller seems to notify of command completed
|
||||
* event even though it supports none of power
|
||||
* controller, attention led, power led and EMI.
|
||||
*/
|
||||
ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Need to wait for command completed event\n");
|
||||
ctrl->no_cmd_complete = 0;
|
||||
} else {
|
||||
ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Maybe the controller is broken\n");
|
||||
}
|
||||
}
|
||||
/* Wait for any previous command that might still be in progress */
|
||||
pcie_wait_cmd(ctrl);
|
||||
|
||||
pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
|
||||
slot_ctrl &= ~mask;
|
||||
@ -187,22 +198,9 @@ static void pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
|
||||
ctrl->cmd_busy = 1;
|
||||
smp_mb();
|
||||
pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl);
|
||||
ctrl->cmd_started = jiffies;
|
||||
ctrl->slot_ctrl = slot_ctrl;
|
||||
|
||||
/*
|
||||
* Wait for command completion.
|
||||
*/
|
||||
if (!ctrl->no_cmd_complete) {
|
||||
int poll = 0;
|
||||
/*
|
||||
* if hotplug interrupt is not enabled or command
|
||||
* completed interrupt is not enabled, we need to poll
|
||||
* command completed event.
|
||||
*/
|
||||
if (!(slot_ctrl & PCI_EXP_SLTCTL_HPIE) ||
|
||||
!(slot_ctrl & PCI_EXP_SLTCTL_CCIE))
|
||||
poll = 1;
|
||||
pcie_wait_cmd(ctrl, poll);
|
||||
}
|
||||
mutex_unlock(&ctrl->ctrl_lock);
|
||||
}
|
||||
|
||||
@ -773,15 +771,6 @@ struct controller *pcie_init(struct pcie_device *dev)
|
||||
mutex_init(&ctrl->ctrl_lock);
|
||||
init_waitqueue_head(&ctrl->queue);
|
||||
dbg_ctrl(ctrl);
|
||||
/*
|
||||
* Controller doesn't notify of command completion if the "No
|
||||
* Command Completed Support" bit is set in Slot Capability
|
||||
* register or the controller supports none of power
|
||||
* controller, attention led, power led and EMI.
|
||||
*/
|
||||
if (NO_CMD_CMPL(ctrl) ||
|
||||
!(POWER_CTRL(ctrl) | ATTN_LED(ctrl) | PWR_LED(ctrl) | EMI(ctrl)))
|
||||
ctrl->no_cmd_complete = 1;
|
||||
|
||||
/* Check if Data Link Layer Link Active Reporting is implemented */
|
||||
pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &link_cap);
|
||||
@ -794,7 +783,7 @@ struct controller *pcie_init(struct pcie_device *dev)
|
||||
pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
|
||||
PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
|
||||
PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
|
||||
PCI_EXP_SLTSTA_CC);
|
||||
PCI_EXP_SLTSTA_CC | PCI_EXP_SLTSTA_DLLSC);
|
||||
|
||||
/* Disable software notification */
|
||||
pcie_disable_notification(ctrl);
|
||||
|
||||
@ -149,15 +149,14 @@ static void msi_set_enable(struct pci_dev *dev, int enable)
|
||||
pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
|
||||
}
|
||||
|
||||
static void msix_set_enable(struct pci_dev *dev, int enable)
|
||||
static void msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set)
|
||||
{
|
||||
u16 control;
|
||||
u16 ctrl;
|
||||
|
||||
pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
|
||||
control &= ~PCI_MSIX_FLAGS_ENABLE;
|
||||
if (enable)
|
||||
control |= PCI_MSIX_FLAGS_ENABLE;
|
||||
pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control);
|
||||
pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
|
||||
ctrl &= ~clear;
|
||||
ctrl |= set;
|
||||
pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl);
|
||||
}
|
||||
|
||||
static inline __attribute_const__ u32 msi_mask(unsigned x)
|
||||
@ -168,16 +167,6 @@ static inline __attribute_const__ u32 msi_mask(unsigned x)
|
||||
return (1 << (1 << x)) - 1;
|
||||
}
|
||||
|
||||
static inline __attribute_const__ u32 msi_capable_mask(u16 control)
|
||||
{
|
||||
return msi_mask((control >> 1) & 7);
|
||||
}
|
||||
|
||||
static inline __attribute_const__ u32 msi_enabled_mask(u16 control)
|
||||
{
|
||||
return msi_mask((control >> 4) & 7);
|
||||
}
|
||||
|
||||
/*
|
||||
* PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to
|
||||
* mask all MSI interrupts by clearing the MSI enable bit does not work
|
||||
@ -460,7 +449,8 @@ static void __pci_restore_msi_state(struct pci_dev *dev)
|
||||
arch_restore_msi_irqs(dev);
|
||||
|
||||
pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
|
||||
msi_mask_irq(entry, msi_capable_mask(control), entry->masked);
|
||||
msi_mask_irq(entry, msi_mask(entry->msi_attrib.multi_cap),
|
||||
entry->masked);
|
||||
control &= ~PCI_MSI_FLAGS_QSIZE;
|
||||
control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE;
|
||||
pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
|
||||
@ -469,26 +459,23 @@ static void __pci_restore_msi_state(struct pci_dev *dev)
|
||||
static void __pci_restore_msix_state(struct pci_dev *dev)
|
||||
{
|
||||
struct msi_desc *entry;
|
||||
u16 control;
|
||||
|
||||
if (!dev->msix_enabled)
|
||||
return;
|
||||
BUG_ON(list_empty(&dev->msi_list));
|
||||
entry = list_first_entry(&dev->msi_list, struct msi_desc, list);
|
||||
pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
|
||||
|
||||
/* route the table */
|
||||
pci_intx_for_msi(dev, 0);
|
||||
control |= PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL;
|
||||
pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control);
|
||||
msix_clear_and_set_ctrl(dev, 0,
|
||||
PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL);
|
||||
|
||||
arch_restore_msi_irqs(dev);
|
||||
list_for_each_entry(entry, &dev->msi_list, list) {
|
||||
msix_mask_irq(entry, entry->masked);
|
||||
}
|
||||
|
||||
control &= ~PCI_MSIX_FLAGS_MASKALL;
|
||||
pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control);
|
||||
msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
|
||||
}
|
||||
|
||||
void pci_restore_msi_state(struct pci_dev *dev)
|
||||
@ -626,6 +613,7 @@ static int msi_capability_init(struct pci_dev *dev, int nvec)
|
||||
entry->msi_attrib.maskbit = !!(control & PCI_MSI_FLAGS_MASKBIT);
|
||||
entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */
|
||||
entry->msi_attrib.pos = dev->msi_cap;
|
||||
entry->msi_attrib.multi_cap = (control & PCI_MSI_FLAGS_QMASK) >> 1;
|
||||
|
||||
if (control & PCI_MSI_FLAGS_64BIT)
|
||||
entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_64;
|
||||
@ -634,7 +622,7 @@ static int msi_capability_init(struct pci_dev *dev, int nvec)
|
||||
/* All MSIs are unmasked by default, Mask them all */
|
||||
if (entry->msi_attrib.maskbit)
|
||||
pci_read_config_dword(dev, entry->mask_pos, &entry->masked);
|
||||
mask = msi_capable_mask(control);
|
||||
mask = msi_mask(entry->msi_attrib.multi_cap);
|
||||
msi_mask_irq(entry, mask, mask);
|
||||
|
||||
list_add_tail(&entry->list, &dev->msi_list);
|
||||
@ -743,12 +731,10 @@ static int msix_capability_init(struct pci_dev *dev,
|
||||
u16 control;
|
||||
void __iomem *base;
|
||||
|
||||
pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
|
||||
|
||||
/* Ensure MSI-X is disabled while it is set up */
|
||||
control &= ~PCI_MSIX_FLAGS_ENABLE;
|
||||
pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control);
|
||||
msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
|
||||
|
||||
pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
|
||||
/* Request & Map MSI-X table region */
|
||||
base = msix_map_region(dev, msix_table_size(control));
|
||||
if (!base)
|
||||
@ -767,8 +753,8 @@ static int msix_capability_init(struct pci_dev *dev,
|
||||
* MSI-X registers. We need to mask all the vectors to prevent
|
||||
* interrupts coming in before they're fully set up.
|
||||
*/
|
||||
control |= PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE;
|
||||
pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control);
|
||||
msix_clear_and_set_ctrl(dev, 0,
|
||||
PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE);
|
||||
|
||||
msix_program_entries(dev, entries);
|
||||
|
||||
@ -780,8 +766,7 @@ static int msix_capability_init(struct pci_dev *dev,
|
||||
pci_intx_for_msi(dev, 0);
|
||||
dev->msix_enabled = 1;
|
||||
|
||||
control &= ~PCI_MSIX_FLAGS_MASKALL;
|
||||
pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control);
|
||||
msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
|
||||
|
||||
return 0;
|
||||
|
||||
@ -882,7 +867,6 @@ void pci_msi_shutdown(struct pci_dev *dev)
|
||||
{
|
||||
struct msi_desc *desc;
|
||||
u32 mask;
|
||||
u16 ctrl;
|
||||
|
||||
if (!pci_msi_enable || !dev || !dev->msi_enabled)
|
||||
return;
|
||||
@ -895,8 +879,7 @@ void pci_msi_shutdown(struct pci_dev *dev)
|
||||
dev->msi_enabled = 0;
|
||||
|
||||
/* Return the device with MSI unmasked as initial states */
|
||||
pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &ctrl);
|
||||
mask = msi_capable_mask(ctrl);
|
||||
mask = msi_mask(desc->msi_attrib.multi_cap);
|
||||
/* Keep cached state to be restored */
|
||||
arch_msi_mask_irq(desc, mask, ~mask);
|
||||
|
||||
@ -1001,7 +984,7 @@ void pci_msix_shutdown(struct pci_dev *dev)
|
||||
arch_msix_mask_irq(entry, 1);
|
||||
}
|
||||
|
||||
msix_set_enable(dev, 0);
|
||||
msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
|
||||
pci_intx_for_msi(dev, 1);
|
||||
dev->msix_enabled = 0;
|
||||
}
|
||||
@ -1065,7 +1048,7 @@ void pci_msi_init_pci_dev(struct pci_dev *dev)
|
||||
|
||||
dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX);
|
||||
if (dev->msix_cap)
|
||||
msix_set_enable(dev, 0);
|
||||
msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
|
||||
}
|
||||
|
||||
/**
|
||||
|
||||
@ -161,8 +161,8 @@ enum acpi_attr_enum {
|
||||
static void dsm_label_utf16s_to_utf8s(union acpi_object *obj, char *buf)
|
||||
{
|
||||
int len;
|
||||
len = utf16s_to_utf8s((const wchar_t *)obj->string.pointer,
|
||||
obj->string.length,
|
||||
len = utf16s_to_utf8s((const wchar_t *)obj->buffer.pointer,
|
||||
obj->buffer.length,
|
||||
UTF16_LITTLE_ENDIAN,
|
||||
buf, PAGE_SIZE);
|
||||
buf[len] = '\n';
|
||||
@ -187,16 +187,22 @@ static int dsm_get_label(struct device *dev, char *buf,
|
||||
tmp = obj->package.elements;
|
||||
if (obj->type == ACPI_TYPE_PACKAGE && obj->package.count == 2 &&
|
||||
tmp[0].type == ACPI_TYPE_INTEGER &&
|
||||
tmp[1].type == ACPI_TYPE_STRING) {
|
||||
(tmp[1].type == ACPI_TYPE_STRING ||
|
||||
tmp[1].type == ACPI_TYPE_BUFFER)) {
|
||||
/*
|
||||
* The second string element is optional even when
|
||||
* this _DSM is implemented; when not implemented,
|
||||
* this entry must return a null string.
|
||||
*/
|
||||
if (attr == ACPI_ATTR_INDEX_SHOW)
|
||||
if (attr == ACPI_ATTR_INDEX_SHOW) {
|
||||
scnprintf(buf, PAGE_SIZE, "%llu\n", tmp->integer.value);
|
||||
else if (attr == ACPI_ATTR_LABEL_SHOW)
|
||||
} else if (attr == ACPI_ATTR_LABEL_SHOW) {
|
||||
if (tmp[1].type == ACPI_TYPE_STRING)
|
||||
scnprintf(buf, PAGE_SIZE, "%s\n",
|
||||
tmp[1].string.pointer);
|
||||
else if (tmp[1].type == ACPI_TYPE_BUFFER)
|
||||
dsm_label_utf16s_to_utf8s(tmp + 1, buf);
|
||||
}
|
||||
len = strlen(buf) > 0 ? strlen(buf) : -1;
|
||||
}
|
||||
|
||||
|
||||
@ -203,10 +203,6 @@ static int pcie_portdrv_probe(struct pci_dev *dev,
|
||||
(pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)))
|
||||
return -ENODEV;
|
||||
|
||||
if (!dev->irq && dev->pin) {
|
||||
dev_warn(&dev->dev, "device [%04x:%04x] has invalid IRQ; check vendor BIOS\n",
|
||||
dev->vendor, dev->device);
|
||||
}
|
||||
status = pcie_port_device_register(dev);
|
||||
if (status)
|
||||
return status;
|
||||
|
||||
@ -3405,6 +3405,8 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080,
|
||||
DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias);
|
||||
/* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */
|
||||
DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias);
|
||||
/* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */
|
||||
DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias);
|
||||
|
||||
static struct pci_dev *pci_func_0_dma_source(struct pci_dev *dev)
|
||||
{
|
||||
|
||||
@ -25,7 +25,8 @@ void write_msi_msg(unsigned int irq, struct msi_msg *msg);
|
||||
struct msi_desc {
|
||||
struct {
|
||||
__u8 is_msix : 1;
|
||||
__u8 multiple: 3; /* log2 number of messages */
|
||||
__u8 multiple: 3; /* log2 num of messages allocated */
|
||||
__u8 multi_cap : 3; /* log2 num of messages supported */
|
||||
__u8 maskbit : 1; /* mask-pending bit supported ? */
|
||||
__u8 is_64 : 1; /* Address size: 0=32bit 1=64bit */
|
||||
__u8 pos; /* Location of the msi capability */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user