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drm/i915/psr: Don't skip both TP1 and TP2/3 on hsw/bdw

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WA 0479 says: "Do not skip both TP1 and TP2/TP3". Let's just
stick the minimum 100us TP2/3 time in there to avoid that.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230609141404.12729-12-ville.syrjala@linux.intel.com
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
This commit is contained in:
Ville Syrjälä 2023-06-09 17:14:02 +03:00
parent 4d2391a0dd
commit 1d3ebcfc5d
1 changed files with 9 additions and 0 deletions
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9
drivers/gpu/drm/i915/display/intel_psr.c
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@ -628,6 +628,15 @@ static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp)
else
val |= EDP_PSR_TP2_TP3_TIME_2500us;
/*
* WA 0479: hsw,bdw
* "Do not skip both TP1 and TP2/TP3"
*/
if (DISPLAY_VER(dev_priv) < 9 &&
connector->panel.vbt.psr.tp1_wakeup_time_us == 0 &&
connector->panel.vbt.psr.tp2_tp3_wakeup_time_us == 0)
val |= EDP_PSR_TP2_TP3_TIME_100us;
check_tp3_sel:
if (intel_dp_source_supports_tps3(dev_priv) &&
drm_dp_tps3_supported(intel_dp->dpcd))