staging: rtl8821ae: Fix typo in rtl8821ae/rtl8821ae.
Fix spelling typo in comment and printk within rtl8821ae/rtl8821ae. Signed-off-by: Masanari Iida <standby24x7@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Masanari Iida
Greg Kroah-Hartman
parent
da4d20162c
commit
1d80d8426d
@ -731,7 +731,7 @@ void rtl8821ae_dm_find_minimum_rssi(struct ieee80211_hw *hw)
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rtl_dm_dig->min_undecorated_pwdb_for_dm =
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rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
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RT_TRACE(COMP_BB_POWERSAVING, DBG_LOUD,
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("AP Ext Port or disconnet PWDB = 0x%x \n",
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("AP Ext Port or disconnect PWDB = 0x%x \n",
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rtl_dm_dig->min_undecorated_pwdb_for_dm));
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}
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RT_TRACE(COMP_DIG, DBG_LOUD, ("MinUndecoratedPWDBForDM =%d\n",
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@ -925,7 +925,7 @@ static void rtl8821ae_dm_dig(struct ieee80211_hw *hw)
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if (rtlpriv->falsealm_cnt.cnt_all > 10000) {
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RT_TRACE(COMP_DIG, DBG_LOUD,
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("rtl8821ae_dm_dig(): Abnornally false alarm case. \n"));
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("rtl8821ae_dm_dig(): Abnormally false alarm case. \n"));
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if (dm_digtable.large_fa_hit != 3)
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dm_digtable.large_fa_hit++;
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@ -1087,7 +1087,7 @@ static void rtl8821ae_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw)
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else
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falsealm_cnt->cnt_all = falsealm_cnt->cnt_ofdm_fail;
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/*reset OFDM FA coutner*/
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/*reset OFDM FA counter*/
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rtl_set_bbreg(hw, ODM_REG_OFDM_FA_RST_11AC, BIT(17), 1);
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rtl_set_bbreg(hw, ODM_REG_OFDM_FA_RST_11AC, BIT(17), 0);
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/* reset CCK FA counter*/
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@ -1316,7 +1316,7 @@ u8 rtl8812ae_hw_rate_to_mrate(
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/*-----------------------------------------------------------------------------
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* Function: odm_TxPwrTrackSetPwr88E()
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*
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* Overview: 88E change all channel tx power accordign to flag.
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* Overview: 88E change all channel tx power according to flag.
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* OFDM & CCK are all different.
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*
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* Input: NONE
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@ -1537,7 +1537,7 @@ void rtl8812ae_dm_txpwr_track_set_pwr(struct ieee80211_hw *hw,
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rtldm->modify_txagc_flag_path_b = false;
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RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
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("******Path_B pDM_Odm->Modify_TxAGC_Flag = FALSE \n"));
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("******Path_B dm_Odm->Modify_TxAGC_Flag = FALSE \n"));
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}
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}
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}
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@ -1654,7 +1654,7 @@ void rtl8812ae_dm_txpower_tracking_callback_thermalmeter
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if (delta > 0 && rtldm->txpower_track_control)
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{
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/*"delta" here is used to record the absolute value of differrence.*/
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/*"delta" here is used to record the absolute value of difference.*/
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delta = thermal_value > rtlefuse->eeprom_thermalmeter ? \
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(thermal_value - rtlefuse->eeprom_thermalmeter) : \
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(rtlefuse->eeprom_thermalmeter - thermal_value);
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@ -1976,7 +1976,7 @@ void rtl8821ae_phy_lccalibrate(
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/*-----------------------------------------------------------------------------
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* Function: odm_TxPwrTrackSetPwr88E()
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*
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* Overview: 88E change all channel tx power accordign to flag.
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* Overview: 88E change all channel tx power according to flag.
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* OFDM & CCK are all different.
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*
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* Input: NONE
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@ -2159,7 +2159,7 @@ void rtl8821ae_dm_txpower_tracking_callback_thermalmeter
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u8 *delta_swing_table_idx_tup_b;
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u8 *delta_swing_table_idx_tdown_b;
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/*2. Initilization ( 7 steps in total )*/
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/*2. Initialization ( 7 steps in total )*/
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rtl8821ae_get_delta_swing_table(hw, (u8**)&delta_swing_table_idx_tup_a,
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(u8**)&delta_swing_table_idx_tdown_a,
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(u8**)&delta_swing_table_idx_tup_b,
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@ -2244,7 +2244,7 @@ void rtl8821ae_dm_txpower_tracking_callback_thermalmeter
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if (delta > 0 && rtldm->txpower_track_control)
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{
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/*"delta" here is used to record the absolute value of differrence.*/
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/*"delta" here is used to record the absolute value of difference.*/
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delta = thermal_value > rtlefuse->eeprom_thermalmeter ? \
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(thermal_value - rtlefuse->eeprom_thermalmeter) : \
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(rtlefuse->eeprom_thermalmeter - thermal_value);
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@ -2613,11 +2613,11 @@ static void rtl8821ae_dm_check_edca_turbo(struct ieee80211_hw *hw)
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RT_TRACE(COMP_TURBO, DBG_LOUD,
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("rtl8821ae_dm_check_edca_turbo=====>"));
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RT_TRACE(COMP_TURBO, DBG_LOUD,
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("Orginial BE PARAM: 0x%x\n",
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("Original BE PARAM: 0x%x\n",
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rtl_read_dword(rtlpriv, DM_REG_EDCA_BE_11N)));
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/*===============================
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list paramter for different platform
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list parameter for different platform
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===============================*/
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b_last_is_cur_rdl_state = rtlpriv->dm.bis_cur_rdlstate;
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pb_is_cur_rdl_state = &( rtlpriv->dm.bis_cur_rdlstate);
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@ -2963,7 +2963,7 @@ void rtl8821ae_dm_dynamic_atc_switch(struct ieee80211_hw *hw)
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"Crystal cap = 0x%x, Crystal cap offset = %d\n",
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rtldm->crystal_cap, adjust_xtal));
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/*3.Adjudt Crystal Cap.*/
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/*3.Adjust Crystal Cap.*/
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if (adjust_xtal != 0){
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rtldm->is_freeze = 0;
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rtldm->crystal_cap += adjust_xtal;
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@ -164,7 +164,7 @@ static int _rtl8821ae_fw_free_to_go(struct ieee80211_hw *hw)
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if (counter >= FW_8821AE_POLLING_TIMEOUT_COUNT) {
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RT_TRACE(COMP_ERR, DBG_LOUD,
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("chksum report faill ! REG_MCUFWDL:0x%08x .\n",
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("chksum report fail ! REG_MCUFWDL:0x%08x .\n",
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value32));
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goto exit;
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}
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@ -368,7 +368,7 @@ static void _rtl8821ae_fill_h2c_command(struct ieee80211_hw *hw,
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wait_h2c_limmit--;
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if (wait_h2c_limmit == 0) {
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RT_TRACE(COMP_CMD, DBG_LOUD,
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("Wating too long for FW read "
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("Waiting too long for FW read "
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"clear HMEBox(%d)!\n", boxnum));
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break;
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}
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@ -378,7 +378,7 @@ static void _rtl8821ae_fill_h2c_command(struct ieee80211_hw *hw,
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isfw_read = _rtl8821ae_check_fw_read_last_h2c(hw, boxnum);
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u1b_tmp = rtl_read_byte(rtlpriv, 0x130);
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RT_TRACE(COMP_CMD, DBG_LOUD,
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("Wating for FW read clear HMEBox(%d)!!! "
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("Waiting for FW read clear HMEBox(%d)!!! "
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"0x130 = %2x\n", boxnum, u1b_tmp));
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}
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}
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@ -1179,7 +1179,7 @@ void rtl8821ae_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool b_dl_finished)
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("Set RSVD page location to Fw FAIL!!!!!!.\n"));
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}
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/*Shoud check FW support p2p or not.*/
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/*Should check FW support p2p or not.*/
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void rtl8821ae_set_p2p_ctw_period_cmd(struct ieee80211_hw *hw, u8 ctwindow)
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{
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u8 u1_ctwindow_period[1] ={ ctwindow};
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@ -142,7 +142,7 @@ void rtl8821ae_dm_bt_hw_coex_all_off(struct ieee80211_hw *hw);
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long rtl8821ae_dm_bt_get_rx_ss(struct ieee80211_hw *hw);
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void rtl8821ae_dm_bt_balance(struct ieee80211_hw *hw,
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bool b_balance_on, u8 ms0, u8 ms1);
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void rtl8821ae_dm_bt_agc_table(struct ieee80211_hw *hw, u8 tyep);
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void rtl8821ae_dm_bt_agc_table(struct ieee80211_hw *hw, u8 type);
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void rtl8821ae_dm_bt_bb_back_off_level(struct ieee80211_hw *hw, u8 type);
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u8 rtl8821ae_dm_bt_check_coex_rssi_state(struct ieee80211_hw *hw,
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u8 level_num, u8 rssi_thresh, u8 rssi_thresh1);
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@ -157,7 +157,7 @@ bool rtl8821ae_dm_bt_is_same_coexist_state(struct ieee80211_hw *hw)
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&&(rtlpcipriv->btcoexist.previous_state_h
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== rtlpcipriv->btcoexist.current_state_h)) {
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RT_TRACE(COMP_BT_COEXIST, DBG_DMESG,
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("[DM][BT], Coexist state do not chang!!\n"));
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("[DM][BT], Coexist state do not change!!\n"));
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return true;
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} else {
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RT_TRACE(COMP_BT_COEXIST, DBG_DMESG,
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@ -902,7 +902,7 @@ void rtl8821ae_dm_bt_set_bt_dm(struct ieee80211_hw *hw, struct btdm_8821ae *p_bt
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/*
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* Note:
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* We should add delay for making sure sw DacSwing can be set sucessfully.
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* We should add delay for making sure sw DacSwing can be set successfully.
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* because of that rtl8821ae_dm_bt_set_fw_2_ant_hid() and rtl8821ae_dm_bt_set_fw_tdma_ctrl()
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* will overwrite the reg 0x880.
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*/
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@ -1017,7 +1017,7 @@ static void _rtl8821ae_hw_configure(struct ieee80211_hw *hw)
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/* ARFB table 12 for 11ac 24G 1SS */
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rtl_write_dword(rtlpriv, REG_ARFR3, 0x00000015);
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rtl_write_dword(rtlpriv, REG_ARFR3 + 4, 0xffcff000);
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/* 0x420[7] = 0 , enable retry AMPDU in new AMPD not singal MPDU. */
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/* 0x420[7] = 0 , enable retry AMPDU in new AMPD not signal MPDU. */
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rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F00);
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rtl_write_byte(rtlpriv, REG_AMPDU_MAX_TIME, 0x70);
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@ -1407,7 +1407,7 @@ int rtl8821ae_hw_init(struct ieee80211_hw *hw)
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rtl8821ae_phy_mac_config(hw);
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/* because last function modify RCR, so we update
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* rcr var here, or TP will unstable for receive_config
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* is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx
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* is wrong, RX RCR_ACRC32 will cause TP unstable & Rx
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* RCR_APP_ICV will cause mac80211 unassoc for cisco 1252
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rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR);
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rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
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@ -1563,7 +1563,7 @@ static enum version_8821ae _rtl8821ae_read_chip_version(struct ieee80211_hw *hw)
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break;
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default:
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RT_TRACE(COMP_INIT, DBG_LOUD,
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("Chip Version ID: Unknow (0x%X).\n", version));
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("Chip Version ID: Unknown (0x%X).\n", version));
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break;
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}
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@ -2372,7 +2372,7 @@ static void _rtl8812ae_read_adapter_info(struct ieee80211_hw *hw, bool b_pseudo_
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if (rtlefuse->eeprom_channelplan == 0xff)
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rtlefuse->eeprom_channelplan = 0x7F;
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/* set channel paln to world wide 13 */
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/* set channel plan to world wide 13 */
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//rtlefuse->channel_plan = (u8) rtlefuse->eeprom_channelplan;
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/*parse xtal*/
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@ -2535,7 +2535,7 @@ static void _rtl8821ae_read_adapter_info(struct ieee80211_hw *hw, bool b_pseudo_
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if (rtlefuse->eeprom_channelplan == 0xff)
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rtlefuse->eeprom_channelplan = 0x7F;
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/* set channel paln to world wide 13 */
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/* set channel plan to world wide 13 */
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//rtlefuse->channel_plan = (u8) rtlefuse->eeprom_channelplan;
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/*parse xtal*/
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@ -86,7 +86,7 @@ void rtl8812ae_fixspur(
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/* 0x8AC[11:10] = 2'b10*/
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/* <20120914, Kordan> A workarould to resolve
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/* <20120914, Kordan> A workaround to resolve
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2480Mhz spur by setting ADC clock as 160M. (Asked by Binson)*/
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if (band_width == HT_CHANNEL_WIDTH_20 &&
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(channel == 13 || channel == 14)) {
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@ -107,7 +107,7 @@ void rtl8812ae_fixspur(
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}
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else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
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{
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/* <20120914, Kordan> A workarould to resolve
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/* <20120914, Kordan> A workaround to resolve
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2480Mhz spur by setting ADC clock as 160M. (Asked by Binson)*/
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if (band_width == HT_CHANNEL_WIDTH_20 &&
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(channel == 13 || channel == 14))
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@ -30,7 +30,7 @@
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#ifndef __RTL8821AE_PHY_H__
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#define __RTL8821AE_PHY_H__
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/*It must always set to 4, otherwise read efuse table secquence will be wrong.*/
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/*It must always set to 4, otherwise read efuse table sequence will be wrong.*/
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#define MAX_TX_COUNT 4
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#define TX_1S 0
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#define TX_2S 1
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@ -81,7 +81,7 @@
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{0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/* 0x47[7:0] = 00 gpio mode */ \
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{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/* suspend option all off */ \
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{0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x80, BIT7},/*0x14[7] = 1 turn on ZCD */ \
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{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x01, BIT0},/* 0x15[0] =1 trun on ZCD */ \
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{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x01, BIT0},/* 0x15[0] =1 turn on ZCD */ \
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{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x10, BIT4},/*0x23[4] = 1 hpon LDO sleep mode */ \
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{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x02, 0},/*0x8[1] = 0 ANA clk =500k */ \
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{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, BIT3}, /*0x04[11] = 2b'11 enable WL suspend for PCIe*/
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@ -91,7 +91,7 @@
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/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
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{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, 0}, /*0x04[11] = 2b'01enable WL suspend*/ \
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{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x10, 0},/*0x23[4] = 0 hpon LDO sleep mode leave */ \
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{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x01, 0},/* 0x15[0] =0 trun off ZCD */ \
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{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x01, 0},/* 0x15[0] =0 turn off ZCD */ \
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{0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x80, 0},/*0x14[7] = 0 turn off ZCD */ \
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{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/* gpio0~7 input mode */ \
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{0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/* gpio11 input mode, gpio10~8 input mode */
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@ -110,7 +110,7 @@
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{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xff},/* gpio0~7 output mode */ \
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{0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/* 0x47[7:0] = 00 gpio mode */ \
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{0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x80, BIT7},/*0x14[7] = 1 turn on ZCD */ \
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{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x01, BIT0},/* 0x15[0] =1 trun on ZCD */ \
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{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x01, BIT0},/* 0x15[0] =1 turn on ZCD */ \
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{0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x01, 0},/*0x12[0] = 0 force PFM mode */ \
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{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x10, BIT4},/*0x23[4] = 1 hpon LDO sleep mode */ \
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{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x02, 0},/*0x8[1] = 0 ANA clk =500k */ \
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@ -124,7 +124,7 @@
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/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
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{0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/*0x12[0] = 1 force PWM mode */ \
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{0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x80, 0},/*0x14[7] = 0 turn off ZCD */ \
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{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x01, 0},/* 0x15[0] =0 trun off ZCD */ \
|
||||
{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x01, 0},/* 0x15[0] =0 turn off ZCD */ \
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x10, 0},/*0x23[4] = 0 hpon LDO leave sleep mode */ \
|
||||
{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/* gpio0~7 input mode */ \
|
||||
{0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/* gpio11 input mode, gpio10~8 input mode */ \
|
||||
@ -204,7 +204,7 @@ extern struct wlan_pwr_cfg rtl8812_leave_lps_flow[RTL8812_TRANS_LPS_TO_ACT_STEP
|
||||
4: LPS--Low Power State
|
||||
5: SUS--Suspend
|
||||
|
||||
The transision from different states are defined below
|
||||
The transition from different states are defined below
|
||||
TRANS_CARDEMU_TO_ACT
|
||||
TRANS_ACT_TO_CARDEMU
|
||||
TRANS_CARDEMU_TO_SUS
|
||||
|
||||
@ -82,7 +82,7 @@ bool rtl_hal_pwrseqcmdparsing (struct rtl_priv* rtlpriv, u8 cut_version,
|
||||
value = value | (GET_PWR_CFG_VALUE(pwr_cfg_cmd)
|
||||
& GET_PWR_CFG_MASK(pwr_cfg_cmd));
|
||||
|
||||
/*Write the value back to sytem register*/
|
||||
/*Write the value back to system register*/
|
||||
rtl_write_byte(rtlpriv, offset, value);
|
||||
}
|
||||
break;
|
||||
|
||||
@ -596,13 +596,13 @@
|
||||
#define IMR_BCNDMAINT3 BIT(23) /* Beacon DMA Interrupt 3 */
|
||||
#define IMR_BCNDMAINT2 BIT(22) /* Beacon DMA Interrupt 2 */
|
||||
#define IMR_BCNDMAINT1 BIT(21) /* Beacon DMA Interrupt 1 */
|
||||
#define IMR_BCNDOK7 BIT(20) /* Beacon Queue DMA OK Interrup 7 */
|
||||
#define IMR_BCNDOK6 BIT(19) /* Beacon Queue DMA OK Interrup 6 */
|
||||
#define IMR_BCNDOK5 BIT(18) /* Beacon Queue DMA OK Interrup 5 */
|
||||
#define IMR_BCNDOK4 BIT(17) /* Beacon Queue DMA OK Interrup 4 */
|
||||
#define IMR_BCNDOK3 BIT(16) /* Beacon Queue DMA OK Interrup 3 */
|
||||
#define IMR_BCNDOK2 BIT(15) /* Beacon Queue DMA OK Interrup 2 */
|
||||
#define IMR_BCNDOK1 BIT(14) /* Beacon Queue DMA OK Interrup 1 */
|
||||
#define IMR_BCNDOK7 BIT(20) /* Beacon Queue DMA OK Interrupt 7 */
|
||||
#define IMR_BCNDOK6 BIT(19) /* Beacon Queue DMA OK Interrupt 6 */
|
||||
#define IMR_BCNDOK5 BIT(18) /* Beacon Queue DMA OK Interrupt 5 */
|
||||
#define IMR_BCNDOK4 BIT(17) /* Beacon Queue DMA OK Interrupt 4 */
|
||||
#define IMR_BCNDOK3 BIT(16) /* Beacon Queue DMA OK Interrupt 3 */
|
||||
#define IMR_BCNDOK2 BIT(15) /* Beacon Queue DMA OK Interrupt 2 */
|
||||
#define IMR_BCNDOK1 BIT(14) /* Beacon Queue DMA OK Interrupt 1 */
|
||||
#define IMR_ATIMEND_E BIT(13) /* ATIM Window End Extension for Win7 */
|
||||
#define IMR_TXERR BIT(11) /* Tx Error Flag Interrupt Status, write 1 clear. */
|
||||
#define IMR_RXERR BIT(10) /* Rx Error Flag INT Status, Write 1 clear */
|
||||
@ -613,7 +613,7 @@
|
||||
#define HWSET_MAX_SIZE 512
|
||||
#define EFUSE_MAX_SECTION 64
|
||||
#define EFUSE_REAL_CONTENT_LEN 256
|
||||
#define EFUSE_OOB_PROTECT_BYTES 18 /* PG data exclude header, dummy 7 bytes frome CP test and reserved 1byte.*/
|
||||
#define EFUSE_OOB_PROTECT_BYTES 18 /* PG data exclude header, dummy 7 bytes from CP test and reserved 1byte.*/
|
||||
|
||||
|
||||
#define EEPROM_DEFAULT_TSSI 0x0
|
||||
@ -1511,7 +1511,7 @@
|
||||
#define ROFDM0_TXCOEFF5 0xcb4
|
||||
#define ROFDM0_TXCOEFF6 0xcb8
|
||||
|
||||
/*Path_A RFE cotrol */
|
||||
/*Path_A RFE control */
|
||||
#define RA_RFE_CTRL_8812 0xcb8
|
||||
/*Path_B RFE control*/
|
||||
#define RB_RFE_CTRL_8812 0xeb8
|
||||
@ -2336,19 +2336,19 @@
|
||||
#define WOL_REASON_DEAUTH BIT(3)
|
||||
#define WOL_REASON_FW_DISCONNECT BIT(4)
|
||||
|
||||
#define RA_RFE_PINMUX 0xcb0 /* Path_A RFE cotrol pinmux*/
|
||||
#define RA_RFE_PINMUX 0xcb0 /* Path_A RFE control pinmux*/
|
||||
#define RB_RFE_PINMUX 0xeb0 /* Path_B RFE control pinmux*/
|
||||
|
||||
#define RA_RFE_INV 0xcb4
|
||||
#define RB_RFE_INV 0xeb4
|
||||
|
||||
/* RXIQC */
|
||||
#define RA_RXIQC_AB 0xc10 /*RxIQ imblance matrix coeff. A & B*/
|
||||
#define RA_RXIQC_CD 0xc14 /*RxIQ imblance matrix coeff. C & D*/
|
||||
#define RA_RXIQC_AB 0xc10 /*RxIQ imbalance matrix coeff. A & B*/
|
||||
#define RA_RXIQC_CD 0xc14 /*RxIQ imbalance matrix coeff. C & D*/
|
||||
#define RA_TXSCALE 0xc1c /* Pah_A TX scaling factor*/
|
||||
#define RB_TXSCALE 0xe1c /* Path_B TX scaling factor*/
|
||||
#define RB_RXIQC_AB 0xe10 /*RxIQ imblance matrix coeff. A & B*/
|
||||
#define RB_RXIQC_CD 0xe14 /*RxIQ imblance matrix coeff. C & D*/
|
||||
#define RB_RXIQC_AB 0xe10 /*RxIQ imbalance matrix coeff. A & B*/
|
||||
#define RB_RXIQC_CD 0xe14 /*RxIQ imbalance matrix coeff. C & D*/
|
||||
#define RXIQC_AC 0x02ff /*bit mask for IQC matrix element A & C*/
|
||||
#define RXIQC_BD 0x02ff0000 /*bit mask for IQC matrix element A & C*/
|
||||
|
||||
|
||||
@ -57,9 +57,9 @@ void rtl8821ae_init_aspm_vars(struct ieee80211_hw *hw)
|
||||
* 0 - Disable ASPM,
|
||||
* 1 - Enable ASPM without Clock Req,
|
||||
* 2 - Enable ASPM with Clock Req,
|
||||
* 3 - Alwyas Enable ASPM with Clock Req,
|
||||
* 3 - Always Enable ASPM with Clock Req,
|
||||
* 4 - Always Enable ASPM without Clock Req.
|
||||
* set defult to RTL8192CE:3 RTL8192E:2
|
||||
* set default to RTL8192CE:3 RTL8192E:2
|
||||
* */
|
||||
rtlpci->const_pci_aspm = 3;
|
||||
|
||||
|
||||
@ -244,7 +244,7 @@ static void _rtl8821ae_query_rxphystatus(struct ieee80211_hw *hw,
|
||||
cck_agc_rpt = cck_buf->cck_agc_rpt;
|
||||
|
||||
/* (1)Hardware does not provide RSSI for CCK */
|
||||
/* (2)PWDB, Average PWDB cacluated by
|
||||
/* (2)PWDB, Average PWDB calculated by
|
||||
* hardware (for rate adaptive) */
|
||||
if (ppsc->rfpwr_state == ERFON)
|
||||
cck_highpwr = (u8) rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2,
|
||||
@ -363,7 +363,7 @@ static void _rtl8821ae_query_rxphystatus(struct ieee80211_hw *hw,
|
||||
pstatus->rx_mimo_signalstrength[i] = (u8) rssi;
|
||||
}
|
||||
|
||||
/* (2)PWDB, Average PWDB cacluated by
|
||||
/* (2)PWDB, Average PWDB calculated by
|
||||
* hardware (for rate adaptive) */
|
||||
rx_pwr_all = ((p_drvinfo->pwdb_all >> 1) & 0x7f) - 110;
|
||||
|
||||
@ -603,7 +603,7 @@ bool rtl8821ae_rx_query_desc(struct ieee80211_hw *hw,
|
||||
|
||||
/* hw will set status->decrypted true, if it finds the
|
||||
* frame is open data frame or mgmt frame. */
|
||||
/* So hw will not decryption robust managment frame
|
||||
/* So hw will not decryption robust management frame
|
||||
* for IEEE80211w but still set status->decrypted
|
||||
* true, so here we should set it back to undecrypted
|
||||
* for IEEE80211w frame, and mac80211 sw will help
|
||||
|
||||
Loading…
Reference in New Issue
Block a user