Merge branch 'clk-uniphier' into clk-next
* clk-uniphier: clk: uniphier: fix DAPLL2 clock rate of Pro5 clk: uniphier: fix parent of miodmac clock data
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1d96ad64c9
@ -13,6 +13,8 @@
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* GNU General Public License for more details.
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*/
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#include <linux/stddef.h>
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#include "clk-uniphier.h"
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#define UNIPHIER_MIO_CLK_SD_FIXED \
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@ -73,15 +75,12 @@
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#define UNIPHIER_MIO_CLK_USB2_PHY(idx, ch) \
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UNIPHIER_CLK_GATE("usb2" #ch "-phy", (idx), "usb2", 0x20 + 0x200 * (ch), 29)
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#define UNIPHIER_MIO_CLK_DMAC(idx) \
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UNIPHIER_CLK_GATE("miodmac", (idx), "stdmac", 0x20, 25)
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const struct uniphier_clk_data uniphier_ld4_mio_clk_data[] = {
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UNIPHIER_MIO_CLK_SD_FIXED,
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UNIPHIER_MIO_CLK_SD(0, 0),
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UNIPHIER_MIO_CLK_SD(1, 1),
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UNIPHIER_MIO_CLK_SD(2, 2),
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UNIPHIER_MIO_CLK_DMAC(7),
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UNIPHIER_CLK_GATE("miodmac", 7, NULL, 0x20, 25),
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UNIPHIER_MIO_CLK_USB2(8, 0),
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UNIPHIER_MIO_CLK_USB2(9, 1),
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UNIPHIER_MIO_CLK_USB2(10, 2),
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@ -123,7 +123,7 @@ const struct uniphier_clk_data uniphier_sld8_sys_clk_data[] = {
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const struct uniphier_clk_data uniphier_pro5_sys_clk_data[] = {
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UNIPHIER_CLK_FACTOR("spll", -1, "ref", 120, 1), /* 2400 MHz */
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UNIPHIER_CLK_FACTOR("dapll1", -1, "ref", 128, 1), /* 2560 MHz */
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UNIPHIER_CLK_FACTOR("dapll2", -1, "ref", 144, 125), /* 2949.12 MHz */
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UNIPHIER_CLK_FACTOR("dapll2", -1, "dapll1", 144, 125), /* 2949.12 MHz */
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UNIPHIER_CLK_FACTOR("uart", 0, "dapll2", 1, 40),
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UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 48),
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UNIPHIER_PRO5_SYS_CLK_NAND(2),
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