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fpga: microchip-spi: move SPI I/O buffers out of stack

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As spi-summary doc says:
 > I/O buffers use the usual Linux rules, and must be DMA-safe.
 > You'd normally allocate them from the heap or free page pool.
 > Don't use the stack, or anything that's declared "static".

Replace spi_write() with spi_write_then_read(), which is dma-safe for
on-stack buffers. Use cacheline aligned buffers for transfers used in
spi_sync_transfer().

Although everything works OK with stack-located I/O buffers, better
follow the doc to be safe.

Fixes: 5f8d4a9008 ("fpga: microchip-spi: add Microchip MPF FPGA manager")
Signed-off-by: Ivan Bornyakov <i.bornyakov@metrotek.ru>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Xu Yilun <yilun.xu@intel.com>
Link: https://lore.kernel.org/r/20221230092922.18822-2-i.bornyakov@metrotek.ru
Signed-off-by: Xu Yilun <yilun.xu@intel.com>
This commit is contained in:
Ivan Bornyakov 2022-12-30 12:29:20 +03:00 committed by Xu Yilun
parent 1b929c02af
commit 1da53d23a4
No known key found for this signature in database
GPG Key ID: FCB70381A4A08CDA
1 changed files with 47 additions and 46 deletions
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93
drivers/fpga/microchip-spi.c
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@ -42,46 +42,55 @@
struct mpf_priv { struct mpf_priv {
struct spi_device *spi; struct spi_device *spi;
bool program_mode; bool program_mode;
u8 tx __aligned(ARCH_KMALLOC_MINALIGN);
u8 rx;
}; };
static int mpf_read_status(struct spi_device *spi) static int mpf_read_status(struct mpf_priv *priv)
{ {
u8 status = 0, status_command = MPF_SPI_READ_STATUS;
struct spi_transfer xfers[2] = { 0 };
int ret;
/* /*
* HW status is returned on MISO in the first byte after CS went * HW status is returned on MISO in the first byte after CS went
* active. However, first reading can be inadequate, so we submit * active. However, first reading can be inadequate, so we submit
* two identical SPI transfers and use result of the later one. * two identical SPI transfers and use result of the later one.
*/ */
xfers[0].tx_buf = &status_command; struct spi_transfer xfers[2] = {
xfers[1].tx_buf = &status_command; {
xfers[0].rx_buf = &status; .tx_buf = &priv->tx,
xfers[1].rx_buf = &status; .rx_buf = &priv->rx,
xfers[0].len = 1; .len = 1,
xfers[1].len = 1; .cs_change = 1,
xfers[0].cs_change = 1; }, {
.tx_buf = &priv->tx,
.rx_buf = &priv->rx,
.len = 1,
},
};
u8 status;
int ret;
ret = spi_sync_transfer(spi, xfers, 2); priv->tx = MPF_SPI_READ_STATUS;
ret = spi_sync_transfer(priv->spi, xfers, 2);
if (ret)
return ret;
status = priv->rx;
if ((status & MPF_STATUS_SPI_VIOLATION) || if ((status & MPF_STATUS_SPI_VIOLATION) ||
(status & MPF_STATUS_SPI_ERROR)) (status & MPF_STATUS_SPI_ERROR))
ret = -EIO; return -EIO;
return ret ? : status; return status;
} }
static enum fpga_mgr_states mpf_ops_state(struct fpga_manager *mgr) static enum fpga_mgr_states mpf_ops_state(struct fpga_manager *mgr)
{ {
struct mpf_priv *priv = mgr->priv; struct mpf_priv *priv = mgr->priv;
struct spi_device *spi;
bool program_mode; bool program_mode;
int status; int status;
spi = priv->spi;
program_mode = priv->program_mode; program_mode = priv->program_mode;
status = mpf_read_status(spi); status = mpf_read_status(priv);
if (!program_mode && !status) if (!program_mode && !status)
return FPGA_MGR_STATE_OPERATING; return FPGA_MGR_STATE_OPERATING;
@ -186,12 +195,12 @@ static int mpf_ops_parse_header(struct fpga_manager *mgr,
} }
/* Poll HW status until busy bit is cleared and mask bits are set. */ /* Poll HW status until busy bit is cleared and mask bits are set. */
static int mpf_poll_status(struct spi_device *spi, u8 mask) static int mpf_poll_status(struct mpf_priv *priv, u8 mask)
{ {
int status, retries = MPF_STATUS_POLL_RETRIES; int status, retries = MPF_STATUS_POLL_RETRIES;
while (retries--) { while (retries--) {
status = mpf_read_status(spi); status = mpf_read_status(priv);
if (status < 0) if (status < 0)
return status; return status;
@ -205,32 +214,32 @@ static int mpf_poll_status(struct spi_device *spi, u8 mask)
return -EBUSY; return -EBUSY;
} }
static int mpf_spi_write(struct spi_device *spi, const void *buf, size_t buf_size) static int mpf_spi_write(struct mpf_priv *priv, const void *buf, size_t buf_size)
{ {
int status = mpf_poll_status(spi, 0); int status = mpf_poll_status(priv, 0);
if (status < 0) if (status < 0)
return status; return status;
return spi_write(spi, buf, buf_size); return spi_write_then_read(priv->spi, buf, buf_size, NULL, 0);
} }
static int mpf_spi_write_then_read(struct spi_device *spi, static int mpf_spi_write_then_read(struct mpf_priv *priv,
const void *txbuf, size_t txbuf_size, const void *txbuf, size_t txbuf_size,
void *rxbuf, size_t rxbuf_size) void *rxbuf, size_t rxbuf_size)
{ {
const u8 read_command[] = { MPF_SPI_READ_DATA }; const u8 read_command[] = { MPF_SPI_READ_DATA };
int ret; int ret;
ret = mpf_spi_write(spi, txbuf, txbuf_size); ret = mpf_spi_write(priv, txbuf, txbuf_size);
if (ret) if (ret)
return ret; return ret;
ret = mpf_poll_status(spi, MPF_STATUS_READY); ret = mpf_poll_status(priv, MPF_STATUS_READY);
if (ret < 0) if (ret < 0)
return ret; return ret;
return spi_write_then_read(spi, read_command, sizeof(read_command), return spi_write_then_read(priv->spi, read_command, sizeof(read_command),
rxbuf, rxbuf_size); rxbuf, rxbuf_size);
} }
@ -242,7 +251,6 @@ static int mpf_ops_write_init(struct fpga_manager *mgr,
const u8 isc_en_command[] = { MPF_SPI_ISC_ENABLE }; const u8 isc_en_command[] = { MPF_SPI_ISC_ENABLE };
struct mpf_priv *priv = mgr->priv; struct mpf_priv *priv = mgr->priv;
struct device *dev = &mgr->dev; struct device *dev = &mgr->dev;
struct spi_device *spi;
u32 isc_ret = 0; u32 isc_ret = 0;
int ret; int ret;
@ -251,9 +259,7 @@ static int mpf_ops_write_init(struct fpga_manager *mgr,
return -EOPNOTSUPP; return -EOPNOTSUPP;
} }
spi = priv->spi; ret = mpf_spi_write_then_read(priv, isc_en_command, sizeof(isc_en_command),
ret = mpf_spi_write_then_read(spi, isc_en_command, sizeof(isc_en_command),
&isc_ret, sizeof(isc_ret)); &isc_ret, sizeof(isc_ret));
if (ret || isc_ret) { if (ret || isc_ret) {
dev_err(dev, "Failed to enable ISC: spi_ret %d, isc_ret %u\n", dev_err(dev, "Failed to enable ISC: spi_ret %d, isc_ret %u\n",
@ -261,7 +267,7 @@ static int mpf_ops_write_init(struct fpga_manager *mgr,
return -EFAULT; return -EFAULT;
} }
ret = mpf_spi_write(spi, program_mode, sizeof(program_mode)); ret = mpf_spi_write(priv, program_mode, sizeof(program_mode));
if (ret) { if (ret) {
dev_err(dev, "Failed to enter program mode: %d\n", ret); dev_err(dev, "Failed to enter program mode: %d\n", ret);
return ret; return ret;
@ -274,11 +280,9 @@ static int mpf_ops_write_init(struct fpga_manager *mgr,
static int mpf_ops_write(struct fpga_manager *mgr, const char *buf, size_t count) static int mpf_ops_write(struct fpga_manager *mgr, const char *buf, size_t count)
{ {
u8 spi_frame_command[] = { MPF_SPI_FRAME };
struct spi_transfer xfers[2] = { 0 }; struct spi_transfer xfers[2] = { 0 };
struct mpf_priv *priv = mgr->priv; struct mpf_priv *priv = mgr->priv;
struct device *dev = &mgr->dev; struct device *dev = &mgr->dev;
struct spi_device *spi;
int ret, i; int ret, i;
if (count % MPF_SPI_FRAME_SIZE) { if (count % MPF_SPI_FRAME_SIZE) {
@ -287,18 +291,18 @@ static int mpf_ops_write(struct fpga_manager *mgr, const char *buf, size_t count
return -EINVAL; return -EINVAL;
} }
spi = priv->spi; xfers[0].tx_buf = &priv->tx;
xfers[0].len = 1;
xfers[0].tx_buf = spi_frame_command;
xfers[0].len = sizeof(spi_frame_command);
for (i = 0; i < count / MPF_SPI_FRAME_SIZE; i++) { for (i = 0; i < count / MPF_SPI_FRAME_SIZE; i++) {
xfers[1].tx_buf = buf + i * MPF_SPI_FRAME_SIZE; xfers[1].tx_buf = buf + i * MPF_SPI_FRAME_SIZE;
xfers[1].len = MPF_SPI_FRAME_SIZE; xfers[1].len = MPF_SPI_FRAME_SIZE;
ret = mpf_poll_status(spi, 0); ret = mpf_poll_status(priv, 0);
if (ret >= 0) if (ret >= 0) {
ret = spi_sync_transfer(spi, xfers, ARRAY_SIZE(xfers)); priv->tx = MPF_SPI_FRAME;
ret = spi_sync_transfer(priv->spi, xfers, ARRAY_SIZE(xfers));
}
if (ret) { if (ret) {
dev_err(dev, "Failed to write bitstream frame %d/%zu\n", dev_err(dev, "Failed to write bitstream frame %d/%zu\n",
@ -317,12 +321,9 @@ static int mpf_ops_write_complete(struct fpga_manager *mgr,
const u8 release_command[] = { MPF_SPI_RELEASE }; const u8 release_command[] = { MPF_SPI_RELEASE };
struct mpf_priv *priv = mgr->priv; struct mpf_priv *priv = mgr->priv;
struct device *dev = &mgr->dev; struct device *dev = &mgr->dev;
struct spi_device *spi;
int ret; int ret;
spi = priv->spi; ret = mpf_spi_write(priv, isc_dis_command, sizeof(isc_dis_command));
ret = mpf_spi_write(spi, isc_dis_command, sizeof(isc_dis_command));
if (ret) { if (ret) {
dev_err(dev, "Failed to disable ISC: %d\n", ret); dev_err(dev, "Failed to disable ISC: %d\n", ret);
return ret; return ret;
@ -330,7 +331,7 @@ static int mpf_ops_write_complete(struct fpga_manager *mgr,
usleep_range(1000, 2000); usleep_range(1000, 2000);
ret = mpf_spi_write(spi, release_command, sizeof(release_command)); ret = mpf_spi_write(priv, release_command, sizeof(release_command));
if (ret) { if (ret) {
dev_err(dev, "Failed to exit program mode: %d\n", ret); dev_err(dev, "Failed to exit program mode: %d\n", ret);
return ret; return ret;