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dt-bindings: Add Tegra SDHCI pad pdpu offset bindings

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Add bindings documentation for pad pull up and pull down offset values to be
programmed before executing automatic pad drive strength calibration.

Signed-off-by: Aapo Vienamo <avienamo@nvidia.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Aapo Vienamo 2018-08-30 18:06:04 +03:00 committed by Ulf Hansson
parent 3700cdf8e3
commit 1dd2a75809
1 changed files with 35 additions and 0 deletions
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35
Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
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@ -45,6 +45,37 @@ Optional properties for Tegra210 and Tegra186:
for controllers supporting multiple voltage levels. The order of names
should correspond to the pin configuration states in pinctrl-0 and
pinctrl-1.
- nvidia,only-1-8-v : The presence of this property indicates that the
controller operates at a 1.8 V fixed I/O voltage.
- nvidia,pad-autocal-pull-up-offset-3v3,
nvidia,pad-autocal-pull-down-offset-3v3 : Specify drive strength
calibration offsets for 3.3 V signaling modes.
- nvidia,pad-autocal-pull-up-offset-1v8,
nvidia,pad-autocal-pull-down-offset-1v8 : Specify drive strength
calibration offsets for 1.8 V signaling modes.
- nvidia,pad-autocal-pull-up-offset-3v3-timeout,
nvidia,pad-autocal-pull-down-offset-3v3-timeout : Specify drive
strength used as a fallback in case the automatic calibration times
out on a 3.3 V signaling mode.
- nvidia,pad-autocal-pull-up-offset-1v8-timeout,
nvidia,pad-autocal-pull-down-offset-1v8-timeout : Specify drive
strength used as a fallback in case the automatic calibration times
out on a 1.8 V signaling mode.
- nvidia,pad-autocal-pull-up-offset-sdr104,
nvidia,pad-autocal-pull-down-offset-sdr104 : Specify drive strength
calibration offsets for SDR104 mode.
- nvidia,pad-autocal-pull-up-offset-hs400,
nvidia,pad-autocal-pull-down-offset-hs400 : Specify drive strength
calibration offsets for HS400 mode.
Notes on the pad calibration pull up and pulldown offset values:
- The property values are drive codes which are programmed into the
PD_OFFSET and PU_OFFSET sections of the
SDHCI_TEGRA_AUTO_CAL_CONFIG register.
- A higher value corresponds to higher drive strength. Please refer
to the reference manual of the SoC for correct values.
- The SDR104 and HS400 timing specific values are used in
corresponding modes if specified.
Example:
sdhci@700b0000 {
@ -58,5 +89,9 @@ sdhci@700b0000 {
pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
pinctrl-0 = <&sdmmc1_3v3>;
pinctrl-1 = <&sdmmc1_1v8>;
nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
status = "disabled";
};