drm/amd/swsmu: enable more Pstates profile levels for SMU v14.0.0 and v14.0.1
V1: This patch enables following UMD stable Pstates profile levels for power_dpm_force_performance_level interface. - profile_peak - profile_min_mclk - profile_min_sclk - profile_standard V2: Fix conflict with commit "drm/amd/pm: smu v14.0.4 reuse smu v14.0.0 dpmtable " V3: Add VCLK1 and DCLK1 support for SMU V14.0.1 And avoid to set VCLK1 and DCLK1 for SMU v14.0.0 Signed-off-by: Li Ma <li.ma@amd.com> Reviewed-by: Tim Huang <tim.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Li Ma
Alex Deucher
parent
12b435a40c
commit
1dd34092c1
@ -65,6 +65,10 @@
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#define SMU_MALL_PG_CONFIG_DEFAULT SMU_MALL_PG_CONFIG_DRIVER_CONTROL_ALWAYS_ON
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#define SMU_14_0_0_UMD_PSTATE_GFXCLK 700
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#define SMU_14_0_0_UMD_PSTATE_SOCCLK 678
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#define SMU_14_0_0_UMD_PSTATE_FCLK 1800
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#define FEATURE_MASK(feature) (1ULL << feature)
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#define SMC_DPM_FEATURE ( \
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FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \
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@ -725,7 +729,7 @@ static int smu_v14_0_common_get_dpm_freq_by_index(struct smu_context *smu,
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{
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if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1))
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smu_v14_0_1_get_dpm_freq_by_index(smu, clk_type, dpm_level, freq);
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else
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else if (clk_type != SMU_VCLK1 && clk_type != SMU_DCLK1)
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smu_v14_0_0_get_dpm_freq_by_index(smu, clk_type, dpm_level, freq);
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return 0;
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@ -818,9 +822,11 @@ static int smu_v14_0_1_get_dpm_ultimate_freq(struct smu_context *smu,
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break;
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case SMU_MCLK:
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case SMU_UCLK:
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case SMU_FCLK:
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max_dpm_level = 0;
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break;
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case SMU_FCLK:
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max_dpm_level = clk_table->NumFclkLevelsEnabled - 1;
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break;
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case SMU_SOCCLK:
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max_dpm_level = clk_table->NumSocClkLevelsEnabled - 1;
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break;
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@ -855,7 +861,7 @@ static int smu_v14_0_1_get_dpm_ultimate_freq(struct smu_context *smu,
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min_dpm_level = clk_table->NumMemPstatesEnabled - 1;
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break;
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case SMU_FCLK:
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min_dpm_level = clk_table->NumFclkLevelsEnabled - 1;
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min_dpm_level = 0;
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break;
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case SMU_SOCCLK:
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min_dpm_level = 0;
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@ -936,9 +942,11 @@ static int smu_v14_0_0_get_dpm_ultimate_freq(struct smu_context *smu,
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break;
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case SMU_MCLK:
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case SMU_UCLK:
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case SMU_FCLK:
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max_dpm_level = 0;
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break;
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case SMU_FCLK:
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max_dpm_level = clk_table->NumFclkLevelsEnabled - 1;
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break;
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case SMU_SOCCLK:
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max_dpm_level = clk_table->NumSocClkLevelsEnabled - 1;
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break;
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@ -969,7 +977,7 @@ static int smu_v14_0_0_get_dpm_ultimate_freq(struct smu_context *smu,
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min_dpm_level = clk_table->NumMemPstatesEnabled - 1;
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break;
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case SMU_FCLK:
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min_dpm_level = clk_table->NumFclkLevelsEnabled - 1;
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min_dpm_level = 0;
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break;
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case SMU_SOCCLK:
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min_dpm_level = 0;
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@ -1001,7 +1009,7 @@ static int smu_v14_0_common_get_dpm_ultimate_freq(struct smu_context *smu,
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{
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if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1))
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smu_v14_0_1_get_dpm_ultimate_freq(smu, clk_type, min, max);
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else
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else if (clk_type != SMU_VCLK1 && clk_type != SMU_DCLK1)
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smu_v14_0_0_get_dpm_ultimate_freq(smu, clk_type, min, max);
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return 0;
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@ -1020,9 +1028,15 @@ static int smu_v14_0_0_get_current_clk_freq(struct smu_context *smu,
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case SMU_VCLK:
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member_type = METRICS_AVERAGE_VCLK;
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break;
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case SMU_VCLK1:
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member_type = METRICS_AVERAGE_VCLK1;
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break;
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case SMU_DCLK:
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member_type = METRICS_AVERAGE_DCLK;
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break;
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case SMU_DCLK1:
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member_type = METRICS_AVERAGE_DCLK1;
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break;
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case SMU_MCLK:
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member_type = METRICS_AVERAGE_UCLK;
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break;
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@ -1106,7 +1120,7 @@ static int smu_v14_0_common_get_dpm_level_count(struct smu_context *smu,
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{
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if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1))
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smu_v14_0_1_get_dpm_level_count(smu, clk_type, count);
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else
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else if (clk_type != SMU_VCLK1 && clk_type != SMU_DCLK1)
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smu_v14_0_0_get_dpm_level_count(smu, clk_type, count);
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return 0;
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@ -1250,6 +1264,8 @@ static int smu_v14_0_0_force_clk_levels(struct smu_context *smu,
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case SMU_FCLK:
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case SMU_VCLK:
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case SMU_DCLK:
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case SMU_VCLK1:
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case SMU_DCLK1:
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ret = smu_v14_0_common_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
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if (ret)
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break;
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@ -1268,13 +1284,67 @@ static int smu_v14_0_0_force_clk_levels(struct smu_context *smu,
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return ret;
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}
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static int smu_v14_0_0_set_performance_level(struct smu_context *smu,
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static int smu_v14_0_common_get_dpm_profile_freq(struct smu_context *smu,
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enum amd_dpm_forced_level level,
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enum smu_clk_type clk_type,
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uint32_t *min_clk,
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uint32_t *max_clk)
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{
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uint32_t clk_limit = 0;
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int ret = 0;
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switch (clk_type) {
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case SMU_GFXCLK:
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case SMU_SCLK:
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clk_limit = SMU_14_0_0_UMD_PSTATE_GFXCLK;
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if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
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smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &clk_limit);
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else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK)
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smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_SCLK, &clk_limit, NULL);
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break;
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case SMU_SOCCLK:
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clk_limit = SMU_14_0_0_UMD_PSTATE_SOCCLK;
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if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
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smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &clk_limit);
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break;
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case SMU_FCLK:
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clk_limit = SMU_14_0_0_UMD_PSTATE_FCLK;
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if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
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smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &clk_limit);
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else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK)
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smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_FCLK, &clk_limit, NULL);
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break;
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case SMU_VCLK:
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smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL, &clk_limit);
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break;
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case SMU_VCLK1:
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smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_VCLK1, NULL, &clk_limit);
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break;
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case SMU_DCLK:
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smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &clk_limit);
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break;
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case SMU_DCLK1:
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smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_DCLK1, NULL, &clk_limit);
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break;
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default:
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ret = -EINVAL;
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break;
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}
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*min_clk = *max_clk = clk_limit;
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return ret;
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}
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static int smu_v14_0_common_set_performance_level(struct smu_context *smu,
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enum amd_dpm_forced_level level)
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{
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struct amdgpu_device *adev = smu->adev;
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uint32_t sclk_min = 0, sclk_max = 0;
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uint32_t fclk_min = 0, fclk_max = 0;
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uint32_t socclk_min = 0, socclk_max = 0;
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uint32_t vclk_min = 0, vclk_max = 0;
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uint32_t dclk_min = 0, dclk_max = 0;
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uint32_t vclk1_min = 0, vclk1_max = 0;
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uint32_t dclk1_min = 0, dclk1_max = 0;
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int ret = 0;
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switch (level) {
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@ -1282,28 +1352,54 @@ static int smu_v14_0_0_set_performance_level(struct smu_context *smu,
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smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &sclk_max);
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smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &fclk_max);
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smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &socclk_max);
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smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL, &vclk_max);
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smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &dclk_max);
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smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_VCLK1, NULL, &vclk1_max);
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smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_DCLK1, NULL, &dclk1_max);
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sclk_min = sclk_max;
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fclk_min = fclk_max;
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socclk_min = socclk_max;
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vclk_min = vclk_max;
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dclk_min = dclk_max;
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vclk1_min = vclk1_max;
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dclk1_min = dclk1_max;
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break;
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case AMD_DPM_FORCED_LEVEL_LOW:
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smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, NULL);
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smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_FCLK, &fclk_min, NULL);
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smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_SOCCLK, &socclk_min, NULL);
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smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_VCLK, &vclk_min, NULL);
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smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_DCLK, &dclk_min, NULL);
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smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_VCLK1, &vclk1_min, NULL);
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smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_DCLK1, &dclk1_min, NULL);
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sclk_max = sclk_min;
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fclk_max = fclk_min;
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socclk_max = socclk_min;
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vclk_max = vclk_min;
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dclk_max = dclk_min;
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vclk1_max = vclk1_min;
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dclk1_max = dclk1_min;
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break;
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case AMD_DPM_FORCED_LEVEL_AUTO:
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smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, &sclk_max);
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smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_FCLK, &fclk_min, &fclk_max);
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smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_SOCCLK, &socclk_min, &socclk_max);
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smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_VCLK, &vclk_min, &vclk_max);
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smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_DCLK, &dclk_min, &dclk_max);
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smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_VCLK1, &vclk1_min, &vclk1_max);
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smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_DCLK1, &dclk1_min, &dclk1_max);
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break;
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case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
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case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
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case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
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case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
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/* Temporarily do nothing since the optimal clocks haven't been provided yet */
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smu_v14_0_common_get_dpm_profile_freq(smu, level, SMU_SCLK, &sclk_min, &sclk_max);
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smu_v14_0_common_get_dpm_profile_freq(smu, level, SMU_FCLK, &fclk_min, &fclk_max);
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smu_v14_0_common_get_dpm_profile_freq(smu, level, SMU_SOCCLK, &socclk_min, &socclk_max);
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smu_v14_0_common_get_dpm_profile_freq(smu, level, SMU_VCLK, &vclk_min, &vclk_max);
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smu_v14_0_common_get_dpm_profile_freq(smu, level, SMU_DCLK, &dclk_min, &dclk_max);
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smu_v14_0_common_get_dpm_profile_freq(smu, level, SMU_VCLK1, &vclk1_min, &vclk1_max);
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smu_v14_0_common_get_dpm_profile_freq(smu, level, SMU_DCLK1, &dclk1_min, &dclk1_max);
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break;
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case AMD_DPM_FORCED_LEVEL_MANUAL:
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case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
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@ -1343,6 +1439,42 @@ static int smu_v14_0_0_set_performance_level(struct smu_context *smu,
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return ret;
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}
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if (vclk_min && vclk_max) {
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ret = smu_v14_0_0_set_soft_freq_limited_range(smu,
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SMU_VCLK,
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vclk_min,
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vclk_max);
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if (ret)
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return ret;
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}
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if (vclk1_min && vclk1_max) {
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ret = smu_v14_0_0_set_soft_freq_limited_range(smu,
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SMU_VCLK1,
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vclk1_min,
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vclk1_max);
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if (ret)
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return ret;
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}
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if (dclk_min && dclk_max) {
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ret = smu_v14_0_0_set_soft_freq_limited_range(smu,
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SMU_DCLK,
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dclk_min,
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dclk_max);
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if (ret)
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return ret;
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}
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if (dclk1_min && dclk1_max) {
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ret = smu_v14_0_0_set_soft_freq_limited_range(smu,
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SMU_DCLK1,
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dclk1_min,
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dclk1_max);
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if (ret)
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return ret;
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}
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return ret;
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}
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@ -1520,7 +1652,7 @@ static const struct pptable_funcs smu_v14_0_0_ppt_funcs = {
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.od_edit_dpm_table = smu_v14_0_od_edit_dpm_table,
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.print_clk_levels = smu_v14_0_0_print_clk_levels,
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.force_clk_levels = smu_v14_0_0_force_clk_levels,
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.set_performance_level = smu_v14_0_0_set_performance_level,
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.set_performance_level = smu_v14_0_common_set_performance_level,
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.set_fine_grain_gfx_freq_parameters = smu_v14_0_common_set_fine_grain_gfx_freq_parameters,
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.set_gfx_power_up_by_imu = smu_v14_0_set_gfx_power_up_by_imu,
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.dpm_set_vpe_enable = smu_v14_0_0_set_vpe_enable,
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