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drm/amdgpu: use psp_execute_load_ip_fw instead

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Replace the old ones with psp_execute_load_ip_fw.

Suggested-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Lang Yu
2023-07-08 12:43:14 +08:00
committed by Alex Deucher
parent 45b51acb38
commit 1ddcdb7cb6
9 changed files with 23 additions and 30 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
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@ -2920,19 +2920,6 @@ int psp_rlc_autoload_start(struct psp_context *psp)
return ret; return ret;
} }
int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
uint64_t cmd_gpu_addr, int cmd_size)
{
struct amdgpu_firmware_info ucode = {0};
ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM :
AMDGPU_UCODE_ID_VCN0_RAM;
ucode.mc_addr = cmd_gpu_addr;
ucode.ucode_size = cmd_size;
return psp_execute_ip_fw_load(&adev->psp, &ucode);
}
int psp_ring_cmd_submit(struct psp_context *psp, int psp_ring_cmd_submit(struct psp_context *psp,
uint64_t cmd_buf_mc_addr, uint64_t cmd_buf_mc_addr,
uint64_t fence_mc_addr, uint64_t fence_mc_addr,

2
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
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@ -466,8 +466,6 @@ int psp_execute_ip_fw_load(struct psp_context *psp,
struct amdgpu_firmware_info *ucode); struct amdgpu_firmware_info *ucode);
int psp_gpu_reset(struct amdgpu_device *adev); int psp_gpu_reset(struct amdgpu_device *adev);
int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
uint64_t cmd_gpu_addr, int cmd_size);
int psp_ta_init_shared_buf(struct psp_context *psp, int psp_ta_init_shared_buf(struct psp_context *psp,
struct ta_mem_context *mem_ctx); struct ta_mem_context *mem_ctx);

15
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
View File

@ -1239,3 +1239,18 @@ int amdgpu_vcn_ras_sw_init(struct amdgpu_device *adev)
return 0; return 0;
} }
int amdgpu_vcn_psp_update_sram(struct amdgpu_device *adev, int inst_idx,
enum AMDGPU_UCODE_ID ucode_id)
{
struct amdgpu_firmware_info ucode = {
.ucode_id = (ucode_id ? ucode_id :
(inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM :
AMDGPU_UCODE_ID_VCN0_RAM)),
.mc_addr = adev->vcn.inst[inst_idx].dpg_sram_gpu_addr,
.ucode_size = ((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr -
(uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr),
};
return psp_execute_ip_fw_load(&adev->psp, &ucode);
}

3
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
View File

@ -414,4 +414,7 @@ int amdgpu_vcn_ras_late_init(struct amdgpu_device *adev,
struct ras_common_if *ras_block); struct ras_common_if *ras_block);
int amdgpu_vcn_ras_sw_init(struct amdgpu_device *adev); int amdgpu_vcn_ras_sw_init(struct amdgpu_device *adev);
int amdgpu_vcn_psp_update_sram(struct amdgpu_device *adev, int inst_idx,
enum AMDGPU_UCODE_ID ucode_id);
#endif #endif

4
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
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@ -881,9 +881,7 @@ static int vcn_v2_0_start_dpg_mode(struct amdgpu_device *adev, bool indirect)
UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
if (indirect) if (indirect)
psp_update_vcn_sram(adev, 0, adev->vcn.inst->dpg_sram_gpu_addr, amdgpu_vcn_psp_update_sram(adev, 0, 0);
(uint32_t)((uintptr_t)adev->vcn.inst->dpg_sram_curr_addr -
(uintptr_t)adev->vcn.inst->dpg_sram_cpu_addr));
/* force RBC into idle state */ /* force RBC into idle state */
rb_bufsz = order_base_2(ring->ring_size); rb_bufsz = order_base_2(ring->ring_size);

4
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
View File

@ -912,9 +912,7 @@ static int vcn_v2_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo
UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
if (indirect) if (indirect)
psp_update_vcn_sram(adev, inst_idx, adev->vcn.inst[inst_idx].dpg_sram_gpu_addr, amdgpu_vcn_psp_update_sram(adev, inst_idx, 0);
(uint32_t)((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr -
(uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr));
ring = &adev->vcn.inst[inst_idx].ring_dec; ring = &adev->vcn.inst[inst_idx].ring_dec;
/* force RBC into idle state */ /* force RBC into idle state */

4
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
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@ -1037,9 +1037,7 @@ static int vcn_v3_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo
VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);
if (indirect) if (indirect)
psp_update_vcn_sram(adev, inst_idx, adev->vcn.inst[inst_idx].dpg_sram_gpu_addr, amdgpu_vcn_psp_update_sram(adev, inst_idx, 0);
(uint32_t)((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr -
(uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr));
ring = &adev->vcn.inst[inst_idx].ring_dec; ring = &adev->vcn.inst[inst_idx].ring_dec;
/* force RBC into idle state */ /* force RBC into idle state */

4
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
View File

@ -993,9 +993,7 @@ static int vcn_v4_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo
if (indirect) if (indirect)
psp_update_vcn_sram(adev, inst_idx, adev->vcn.inst[inst_idx].dpg_sram_gpu_addr, amdgpu_vcn_psp_update_sram(adev, inst_idx, 0);
(uint32_t)((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr -
(uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr));
ring = &adev->vcn.inst[inst_idx].ring_enc[0]; ring = &adev->vcn.inst[inst_idx].ring_enc[0];

4
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
View File

@ -778,9 +778,7 @@ static int vcn_v4_0_3_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, b
UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
if (indirect) if (indirect)
psp_update_vcn_sram(adev, 0, adev->vcn.inst[inst_idx].dpg_sram_gpu_addr, amdgpu_vcn_psp_update_sram(adev, inst_idx, AMDGPU_UCODE_ID_VCN0_RAM);
(uint32_t)((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr -
(uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr));
ring = &adev->vcn.inst[inst_idx].ring_enc[0]; ring = &adev->vcn.inst[inst_idx].ring_enc[0];