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drm/nvc0-: remove nasty fifo swmthd hack for flip completion method

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Not required anymore as flips are always done on the kernel's channel,
which means we can use a proper software object class instead.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2013-11-13 10:49:46 +10:00
parent 69a6146d1e
commit 1e303c03af
4 changed files with 9 additions and 26 deletions
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7
drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c
View File

@ -494,13 +494,6 @@ nvc0_fifo_isr_subfifo_intr(struct nvc0_fifo_priv *priv, int unit)
u32 mthd = (addr & 0x00003ffc); u32 mthd = (addr & 0x00003ffc);
u32 show = stat; u32 show = stat;
if (stat & 0x00200000) {
if (mthd == 0x0054) {
if (!nvc0_fifo_swmthd(priv, chid, 0x0500, 0x00000000))
show &= ~0x00200000;
}
}
if (stat & 0x00800000) { if (stat & 0x00800000) {
if (!nvc0_fifo_swmthd(priv, chid, mthd, data)) if (!nvc0_fifo_swmthd(priv, chid, mthd, data))
show &= ~0x00800000; show &= ~0x00800000;

7
drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c
View File

@ -481,13 +481,6 @@ nve0_fifo_isr_subfifo_intr(struct nve0_fifo_priv *priv, int unit)
u32 mthd = (addr & 0x00003ffc); u32 mthd = (addr & 0x00003ffc);
u32 show = stat; u32 show = stat;
if (stat & 0x00200000) {
if (mthd == 0x0054) {
if (!nve0_fifo_swmthd(priv, chid, 0x0500, 0x00000000))
show &= ~0x00200000;
}
}
if (stat & 0x00800000) { if (stat & 0x00800000) {
if (!nve0_fifo_swmthd(priv, chid, mthd, data)) if (!nve0_fifo_swmthd(priv, chid, mthd, data))
show &= ~0x00800000; show &= ~0x00800000;

14
drivers/gpu/drm/nouveau/nouveau_display.c
View File

@ -554,19 +554,15 @@ nouveau_page_flip_emit(struct nouveau_channel *chan,
goto fail; goto fail;
/* Emit the pageflip */ /* Emit the pageflip */
ret = RING_SPACE(chan, 3); ret = RING_SPACE(chan, 2);
if (ret) if (ret)
goto fail; goto fail;
if (nv_device(drm->device)->card_type < NV_C0) { if (nv_device(drm->device)->card_type < NV_C0)
BEGIN_NV04(chan, NvSubSw, NV_SW_PAGE_FLIP, 1); BEGIN_NV04(chan, NvSubSw, NV_SW_PAGE_FLIP, 1);
OUT_RING (chan, 0x00000000); else
OUT_RING (chan, 0x00000000); BEGIN_NVC0(chan, FermiSw, NV_SW_PAGE_FLIP, 1);
} else { OUT_RING (chan, 0x00000000);
BEGIN_NVC0(chan, 0, NV10_SUBCHAN_REF_CNT, 1);
OUT_RING (chan, 0);
BEGIN_IMC0(chan, 0, NVSW_SUBCHAN_PAGE_FLIP, 0x0000);
}
FIRE_RING (chan); FIRE_RING (chan);
ret = nouveau_fence_new(chan, false, pfence); ret = nouveau_fence_new(chan, false, pfence);

7
drivers/gpu/drm/nouveau/nouveau_dma.h
View File

@ -51,9 +51,11 @@ enum {
NvSubCtxSurf2D = 0, NvSubCtxSurf2D = 0,
NvSubSw = 1, NvSubSw = 1,
NvSubImageBlit = 2, NvSubImageBlit = 2,
NvSub2D = 3,
NvSubGdiRect = 3, NvSubGdiRect = 3,
NvSubCopy = 4,
NvSub2D = 3, /* DO NOT CHANGE - hardcoded for kepler gr fifo */
NvSubCopy = 4, /* DO NOT CHANGE - hardcoded for kepler gr fifo */
FermiSw = 5, /* DO NOT CHANGE (well.. 6/7 will work...) */
}; };
/* Object handles. */ /* Object handles. */
@ -194,7 +196,6 @@ WIND_RING(struct nouveau_channel *chan)
#define NV84_SUBCHAN_UEVENT 0x00000020 #define NV84_SUBCHAN_UEVENT 0x00000020
#define NV84_SUBCHAN_WRCACHE_FLUSH 0x00000024 #define NV84_SUBCHAN_WRCACHE_FLUSH 0x00000024
#define NV10_SUBCHAN_REF_CNT 0x00000050 #define NV10_SUBCHAN_REF_CNT 0x00000050
#define NVSW_SUBCHAN_PAGE_FLIP 0x00000054
#define NV11_SUBCHAN_DMA_SEMAPHORE 0x00000060 #define NV11_SUBCHAN_DMA_SEMAPHORE 0x00000060
#define NV11_SUBCHAN_SEMAPHORE_OFFSET 0x00000064 #define NV11_SUBCHAN_SEMAPHORE_OFFSET 0x00000064
#define NV11_SUBCHAN_SEMAPHORE_ACQUIRE 0x00000068 #define NV11_SUBCHAN_SEMAPHORE_ACQUIRE 0x00000068