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ARM: tegra: Fix naming in GPIO DT binding header

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According to the Tegra TRM, GPIOs are aggregated into /ports/ of 8 GPIOs,
not into /banks/. Fix <dt-bindings/gpio/tegra-gpio.h> to correctly reflect
this naming convention. While this seems like silly churn, it will become
slightly more important once we introduce the GPIO binding for upcoming
Tegra chips.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Stephen Warren 2016-04-05 13:25:07 -06:00 committed by Thierry Reding
parent f55532a0c0
commit 1e48b695d7
1 changed files with 34 additions and 34 deletions
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68
include/dt-bindings/gpio/tegra-gpio.h
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@ -12,40 +12,40 @@
#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/gpio.h>
#define TEGRA_GPIO_BANK_ID_A 0 #define TEGRA_GPIO_PORT_A 0
#define TEGRA_GPIO_BANK_ID_B 1 #define TEGRA_GPIO_PORT_B 1
#define TEGRA_GPIO_BANK_ID_C 2 #define TEGRA_GPIO_PORT_C 2
#define TEGRA_GPIO_BANK_ID_D 3 #define TEGRA_GPIO_PORT_D 3
#define TEGRA_GPIO_BANK_ID_E 4 #define TEGRA_GPIO_PORT_E 4
#define TEGRA_GPIO_BANK_ID_F 5 #define TEGRA_GPIO_PORT_F 5
#define TEGRA_GPIO_BANK_ID_G 6 #define TEGRA_GPIO_PORT_G 6
#define TEGRA_GPIO_BANK_ID_H 7 #define TEGRA_GPIO_PORT_H 7
#define TEGRA_GPIO_BANK_ID_I 8 #define TEGRA_GPIO_PORT_I 8
#define TEGRA_GPIO_BANK_ID_J 9 #define TEGRA_GPIO_PORT_J 9
#define TEGRA_GPIO_BANK_ID_K 10 #define TEGRA_GPIO_PORT_K 10
#define TEGRA_GPIO_BANK_ID_L 11 #define TEGRA_GPIO_PORT_L 11
#define TEGRA_GPIO_BANK_ID_M 12 #define TEGRA_GPIO_PORT_M 12
#define TEGRA_GPIO_BANK_ID_N 13 #define TEGRA_GPIO_PORT_N 13
#define TEGRA_GPIO_BANK_ID_O 14 #define TEGRA_GPIO_PORT_O 14
#define TEGRA_GPIO_BANK_ID_P 15 #define TEGRA_GPIO_PORT_P 15
#define TEGRA_GPIO_BANK_ID_Q 16 #define TEGRA_GPIO_PORT_Q 16
#define TEGRA_GPIO_BANK_ID_R 17 #define TEGRA_GPIO_PORT_R 17
#define TEGRA_GPIO_BANK_ID_S 18 #define TEGRA_GPIO_PORT_S 18
#define TEGRA_GPIO_BANK_ID_T 19 #define TEGRA_GPIO_PORT_T 19
#define TEGRA_GPIO_BANK_ID_U 20 #define TEGRA_GPIO_PORT_U 20
#define TEGRA_GPIO_BANK_ID_V 21 #define TEGRA_GPIO_PORT_V 21
#define TEGRA_GPIO_BANK_ID_W 22 #define TEGRA_GPIO_PORT_W 22
#define TEGRA_GPIO_BANK_ID_X 23 #define TEGRA_GPIO_PORT_X 23
#define TEGRA_GPIO_BANK_ID_Y 24 #define TEGRA_GPIO_PORT_Y 24
#define TEGRA_GPIO_BANK_ID_Z 25 #define TEGRA_GPIO_PORT_Z 25
#define TEGRA_GPIO_BANK_ID_AA 26 #define TEGRA_GPIO_PORT_AA 26
#define TEGRA_GPIO_BANK_ID_BB 27 #define TEGRA_GPIO_PORT_BB 27
#define TEGRA_GPIO_BANK_ID_CC 28 #define TEGRA_GPIO_PORT_CC 28
#define TEGRA_GPIO_BANK_ID_DD 29 #define TEGRA_GPIO_PORT_DD 29
#define TEGRA_GPIO_BANK_ID_EE 30 #define TEGRA_GPIO_PORT_EE 30
#define TEGRA_GPIO_BANK_ID_FF 31 #define TEGRA_GPIO_PORT_FF 31
#define TEGRA_GPIO(bank, offset) \ #define TEGRA_GPIO(port, offset) \
((TEGRA_GPIO_BANK_ID_##bank * 8) + offset) ((TEGRA_GPIO_PORT_##port * 8) + offset)
#endif #endif