drm/dp: Add drm_dp_max_dprx_data_rate()
Copy intel_dp_max_data_rate() to DRM core. It will be needed by a follow-up DP tunnel patch, checking the maximum rate the DPRX (sink) supports. Accordingly use the drm_dp_max_dprx_data_rate() name for clarity. This patchset will also switch calling the new DRM function in i915 instead of intel_dp_max_data_rate(). While at it simplify the function documentation/comments, removing parts described already by drm_dp_bw_channel_coding_efficiency(). v2: (Ville) - Remove max_link_rate_kbps. - Simplify the function documentation. v3: - Rebased on latest drm-tip. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240226185246.1276018-1-imre.deak@intel.com
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@ -4059,3 +4059,33 @@ int drm_dp_bw_channel_coding_efficiency(bool is_uhbr)
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return 800000;
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}
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EXPORT_SYMBOL(drm_dp_bw_channel_coding_efficiency);
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/**
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* drm_dp_max_dprx_data_rate - Get the max data bandwidth of a DPRX sink
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* @max_link_rate: max DPRX link rate in 10kbps units
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* @max_lanes: max DPRX lane count
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*
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* Given a link rate and lanes, get the data bandwidth.
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*
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* Data bandwidth is the actual payload rate, which depends on the data
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* bandwidth efficiency and the link rate.
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*
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* Note that protocol layers above the DPRX link level considered here can
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* further limit the maximum data rate. Such layers are the MST topology (with
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* limits on the link between the source and first branch device as well as on
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* the whole MST path until the DPRX link) and (Thunderbolt) DP tunnels -
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* which in turn can encapsulate an MST link with its own limit - with each
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* SST or MST encapsulated tunnel sharing the BW of a tunnel group.
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*
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* Returns the maximum data rate in kBps units.
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*/
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int drm_dp_max_dprx_data_rate(int max_link_rate, int max_lanes)
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{
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int ch_coding_efficiency =
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drm_dp_bw_channel_coding_efficiency(drm_dp_is_uhbr_rate(max_link_rate));
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return DIV_ROUND_DOWN_ULL(mul_u32_u32(max_link_rate * 10 * max_lanes,
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ch_coding_efficiency),
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1000000 * 8);
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}
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EXPORT_SYMBOL(drm_dp_max_dprx_data_rate);
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@ -812,5 +812,6 @@ int drm_dp_bw_overhead(int lane_count, int hactive,
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int dsc_slice_count,
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int bpp_x16, unsigned long flags);
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int drm_dp_bw_channel_coding_efficiency(bool is_uhbr);
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int drm_dp_max_dprx_data_rate(int max_link_rate, int max_lanes);
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#endif /* _DRM_DP_HELPER_H_ */
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