Merge branch 'qed-fixes'
Yuval Mintz says: ==================== qed: Fixes series This address several different issues in qed. The more significant portions: Patch #1 would cause timeout when qedr utilizes the highest CIDs availble for it [or when future qede adapters would utilize queues in some constellations]. Patch #4 fixes a leak of mapped addresses; When iommu is enabled, offloaded storage protocols might eventually run out of resources and fail to map additional buffers. Patches #6,#7 were missing in the initial iSCSI infrastructure submissions, and would hamper qedi's stability when it reaches out-of-order scenarios. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
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1e6a1cd888
@ -422,8 +422,9 @@ static void qed_cxt_set_proto_cid_count(struct qed_hwfn *p_hwfn,
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u32 page_sz = p_mgr->clients[ILT_CLI_CDUC].p_size.val;
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u32 cxt_size = CONN_CXT_SIZE(p_hwfn);
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u32 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
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u32 align = elems_per_page * DQ_RANGE_ALIGN;
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p_conn->cid_count = roundup(p_conn->cid_count, elems_per_page);
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p_conn->cid_count = roundup(p_conn->cid_count, align);
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}
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}
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@ -2389,9 +2389,8 @@ qed_chain_alloc_sanity_check(struct qed_dev *cdev,
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* size/capacity fields are of a u32 type.
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*/
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if ((cnt_type == QED_CHAIN_CNT_TYPE_U16 &&
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chain_size > 0x10000) ||
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(cnt_type == QED_CHAIN_CNT_TYPE_U32 &&
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chain_size > 0x100000000ULL)) {
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chain_size > ((u32)U16_MAX + 1)) ||
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(cnt_type == QED_CHAIN_CNT_TYPE_U32 && chain_size > U32_MAX)) {
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DP_NOTICE(cdev,
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"The actual chain size (0x%llx) is larger than the maximal possible value\n",
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chain_size);
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@ -190,6 +190,9 @@ qed_sp_iscsi_func_start(struct qed_hwfn *p_hwfn,
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p_init->num_sq_pages_in_ring = p_params->num_sq_pages_in_ring;
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p_init->num_r2tq_pages_in_ring = p_params->num_r2tq_pages_in_ring;
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p_init->num_uhq_pages_in_ring = p_params->num_uhq_pages_in_ring;
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p_init->ooo_enable = p_params->ooo_enable;
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p_init->ll2_rx_queue_id = p_hwfn->hw_info.resc_start[QED_LL2_QUEUE] +
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p_params->ll2_ooo_queue_id;
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p_init->func_params.log_page_size = p_params->log_page_size;
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val = p_params->num_tasks;
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p_init->func_params.num_tasks = cpu_to_le16(val);
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@ -786,6 +789,23 @@ static void qed_iscsi_release_connection(struct qed_hwfn *p_hwfn,
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spin_unlock_bh(&p_hwfn->p_iscsi_info->lock);
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}
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void qed_iscsi_free_connection(struct qed_hwfn *p_hwfn,
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struct qed_iscsi_conn *p_conn)
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{
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qed_chain_free(p_hwfn->cdev, &p_conn->xhq);
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qed_chain_free(p_hwfn->cdev, &p_conn->uhq);
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qed_chain_free(p_hwfn->cdev, &p_conn->r2tq);
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dma_free_coherent(&p_hwfn->cdev->pdev->dev,
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sizeof(struct tcp_upload_params),
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p_conn->tcp_upload_params_virt_addr,
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p_conn->tcp_upload_params_phys_addr);
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dma_free_coherent(&p_hwfn->cdev->pdev->dev,
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sizeof(struct scsi_terminate_extra_params),
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p_conn->queue_cnts_virt_addr,
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p_conn->queue_cnts_phys_addr);
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kfree(p_conn);
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}
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struct qed_iscsi_info *qed_iscsi_alloc(struct qed_hwfn *p_hwfn)
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{
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struct qed_iscsi_info *p_iscsi_info;
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@ -807,6 +827,17 @@ void qed_iscsi_setup(struct qed_hwfn *p_hwfn,
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void qed_iscsi_free(struct qed_hwfn *p_hwfn,
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struct qed_iscsi_info *p_iscsi_info)
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{
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struct qed_iscsi_conn *p_conn = NULL;
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while (!list_empty(&p_hwfn->p_iscsi_info->free_list)) {
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p_conn = list_first_entry(&p_hwfn->p_iscsi_info->free_list,
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struct qed_iscsi_conn, list_entry);
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if (p_conn) {
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list_del(&p_conn->list_entry);
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qed_iscsi_free_connection(p_hwfn, p_conn);
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}
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}
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kfree(p_iscsi_info);
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}
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@ -211,6 +211,8 @@ static void qed_ll2b_complete_rx_packet(struct qed_hwfn *p_hwfn,
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/* If need to reuse or there's no replacement buffer, repost this */
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if (rc)
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goto out_post;
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dma_unmap_single(&cdev->pdev->dev, buffer->phys_addr,
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cdev->ll2->rx_size, DMA_FROM_DEVICE);
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skb = build_skb(buffer->data, 0);
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if (!skb) {
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@ -474,7 +476,7 @@ qed_ll2_rxq_completion_gsi(struct qed_hwfn *p_hwfn,
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static int qed_ll2_rxq_completion_reg(struct qed_hwfn *p_hwfn,
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struct qed_ll2_info *p_ll2_conn,
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union core_rx_cqe_union *p_cqe,
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unsigned long lock_flags,
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unsigned long *p_lock_flags,
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bool b_last_cqe)
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{
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struct qed_ll2_rx_queue *p_rx = &p_ll2_conn->rx_queue;
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@ -495,10 +497,10 @@ static int qed_ll2_rxq_completion_reg(struct qed_hwfn *p_hwfn,
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"Mismatch between active_descq and the LL2 Rx chain\n");
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list_add_tail(&p_pkt->list_entry, &p_rx->free_descq);
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spin_unlock_irqrestore(&p_rx->lock, lock_flags);
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spin_unlock_irqrestore(&p_rx->lock, *p_lock_flags);
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qed_ll2b_complete_rx_packet(p_hwfn, p_ll2_conn->my_id,
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p_pkt, &p_cqe->rx_cqe_fp, b_last_cqe);
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spin_lock_irqsave(&p_rx->lock, lock_flags);
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spin_lock_irqsave(&p_rx->lock, *p_lock_flags);
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return 0;
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}
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@ -538,7 +540,8 @@ static int qed_ll2_rxq_completion(struct qed_hwfn *p_hwfn, void *cookie)
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break;
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case CORE_RX_CQE_TYPE_REGULAR:
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rc = qed_ll2_rxq_completion_reg(p_hwfn, p_ll2_conn,
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cqe, flags, b_last_cqe);
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cqe, &flags,
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b_last_cqe);
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break;
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default:
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rc = -EIO;
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@ -159,6 +159,8 @@ struct qed_ooo_info *qed_ooo_alloc(struct qed_hwfn *p_hwfn)
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if (!p_ooo_info->ooo_history.p_cqes)
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goto no_history_mem;
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p_ooo_info->ooo_history.num_of_cqes = QED_MAX_NUM_OOO_HISTORY_ENTRIES;
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return p_ooo_info;
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no_history_mem:
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