drm/bridge: imx: Add i.MX8qm/qxp display pixel link support
This patch adds a drm bridge driver for i.MX8qm/qxp display pixel link. The pixel link forms a standard asynchronous linkage between pixel sources(display controller or camera module) and pixel consumers(imaging or displays). It consists of two distinct functions, a pixel transfer function and a control interface. Reviewed-by: Robert Foss <robert.foss@linaro.org> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> # Colibri iMX8X, LT170410-2WHC, LP156WF1 Signed-off-by: Liu Ying <victor.liu@nxp.com> Acked-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Robert Foss <robert.foss@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20220611141421.718743-7-victor.liu@nxp.com
This commit is contained in:
Liu Ying
Robert Foss
parent
2e7bee6816
commit
1ec17c26bc
@ -6,3 +6,12 @@ config DRM_IMX8QXP_PIXEL_COMBINER
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help
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Choose this to enable pixel combiner found in
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Freescale i.MX8qm/qxp processors.
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config DRM_IMX8QXP_PIXEL_LINK
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tristate "Freescale i.MX8QM/QXP display pixel link"
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depends on OF
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depends on IMX_SCU
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select DRM_KMS_HELPER
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help
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Choose this to enable display pixel link found in
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Freescale i.MX8qm/qxp processors.
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@ -1 +1,2 @@
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obj-$(CONFIG_DRM_IMX8QXP_PIXEL_COMBINER) += imx8qxp-pixel-combiner.o
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obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK) += imx8qxp-pixel-link.o
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429
drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c
Normal file
429
drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c
Normal file
@ -0,0 +1,429 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2020,2022 NXP
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*/
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#include <linux/firmware/imx/svc/misc.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_graph.h>
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#include <linux/platform_device.h>
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#include <drm/drm_atomic_state_helper.h>
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#include <drm/drm_bridge.h>
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#include <drm/drm_print.h>
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#include <dt-bindings/firmware/imx/rsrc.h>
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#define DRIVER_NAME "imx8qxp-display-pixel-link"
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#define PL_MAX_MST_ADDR 3
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#define PL_MAX_NEXT_BRIDGES 2
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struct imx8qxp_pixel_link {
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struct drm_bridge bridge;
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struct drm_bridge *next_bridge;
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struct device *dev;
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struct imx_sc_ipc *ipc_handle;
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u8 stream_id;
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u8 dc_id;
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u32 sink_rsc;
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u32 mst_addr;
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u8 mst_addr_ctrl;
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u8 mst_en_ctrl;
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u8 mst_vld_ctrl;
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u8 sync_ctrl;
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};
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static void imx8qxp_pixel_link_enable_mst_en(struct imx8qxp_pixel_link *pl)
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{
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int ret;
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ret = imx_sc_misc_set_control(pl->ipc_handle, pl->sink_rsc,
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pl->mst_en_ctrl, true);
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if (ret)
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DRM_DEV_ERROR(pl->dev,
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"failed to enable DC%u stream%u pixel link mst_en: %d\n",
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pl->dc_id, pl->stream_id, ret);
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}
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static void imx8qxp_pixel_link_enable_mst_vld(struct imx8qxp_pixel_link *pl)
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{
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int ret;
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ret = imx_sc_misc_set_control(pl->ipc_handle, pl->sink_rsc,
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pl->mst_vld_ctrl, true);
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if (ret)
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DRM_DEV_ERROR(pl->dev,
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"failed to enable DC%u stream%u pixel link mst_vld: %d\n",
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pl->dc_id, pl->stream_id, ret);
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}
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static void imx8qxp_pixel_link_enable_sync(struct imx8qxp_pixel_link *pl)
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{
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int ret;
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ret = imx_sc_misc_set_control(pl->ipc_handle, pl->sink_rsc,
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pl->sync_ctrl, true);
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if (ret)
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DRM_DEV_ERROR(pl->dev,
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"failed to enable DC%u stream%u pixel link sync: %d\n",
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pl->dc_id, pl->stream_id, ret);
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}
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static int imx8qxp_pixel_link_disable_mst_en(struct imx8qxp_pixel_link *pl)
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{
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int ret;
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ret = imx_sc_misc_set_control(pl->ipc_handle, pl->sink_rsc,
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pl->mst_en_ctrl, false);
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if (ret)
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DRM_DEV_ERROR(pl->dev,
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"failed to disable DC%u stream%u pixel link mst_en: %d\n",
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pl->dc_id, pl->stream_id, ret);
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return ret;
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}
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static int imx8qxp_pixel_link_disable_mst_vld(struct imx8qxp_pixel_link *pl)
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{
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int ret;
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ret = imx_sc_misc_set_control(pl->ipc_handle, pl->sink_rsc,
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pl->mst_vld_ctrl, false);
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if (ret)
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DRM_DEV_ERROR(pl->dev,
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"failed to disable DC%u stream%u pixel link mst_vld: %d\n",
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pl->dc_id, pl->stream_id, ret);
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return ret;
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}
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static int imx8qxp_pixel_link_disable_sync(struct imx8qxp_pixel_link *pl)
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{
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int ret;
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ret = imx_sc_misc_set_control(pl->ipc_handle, pl->sink_rsc,
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pl->sync_ctrl, false);
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if (ret)
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DRM_DEV_ERROR(pl->dev,
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"failed to disable DC%u stream%u pixel link sync: %d\n",
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pl->dc_id, pl->stream_id, ret);
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return ret;
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}
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static void imx8qxp_pixel_link_set_mst_addr(struct imx8qxp_pixel_link *pl)
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{
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int ret;
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ret = imx_sc_misc_set_control(pl->ipc_handle,
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pl->sink_rsc, pl->mst_addr_ctrl,
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pl->mst_addr);
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if (ret)
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DRM_DEV_ERROR(pl->dev,
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"failed to set DC%u stream%u pixel link mst addr(%u): %d\n",
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pl->dc_id, pl->stream_id, pl->mst_addr, ret);
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}
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static int imx8qxp_pixel_link_bridge_attach(struct drm_bridge *bridge,
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enum drm_bridge_attach_flags flags)
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{
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struct imx8qxp_pixel_link *pl = bridge->driver_private;
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if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) {
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DRM_DEV_ERROR(pl->dev,
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"do not support creating a drm_connector\n");
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return -EINVAL;
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}
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if (!bridge->encoder) {
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DRM_DEV_ERROR(pl->dev, "missing encoder\n");
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return -ENODEV;
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}
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return drm_bridge_attach(bridge->encoder,
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pl->next_bridge, bridge,
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DRM_BRIDGE_ATTACH_NO_CONNECTOR);
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}
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static void
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imx8qxp_pixel_link_bridge_mode_set(struct drm_bridge *bridge,
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const struct drm_display_mode *mode,
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const struct drm_display_mode *adjusted_mode)
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{
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struct imx8qxp_pixel_link *pl = bridge->driver_private;
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imx8qxp_pixel_link_set_mst_addr(pl);
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}
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static void
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imx8qxp_pixel_link_bridge_atomic_enable(struct drm_bridge *bridge,
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struct drm_bridge_state *old_bridge_state)
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{
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struct imx8qxp_pixel_link *pl = bridge->driver_private;
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imx8qxp_pixel_link_enable_mst_en(pl);
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imx8qxp_pixel_link_enable_mst_vld(pl);
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imx8qxp_pixel_link_enable_sync(pl);
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}
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static void
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imx8qxp_pixel_link_bridge_atomic_disable(struct drm_bridge *bridge,
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struct drm_bridge_state *old_bridge_state)
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{
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struct imx8qxp_pixel_link *pl = bridge->driver_private;
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imx8qxp_pixel_link_disable_mst_en(pl);
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imx8qxp_pixel_link_disable_mst_vld(pl);
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imx8qxp_pixel_link_disable_sync(pl);
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}
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static const u32 imx8qxp_pixel_link_bus_output_fmts[] = {
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MEDIA_BUS_FMT_RGB888_1X36_CPADLO,
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MEDIA_BUS_FMT_RGB666_1X36_CPADLO,
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};
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static bool imx8qxp_pixel_link_bus_output_fmt_supported(u32 fmt)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(imx8qxp_pixel_link_bus_output_fmts); i++) {
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if (imx8qxp_pixel_link_bus_output_fmts[i] == fmt)
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return true;
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}
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return false;
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}
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static u32 *
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imx8qxp_pixel_link_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
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struct drm_bridge_state *bridge_state,
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struct drm_crtc_state *crtc_state,
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struct drm_connector_state *conn_state,
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u32 output_fmt,
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unsigned int *num_input_fmts)
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{
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u32 *input_fmts;
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if (!imx8qxp_pixel_link_bus_output_fmt_supported(output_fmt))
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return NULL;
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*num_input_fmts = 1;
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input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL);
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if (!input_fmts)
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return NULL;
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input_fmts[0] = output_fmt;
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return input_fmts;
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}
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static u32 *
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imx8qxp_pixel_link_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
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struct drm_bridge_state *bridge_state,
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struct drm_crtc_state *crtc_state,
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struct drm_connector_state *conn_state,
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unsigned int *num_output_fmts)
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{
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*num_output_fmts = ARRAY_SIZE(imx8qxp_pixel_link_bus_output_fmts);
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return kmemdup(imx8qxp_pixel_link_bus_output_fmts,
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sizeof(imx8qxp_pixel_link_bus_output_fmts), GFP_KERNEL);
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}
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static const struct drm_bridge_funcs imx8qxp_pixel_link_bridge_funcs = {
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.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
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.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
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.atomic_reset = drm_atomic_helper_bridge_reset,
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.attach = imx8qxp_pixel_link_bridge_attach,
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.mode_set = imx8qxp_pixel_link_bridge_mode_set,
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.atomic_enable = imx8qxp_pixel_link_bridge_atomic_enable,
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.atomic_disable = imx8qxp_pixel_link_bridge_atomic_disable,
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.atomic_get_input_bus_fmts =
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imx8qxp_pixel_link_bridge_atomic_get_input_bus_fmts,
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.atomic_get_output_bus_fmts =
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imx8qxp_pixel_link_bridge_atomic_get_output_bus_fmts,
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};
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static int imx8qxp_pixel_link_disable_all_controls(struct imx8qxp_pixel_link *pl)
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{
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int ret;
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ret = imx8qxp_pixel_link_disable_mst_en(pl);
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if (ret)
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return ret;
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ret = imx8qxp_pixel_link_disable_mst_vld(pl);
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if (ret)
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return ret;
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return imx8qxp_pixel_link_disable_sync(pl);
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}
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static struct drm_bridge *
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imx8qxp_pixel_link_find_next_bridge(struct imx8qxp_pixel_link *pl)
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{
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struct device_node *np = pl->dev->of_node;
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struct device_node *port, *remote;
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struct drm_bridge *next_bridge[PL_MAX_NEXT_BRIDGES];
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u32 port_id;
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bool found_port = false;
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int reg, ep_cnt = 0;
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/* select the first next bridge by default */
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int bridge_sel = 0;
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for (port_id = 1; port_id <= PL_MAX_MST_ADDR + 1; port_id++) {
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port = of_graph_get_port_by_id(np, port_id);
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if (!port)
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continue;
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if (of_device_is_available(port)) {
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found_port = true;
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of_node_put(port);
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break;
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}
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of_node_put(port);
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}
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if (!found_port) {
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DRM_DEV_ERROR(pl->dev, "no available output port\n");
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return ERR_PTR(-ENODEV);
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}
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for (reg = 0; reg < PL_MAX_NEXT_BRIDGES; reg++) {
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remote = of_graph_get_remote_node(np, port_id, reg);
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if (!remote)
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continue;
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if (!of_device_is_available(remote->parent)) {
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DRM_DEV_DEBUG(pl->dev,
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"port%u endpoint%u remote parent is not available\n",
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port_id, reg);
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of_node_put(remote);
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continue;
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}
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next_bridge[ep_cnt] = of_drm_find_bridge(remote);
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if (!next_bridge[ep_cnt]) {
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of_node_put(remote);
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return ERR_PTR(-EPROBE_DEFER);
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}
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/* specially select the next bridge with companion PXL2DPI */
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if (of_find_property(remote, "fsl,companion-pxl2dpi", NULL))
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bridge_sel = ep_cnt;
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ep_cnt++;
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of_node_put(remote);
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}
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pl->mst_addr = port_id - 1;
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return next_bridge[bridge_sel];
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}
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static int imx8qxp_pixel_link_bridge_probe(struct platform_device *pdev)
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{
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struct imx8qxp_pixel_link *pl;
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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int ret;
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pl = devm_kzalloc(dev, sizeof(*pl), GFP_KERNEL);
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if (!pl)
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return -ENOMEM;
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ret = imx_scu_get_handle(&pl->ipc_handle);
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if (ret) {
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if (ret != -EPROBE_DEFER)
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DRM_DEV_ERROR(dev, "failed to get SCU ipc handle: %d\n",
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ret);
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return ret;
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}
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ret = of_property_read_u8(np, "fsl,dc-id", &pl->dc_id);
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if (ret) {
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DRM_DEV_ERROR(dev, "failed to get DC index: %d\n", ret);
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return ret;
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}
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ret = of_property_read_u8(np, "fsl,dc-stream-id", &pl->stream_id);
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if (ret) {
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DRM_DEV_ERROR(dev, "failed to get DC stream index: %d\n", ret);
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return ret;
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}
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pl->dev = dev;
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pl->sink_rsc = pl->dc_id ? IMX_SC_R_DC_1 : IMX_SC_R_DC_0;
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if (pl->stream_id == 0) {
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pl->mst_addr_ctrl = IMX_SC_C_PXL_LINK_MST1_ADDR;
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pl->mst_en_ctrl = IMX_SC_C_PXL_LINK_MST1_ENB;
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pl->mst_vld_ctrl = IMX_SC_C_PXL_LINK_MST1_VLD;
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pl->sync_ctrl = IMX_SC_C_SYNC_CTRL0;
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} else {
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pl->mst_addr_ctrl = IMX_SC_C_PXL_LINK_MST2_ADDR;
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pl->mst_en_ctrl = IMX_SC_C_PXL_LINK_MST2_ENB;
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pl->mst_vld_ctrl = IMX_SC_C_PXL_LINK_MST2_VLD;
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pl->sync_ctrl = IMX_SC_C_SYNC_CTRL1;
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}
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/* disable all controls to POR default */
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ret = imx8qxp_pixel_link_disable_all_controls(pl);
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if (ret)
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return ret;
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pl->next_bridge = imx8qxp_pixel_link_find_next_bridge(pl);
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if (IS_ERR(pl->next_bridge)) {
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ret = PTR_ERR(pl->next_bridge);
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if (ret != -EPROBE_DEFER)
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DRM_DEV_ERROR(dev, "failed to find next bridge: %d\n",
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ret);
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return ret;
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}
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platform_set_drvdata(pdev, pl);
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pl->bridge.driver_private = pl;
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pl->bridge.funcs = &imx8qxp_pixel_link_bridge_funcs;
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pl->bridge.of_node = np;
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drm_bridge_add(&pl->bridge);
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return ret;
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}
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static int imx8qxp_pixel_link_bridge_remove(struct platform_device *pdev)
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{
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struct imx8qxp_pixel_link *pl = platform_get_drvdata(pdev);
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drm_bridge_remove(&pl->bridge);
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return 0;
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}
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static const struct of_device_id imx8qxp_pixel_link_dt_ids[] = {
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{ .compatible = "fsl,imx8qm-dc-pixel-link", },
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{ .compatible = "fsl,imx8qxp-dc-pixel-link", },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, imx8qxp_pixel_link_dt_ids);
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||||
|
||||
static struct platform_driver imx8qxp_pixel_link_bridge_driver = {
|
||||
.probe = imx8qxp_pixel_link_bridge_probe,
|
||||
.remove = imx8qxp_pixel_link_bridge_remove,
|
||||
.driver = {
|
||||
.of_match_table = imx8qxp_pixel_link_dt_ids,
|
||||
.name = DRIVER_NAME,
|
||||
},
|
||||
};
|
||||
module_platform_driver(imx8qxp_pixel_link_bridge_driver);
|
||||
|
||||
MODULE_DESCRIPTION("i.MX8QXP/QM display pixel link bridge driver");
|
||||
MODULE_AUTHOR("Liu Ying <victor.liu@nxp.com>");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_ALIAS("platform:" DRIVER_NAME);
|
||||
Loading…
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Reference in New Issue
Block a user