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TTY/Serial changes for 6.7-rc1

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Here is the big set of tty/serial driver changes for 6.7-rc1.  Included
 in here are:
   - console/vgacon cleanups and removals from Arnd
   - tty core and n_tty cleanups from Jiri
   - lots of 8250 driver updates and cleanups
   - sc16is7xx serial driver updates
   - dt binding updates
   - first set of port lock wrapers from Thomas for the printk fixes
     coming in future releases
   - other small serial and tty core cleanups and updates
 
 All of these have been in linux-next for a while with no reported
 issues.
 
 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Merge tag 'tty-6.7-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty

Pull tty and serial updates from Greg KH:
 "Here is the big set of tty/serial driver changes for 6.7-rc1. Included
  in here are:

   - console/vgacon cleanups and removals from Arnd

   - tty core and n_tty cleanups from Jiri

   - lots of 8250 driver updates and cleanups

   - sc16is7xx serial driver updates

   - dt binding updates

   - first set of port lock wrapers from Thomas for the printk fixes
     coming in future releases

   - other small serial and tty core cleanups and updates

  All of these have been in linux-next for a while with no reported
  issues"

* tag 'tty-6.7-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty: (193 commits)
  serdev: Replace custom code with device_match_acpi_handle()
  serdev: Simplify devm_serdev_device_open() function
  serdev: Make use of device_set_node()
  tty: n_gsm: add copyright Siemens Mobility GmbH
  tty: n_gsm: fix race condition in status line change on dead connections
  serial: core: Fix runtime PM handling for pending tx
  vgacon: fix mips/sibyte build regression
  dt-bindings: serial: drop unsupported samsung bindings
  tty: serial: samsung: drop earlycon support for unsupported platforms
  tty: 8250: Add note for PX-835
  tty: 8250: Fix IS-200 PCI ID comment
  tty: 8250: Add Brainboxes Oxford Semiconductor-based quirks
  tty: 8250: Add support for Intashield IX cards
  tty: 8250: Add support for additional Brainboxes PX cards
  tty: 8250: Fix up PX-803/PX-857
  tty: 8250: Fix port count of PX-257
  tty: 8250: Add support for Intashield IS-100
  tty: 8250: Add support for Brainboxes UP cards
  tty: 8250: Add support for additional Brainboxes UC cards
  tty: 8250: Remove UC-257 and UC-431
  ...
This commit is contained in:
Linus Torvalds 2023-11-03 15:44:25 -10:00
commit 1f24458a10
172 changed files with 4058 additions and 2329 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
Documentation/ABI/testing/sysfs-tty
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@ -87,19 +87,22 @@ What: /sys/class/tty/ttyS<x>/close_delay
Date: October 2012
Contact: Alan Cox <alan@linux.intel.com>
Description:
Show the closing delay time for this port in ms.
Show the closing delay time for this port in centiseconds.
These sysfs values expose the TIOCGSERIAL interface via
sysfs rather than via ioctls.
These sysfs values expose the TIOCGSERIAL interface via
sysfs rather than via ioctls.
What: /sys/class/tty/ttyS<x>/closing_wait
Date: October 2012
Contact: Alan Cox <alan@linux.intel.com>
Description:
Show the close wait time for this port in ms.
Show the close wait time for this port in centiseconds.
These sysfs values expose the TIOCGSERIAL interface via
sysfs rather than via ioctls.
Waiting forever is represented as 0. If waiting on close is
disabled then the value is 65535.
These sysfs values expose the TIOCGSERIAL interface via
sysfs rather than via ioctls.
What: /sys/class/tty/ttyS<x>/custom_divisor
Date: October 2012

42
Documentation/devicetree/bindings/serial/esp,esp32-acm.yaml Normal file
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@ -0,0 +1,42 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/serial/esp,esp32-acm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ESP32S3 ACM gadget controller
maintainers:
- Max Filippov <jcmvbkbc@gmail.com>
description:
Fixed function USB CDC-ACM gadget controller of the Espressif ESP32S3 SoC.
allOf:
- $ref: serial.yaml#
properties:
compatible:
const: esp,esp32s3-acm
reg:
maxItems: 1
interrupts:
maxItems: 1
required:
- compatible
- reg
- interrupts
additionalProperties: false
examples:
- |
serial@60038000 {
compatible = "esp,esp32s3-acm";
reg = <0x60038000 0x1000>;
interrupts = <96 3 0>;
};

51
Documentation/devicetree/bindings/serial/esp,esp32-uart.yaml Normal file
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@ -0,0 +1,51 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/serial/esp,esp32-uart.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ESP32xx UART controllers
maintainers:
- Max Filippov <jcmvbkbc@gmail.com>
description:
ESP32 UART controller is a part of the ESP32 SoC.
ESP32S3 UART controller is a part of the ESP32S3 SoC.
Both SoCs are produced by Espressif Systems Co. Ltd.
allOf:
- $ref: serial.yaml#
properties:
compatible:
enum:
- esp,esp32-uart
- esp,esp32s3-uart
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
required:
- compatible
- reg
- interrupts
- clocks
additionalProperties: false
examples:
- |
serial@60000000 {
compatible = "esp,esp32s3-uart";
reg = <0x60000000 0x80>;
interrupts = <27 1 0>;
clocks = <&serial_clk>;
};

2
Documentation/devicetree/bindings/serial/fsl-imx-uart.yaml
View File

@ -70,6 +70,8 @@ properties:
interrupts:
maxItems: 1
wakeup-source: true
fsl,dte-mode:
$ref: /schemas/types.yaml#/definitions/flag
description: |

13
Documentation/devicetree/bindings/serial/fsl-mxs-auart.yaml
View File

@ -14,10 +14,13 @@ allOf:
properties:
compatible:
enum:
- fsl,imx23-auart
- fsl,imx28-auart
- alphascale,asm9260-auart
oneOf:
- const: fsl,imx23-auart
- const: alphascale,asm9260-auart
- items:
- enum:
- fsl,imx28-auart
- const: fsl,imx23-auart
reg:
maxItems: 1
@ -82,7 +85,7 @@ examples:
};
auart0: serial@8006a000 {
compatible = "fsl,imx28-auart";
compatible = "fsl,imx28-auart", "fsl,imx23-auart";
reg = <0x8006a000 0x2000>;
interrupts = <112>;
dmas = <&dma_apbx 8>, <&dma_apbx 9>;

48
Documentation/devicetree/bindings/serial/maxim,max310x.txt
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@ -1,48 +0,0 @@
* Maxim MAX310X advanced Universal Asynchronous Receiver-Transmitter (UART)
Required properties:
- compatible: Should be one of the following:
- "maxim,max3107" for Maxim MAX3107,
- "maxim,max3108" for Maxim MAX3108,
- "maxim,max3109" for Maxim MAX3109,
- "maxim,max14830" for Maxim MAX14830.
- reg: SPI chip select number.
- interrupts: Specifies the interrupt source of the parent interrupt
controller. The format of the interrupt specifier depends on the
parent interrupt controller.
- clocks: phandle to the IC source clock.
- clock-names: Should be "xtal" if clock is an external crystal or
"osc" if an external clock source is used.
Optional properties:
- gpio-controller: Marks the device node as a GPIO controller.
- #gpio-cells: Should be two. The first cell is the GPIO number and
the second cell is used to specify the GPIO polarity:
0 = active high,
1 = active low.
Example:
/ {
clocks {
spi_uart_clk: osc_max14830 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <3686400>;
};
};
};
&spi0 {
max14830: max14830@0 {
compatible = "maxim,max14830";
reg = <0>;
clocks = <&spi_uart_clk>;
clock-names = "osc";
interrupt-parent = <&gpio3>;
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
gpio-controller;
#gpio-cells = <2>;
};
};

74
Documentation/devicetree/bindings/serial/maxim,max310x.yaml Normal file
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@ -0,0 +1,74 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/serial/maxim,max310x.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Maxim MAX310X Advanced Universal Asynchronous Receiver-Transmitter (UART)
maintainers:
- Hugo Villeneuve <hvilleneuve@dimonoff.com>
properties:
compatible:
enum:
- maxim,max3107
- maxim,max3108
- maxim,max3109
- maxim,max14830
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
clock-names:
enum:
- xtal # External crystal
- osc # External clock source
gpio-controller: true
"#gpio-cells":
const: 2
gpio-line-names:
minItems: 1
maxItems: 16
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
allOf:
- $ref: /schemas/spi/spi-peripheral-props.yaml#
- $ref: /schemas/serial/serial.yaml#
- $ref: /schemas/serial/rs485.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
serial@2c {
compatible = "maxim,max3107";
reg = <0x2c>;
clocks = <&xtal4m>;
clock-names = "xtal";
interrupt-parent = <&gpio3>;
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
gpio-controller;
#gpio-cells = <2>;
};
};

10
Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.yaml
View File

@ -91,11 +91,6 @@ properties:
- description: range upper bound
- description: adjustment (in permyriad, i.e. 0.01%)
allOf:
- $ref: serial.yaml
unevaluatedProperties: false
required:
- compatible
- reg
@ -106,6 +101,11 @@ required:
- dmas
- dma-names
allOf:
- $ref: serial.yaml
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/tegra30-car.h>

118
Documentation/devicetree/bindings/serial/nxp,sc16is7xx.txt
View File

@ -1,118 +0,0 @@
* NXP SC16IS7xx advanced Universal Asynchronous Receiver-Transmitter (UART)
* i2c as bus
Required properties:
- compatible: Should be one of the following:
- "nxp,sc16is740" for NXP SC16IS740,
- "nxp,sc16is741" for NXP SC16IS741,
- "nxp,sc16is750" for NXP SC16IS750,
- "nxp,sc16is752" for NXP SC16IS752,
- "nxp,sc16is760" for NXP SC16IS760,
- "nxp,sc16is762" for NXP SC16IS762.
- reg: I2C address of the SC16IS7xx device.
- interrupts: Should contain the UART interrupt
- clocks: Reference to the IC source clock.
OR (when there is no clock provider visible to the platform)
- clock-frequency: The source clock frequency for the IC.
Optional properties:
- gpio-controller: Marks the device node as a GPIO controller.
- #gpio-cells: Should be two. The first cell is the GPIO number and
the second cell is used to specify the GPIO polarity:
0 = active high,
1 = active low.
- irda-mode-ports: An array that lists the indices of the port that
should operate in IrDA mode.
- nxp,modem-control-line-ports: An array that lists the indices of the port that
should have shared GPIO lines configured as
modem control lines.
Example:
sc16is750: sc16is750@51 {
compatible = "nxp,sc16is750";
reg = <0x51>;
clocks = <&clk20m>;
interrupt-parent = <&gpio3>;
interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
gpio-controller;
#gpio-cells = <2>;
};
sc16is752: sc16is752@53 {
compatible = "nxp,sc16is752";
reg = <0x53>;
clocks = <&clk20m>;
interrupt-parent = <&gpio3>;
interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
nxp,modem-control-line-ports = <1>; /* Port 1 as modem control lines */
gpio-controller; /* Port 0 as GPIOs */
#gpio-cells = <2>;
};
sc16is752: sc16is752@54 {
compatible = "nxp,sc16is752";
reg = <0x54>;
clocks = <&clk20m>;
interrupt-parent = <&gpio3>;
interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
nxp,modem-control-line-ports = <0 1>; /* Ports 0 and 1 as modem control lines */
};
* spi as bus
Required properties:
- compatible: Should be one of the following:
- "nxp,sc16is740" for NXP SC16IS740,
- "nxp,sc16is741" for NXP SC16IS741,
- "nxp,sc16is750" for NXP SC16IS750,
- "nxp,sc16is752" for NXP SC16IS752,
- "nxp,sc16is760" for NXP SC16IS760,
- "nxp,sc16is762" for NXP SC16IS762.
- reg: SPI chip select number.
- interrupts: Specifies the interrupt source of the parent interrupt
controller. The format of the interrupt specifier depends on the
parent interrupt controller.
- clocks: phandle to the IC source clock.
Optional properties:
- gpio-controller: Marks the device node as a GPIO controller.
- #gpio-cells: Should be two. The first cell is the GPIO number and
the second cell is used to specify the GPIO polarity:
0 = active high,
1 = active low.
- irda-mode-ports: An array that lists the indices of the port that
should operate in IrDA mode.
- nxp,modem-control-line-ports: An array that lists the indices of the port that
should have shared GPIO lines configured as
modem control lines.
Example:
sc16is750: sc16is750@0 {
compatible = "nxp,sc16is750";
reg = <0>;
clocks = <&clk20m>;
interrupt-parent = <&gpio3>;
interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
gpio-controller;
#gpio-cells = <2>;
};
sc16is752: sc16is752@1 {
compatible = "nxp,sc16is752";
reg = <1>;
clocks = <&clk20m>;
interrupt-parent = <&gpio3>;
interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
nxp,modem-control-line-ports = <1>; /* Port 1 as modem control lines */
gpio-controller; /* Port 0 as GPIOs */
#gpio-cells = <2>;
};
sc16is752: sc16is752@2 {
compatible = "nxp,sc16is752";
reg = <2>;
clocks = <&clk20m>;
interrupt-parent = <&gpio3>;
interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
nxp,modem-control-line-ports = <0 1>; /* Ports 0 and 1 as modem control lines */
};

127
Documentation/devicetree/bindings/serial/nxp,sc16is7xx.yaml Normal file
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@ -0,0 +1,127 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/serial/nxp,sc16is7xx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP SC16IS7xx Advanced Universal Asynchronous Receiver-Transmitter (UART)
maintainers:
- Hugo Villeneuve <hvilleneuve@dimonoff.com>
properties:
compatible:
enum:
- nxp,sc16is740
- nxp,sc16is741
- nxp,sc16is750
- nxp,sc16is752
- nxp,sc16is760
- nxp,sc16is762
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
clock-frequency:
description:
When there is no clock provider visible to the platform, this
is the source crystal or external clock frequency for the IC in Hz.
minimum: 1
maximum: 80000000
gpio-controller: true
"#gpio-cells":
const: 2
gpio-line-names:
minItems: 1
maxItems: 8
irda-mode-ports:
description: |
An array that lists the indices of the port that should operate in IrDA
mode:
0: port A
1: port B
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 1
maxItems: 2
items:
minimum: 0
maximum: 1
nxp,modem-control-line-ports:
description: |
An array that lists the indices of the port that should have shared GPIO
lines configured as modem control lines:
0: port A
1: port B
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 1
maxItems: 2
items:
minimum: 0
maximum: 1
required:
- compatible
- reg
- interrupts
allOf:
- $ref: /schemas/spi/spi-peripheral-props.yaml#
- $ref: /schemas/serial/serial.yaml#
- $ref: /schemas/serial/rs485.yaml#
oneOf:
- required:
- clocks
- required:
- clock-frequency
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
serial@51 {
compatible = "nxp,sc16is750";
reg = <0x51>;
clocks = <&clk20m>;
interrupt-parent = <&gpio3>;
interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
gpio-controller;
#gpio-cells = <2>;
};
serial@53 {
compatible = "nxp,sc16is752";
reg = <0x53>;
clocks = <&clk20m>;
interrupt-parent = <&gpio3>;
interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
nxp,modem-control-line-ports = <1>; /* Port 1 as modem control lines */
gpio-controller; /* Port 0 as GPIOs */
#gpio-cells = <2>;
};
serial@54 {
compatible = "nxp,sc16is752";
reg = <0x54>;
clocks = <&clk20m>;
interrupt-parent = <&gpio3>;
interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
nxp,modem-control-line-ports = <0 1>; /* Ports 0 and 1 as modem control lines */
};
};

4
Documentation/devicetree/bindings/serial/qcom,msm-uart.yaml
View File

@ -40,11 +40,11 @@ required:
- interrupts
- reg
unevaluatedProperties: false
allOf:
- $ref: /schemas/serial/serial.yaml#
unevaluatedProperties: false
examples:
- |
serial@a9c00000 {

4
Documentation/devicetree/bindings/serial/qcom,msm-uartdm.yaml
View File

@ -78,8 +78,6 @@ required:
- interrupts
- reg
unevaluatedProperties: false
allOf:
- $ref: /schemas/serial/serial.yaml#
@ -97,6 +95,8 @@ allOf:
reg:
maxItems: 1
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>

14
Documentation/devicetree/bindings/serial/renesas,em-uart.yaml
View File

@ -38,6 +38,13 @@ properties:
- const: sclk
- const: pclk
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
allOf:
- $ref: serial.yaml#
@ -53,13 +60,6 @@ allOf:
clock-names:
minItems: 2
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
unevaluatedProperties: false
examples:

4
Documentation/devicetree/bindings/serial/renesas,hscif.yaml
View File

@ -111,8 +111,6 @@ required:
- clock-names
- power-domains
unevaluatedProperties: false
if:
properties:
compatible:
@ -125,6 +123,8 @@ then:
required:
- resets
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/r8a7795-cpg-mssr.h>

1
Documentation/devicetree/bindings/serial/renesas,scif.yaml
View File

@ -79,6 +79,7 @@ properties:
- enum:
- renesas,scif-r9a07g043 # RZ/G2UL and RZ/Five
- renesas,scif-r9a07g054 # RZ/V2L
- renesas,scif-r9a08g045 # RZ/G3S
- const: renesas,scif-r9a07g044 # RZ/G2{L,LC} fallback
reg:

4
Documentation/devicetree/bindings/serial/renesas,scifa.yaml
View File

@ -77,8 +77,6 @@ required:
- clock-names
- power-domains
unevaluatedProperties: false
if:
properties:
compatible:
@ -89,6 +87,8 @@ then:
required:
- resets
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/r8a7790-cpg-mssr.h>

4
Documentation/devicetree/bindings/serial/renesas,scifb.yaml
View File

@ -77,8 +77,6 @@ required:
- clock-names
- power-domains
unevaluatedProperties: false
if:
properties:
compatible:
@ -89,6 +87,8 @@ then:
required:
- resets
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/r8a7740-clock.h>

4
Documentation/devicetree/bindings/serial/rs485.yaml
View File

@ -29,6 +29,10 @@ properties:
default: 0
maximum: 100
rs485-rts-active-high:
description: drive RTS high when sending (this is the default).
$ref: /schemas/types.yaml#/definitions/flag
rs485-rts-active-low:
description: drive RTS low when sending (default is high).
$ref: /schemas/types.yaml#/definitions/flag

8
Documentation/devicetree/bindings/serial/samsung_uart.yaml
View File

@ -24,9 +24,6 @@ properties:
- enum:
- apple,s5l-uart
- axis,artpec8-uart
- samsung,s3c2410-uart
- samsung,s3c2412-uart
- samsung,s3c2440-uart
- samsung,s3c6400-uart
- samsung,s5pv210-uart
- samsung,exynos4210-uart
@ -86,8 +83,6 @@ required:
- interrupts
- reg
unevaluatedProperties: false
allOf:
- $ref: serial.yaml#
@ -96,7 +91,6 @@ allOf:
compatible:
contains:
enum:
- samsung,s3c2410-uart
- samsung,s5pv210-uart
then:
properties:
@ -128,6 +122,8 @@ allOf:
- const: uart
- const: clk_uart_baud0
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/samsung,s3c64xx-clock.h>

18
Documentation/devicetree/bindings/serial/serial.yaml
View File

@ -87,16 +87,8 @@ properties:
description:
TX FIFO threshold configuration (in bytes).
if:
required:
- uart-has-rtscts
then:
properties:
cts-gpios: false
rts-gpios: false
patternProperties:
"^bluetooth|gnss|gps|mcu$":
"^(bluetooth|bluetooth-gnss|gnss|gps|mcu)$":
if:
type: object
then:
@ -136,6 +128,14 @@ patternProperties:
required:
- compatible
if:
required:
- uart-has-rtscts
then:
properties:
cts-gpios: false
rts-gpios: false
additionalProperties: true
examples:

1
Documentation/driver-api/tty/index.rst
View File

@ -36,6 +36,7 @@ In-detail description of the named TTY structures is in separate documents:
tty_struct
tty_ldisc
tty_buffer
tty_ioctl
tty_internals
Writing TTY Driver

10
Documentation/driver-api/tty/tty_ioctl.rst Normal file
View File

@ -0,0 +1,10 @@
.. SPDX-License-Identifier: GPL-2.0
=================
TTY IOCTL Helpers
=================
.. kernel-doc:: drivers/tty/tty_ioctl.c
.. kernel-doc:: include/linux/tty.h
:identifiers: tty_get_baud_rate

2
arch/alpha/kernel/proto.h
View File

@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
#include <linux/interrupt.h>
#include <linux/screen_info.h>
#include <linux/io.h>
/* Prototypes of functions used across modules here in this directory. */
@ -113,6 +114,7 @@ extern int boot_cpuid;
#ifdef CONFIG_VERBOSE_MCHECK
extern unsigned long alpha_verbose_mcheck;
#endif
extern struct screen_info vgacon_screen_info;
/* srmcons.c */
#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_SRM)

8
arch/alpha/kernel/setup.c
View File

@ -131,13 +131,14 @@ static void determine_cpu_caches (unsigned int);
static char __initdata command_line[COMMAND_LINE_SIZE];
#ifdef CONFIG_VGA_CONSOLE
/*
* The format of "screen_info" is strange, and due to early
* i386-setup code. This is just enough to make the console
* code think we're on a VGA color display.
*/
struct screen_info screen_info = {
struct screen_info vgacon_screen_info = {
.orig_x = 0,
.orig_y = 25,
.orig_video_cols = 80,
@ -145,8 +146,7 @@ struct screen_info screen_info = {
.orig_video_isVGA = 1,
.orig_video_points = 16
};
EXPORT_SYMBOL(screen_info);
#endif
/*
* The direct map I/O window, if any. This should be the same
@ -652,7 +652,7 @@ setup_arch(char **cmdline_p)
#ifdef CONFIG_VT
#if defined(CONFIG_VGA_CONSOLE)
conswitchp = &vga_con;
vgacon_register_screen(&vgacon_screen_info);
#endif
#endif

8
arch/alpha/kernel/sys_sio.c
View File

@ -57,11 +57,13 @@ sio_init_irq(void)
static inline void __init
alphabook1_init_arch(void)
{
#ifdef CONFIG_VGA_CONSOLE
/* The AlphaBook1 has LCD video fixed at 800x600,
37 rows and 100 cols. */
screen_info.orig_y = 37;
screen_info.orig_video_cols = 100;
screen_info.orig_video_lines = 37;
vgacon_screen_info.orig_y = 37;
vgacon_screen_info.orig_video_cols = 100;
vgacon_screen_info.orig_video_lines = 37;
#endif
lca_init_arch();
}

5
arch/arm/include/asm/setup.h
View File

@ -11,6 +11,7 @@
#ifndef __ASMARM_SETUP_H
#define __ASMARM_SETUP_H
#include <linux/screen_info.h>
#include <uapi/asm/setup.h>
@ -35,4 +36,8 @@ void early_mm_init(const struct machine_desc *);
void adjust_lowmem_bounds(void);
void setup_dma_zone(const struct machine_desc *desc);
#ifdef CONFIG_VGA_CONSOLE
extern struct screen_info vgacon_screen_info;
#endif
#endif

1
arch/arm/include/asm/vga.h
View File

@ -5,6 +5,7 @@
#include <linux/io.h>
extern unsigned long vga_base;
extern struct screen_info vgacon_screen_info;
#define VGA_MAP_MEM(x,s) (vga_base + (x))

20
arch/arm/kernel/atags_parse.c
View File

@ -69,18 +69,18 @@ static int __init parse_tag_mem32(const struct tag *tag)
__tagtable(ATAG_MEM, parse_tag_mem32);
#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
#if defined(CONFIG_ARCH_FOOTBRIDGE) && defined(CONFIG_VGA_CONSOLE)
static int __init parse_tag_videotext(const struct tag *tag)
{
screen_info.orig_x = tag->u.videotext.x;
screen_info.orig_y = tag->u.videotext.y;
screen_info.orig_video_page = tag->u.videotext.video_page;
screen_info.orig_video_mode = tag->u.videotext.video_mode;
screen_info.orig_video_cols = tag->u.videotext.video_cols;
screen_info.orig_video_ega_bx = tag->u.videotext.video_ega_bx;
screen_info.orig_video_lines = tag->u.videotext.video_lines;
screen_info.orig_video_isVGA = tag->u.videotext.video_isvga;
screen_info.orig_video_points = tag->u.videotext.video_points;
vgacon_screen_info.orig_x = tag->u.videotext.x;
vgacon_screen_info.orig_y = tag->u.videotext.y;
vgacon_screen_info.orig_video_page = tag->u.videotext.video_page;
vgacon_screen_info.orig_video_mode = tag->u.videotext.video_mode;
vgacon_screen_info.orig_video_cols = tag->u.videotext.video_cols;
vgacon_screen_info.orig_video_ega_bx = tag->u.videotext.video_ega_bx;
vgacon_screen_info.orig_video_lines = tag->u.videotext.video_lines;
vgacon_screen_info.orig_video_isVGA = tag->u.videotext.video_isvga;
vgacon_screen_info.orig_video_points = tag->u.videotext.video_points;
return 0;
}

6
arch/arm/kernel/efi.c
View File

@ -123,12 +123,6 @@ void __init arm_efi_init(void)
{
efi_init();
if (screen_info.orig_video_isVGA == VIDEO_TYPE_EFI) {
/* dummycon on ARM needs non-zero values for columns/lines */
screen_info.orig_video_cols = 80;
screen_info.orig_video_lines = 25;
}
/* ARM does not permit early mappings to persist across paging_init() */
efi_memmap_unmap();

7
arch/arm/kernel/setup.c
View File

@ -928,9 +928,8 @@ static void __init request_standard_resources(const struct machine_desc *mdesc)
request_resource(&ioport_resource, &lp2);
}
#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE) || \
defined(CONFIG_EFI)
struct screen_info screen_info = {
#if defined(CONFIG_VGA_CONSOLE)
struct screen_info vgacon_screen_info = {
.orig_video_lines = 30,
.orig_video_cols = 80,
.orig_video_mode = 0,
@ -1194,7 +1193,7 @@ void __init setup_arch(char **cmdline_p)
#ifdef CONFIG_VT
#if defined(CONFIG_VGA_CONSOLE)
conswitchp = &vga_con;
vgacon_register_screen(&vgacon_screen_info);
#endif
#endif

4
arch/arm64/kernel/efi.c
View File

@ -71,10 +71,6 @@ static __init pteval_t create_mapping_protection(efi_memory_desc_t *md)
return pgprot_val(PAGE_KERNEL_EXEC);
}
/* we will fill this structure from the stub, so don't put it in .bss */
struct screen_info screen_info __section(".data");
EXPORT_SYMBOL(screen_info);
int __init efi_create_mapping(struct mm_struct *mm, efi_memory_desc_t *md)
{
pteval_t prot_val = create_mapping_protection(md);

2
arch/arm64/kernel/image-vars.h
View File

@ -27,7 +27,9 @@ PROVIDE(__efistub__text = _text);
PROVIDE(__efistub__end = _end);
PROVIDE(__efistub___inittext_end = __inittext_end);
PROVIDE(__efistub__edata = _edata);
#if defined(CONFIG_EFI_EARLYCON) || defined(CONFIG_SYSFB)
PROVIDE(__efistub_screen_info = screen_info);
#endif
PROVIDE(__efistub__ctype = _ctype);
PROVIDE(__pi___memcpy = __pi_memcpy);

12
arch/csky/kernel/setup.c
View File

@ -8,22 +8,10 @@
#include <linux/of_fdt.h>
#include <linux/start_kernel.h>
#include <linux/dma-map-ops.h>
#include <linux/screen_info.h>
#include <asm/sections.h>
#include <asm/mmu_context.h>
#include <asm/pgalloc.h>
#ifdef CONFIG_DUMMY_CONSOLE
struct screen_info screen_info = {
.orig_video_lines = 30,
.orig_video_cols = 80,
.orig_video_mode = 0,
.orig_video_ega_bx = 0,
.orig_video_isVGA = 1,
.orig_video_points = 8
};
#endif
static void __init csky_memblock_init(void)
{
unsigned long lowmem_size = PFN_DOWN(LOWMEM_LIMIT - PHYS_OFFSET_OFFSET);

2
arch/hexagon/kernel/Makefile
View File

@ -17,5 +17,3 @@ obj-y += vm_vectors.o
obj-$(CONFIG_HAS_DMA) += dma.o
obj-$(CONFIG_STACKTRACE) += stacktrace.o
obj-$(CONFIG_VGA_CONSOLE) += screen_info.o

3
arch/hexagon/kernel/screen_info.c
View File

@ -1,3 +0,0 @@
#include <linux/screen_info.h>
struct screen_info screen_info;

8
arch/loongarch/kernel/efi.c
View File

@ -68,6 +68,11 @@ void __init efi_runtime_init(void)
unsigned long __initdata screen_info_table = EFI_INVALID_TABLE_ADDR;
#if defined(CONFIG_SYSFB) || defined(CONFIG_EFI_EARLYCON)
struct screen_info screen_info __section(".data");
EXPORT_SYMBOL_GPL(screen_info);
#endif
static void __init init_screen_info(void)
{
struct screen_info *si;
@ -115,7 +120,8 @@ void __init efi_init(void)
set_bit(EFI_CONFIG_TABLES, &efi.flags);
init_screen_info();
if (IS_ENABLED(CONFIG_EFI_EARLYCON) || IS_ENABLED(CONFIG_SYSFB))
init_screen_info();
if (boot_memmap == EFI_INVALID_TABLE_ADDR)
return;

2
arch/loongarch/kernel/image-vars.h
View File

@ -12,7 +12,9 @@ __efistub_kernel_entry = kernel_entry;
__efistub_kernel_asize = kernel_asize;
__efistub_kernel_fsize = kernel_fsize;
__efistub_kernel_offset = kernel_offset;
#if defined(CONFIG_EFI_EARLYCON) || defined(CONFIG_SYSFB)
__efistub_screen_info = screen_info;
#endif
#endif

3
arch/loongarch/kernel/setup.c
View File

@ -16,7 +16,6 @@
#include <linux/dmi.h>
#include <linux/efi.h>
#include <linux/export.h>
#include <linux/screen_info.h>
#include <linux/memblock.h>
#include <linux/initrd.h>
#include <linux/ioport.h>
@ -57,8 +56,6 @@
#define SMBIOS_CORE_PACKAGE_OFFSET 0x23
#define LOONGSON_EFI_ENABLE (1 << 3)
struct screen_info screen_info __section(".data");
unsigned long fw_arg0, fw_arg1, fw_arg2;
DEFINE_PER_CPU(unsigned long, kernelsp);
struct cpuinfo_loongarch cpu_data[NR_CPUS] __read_mostly;

9
arch/mips/jazz/setup.c
View File

@ -13,7 +13,6 @@
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/console.h>
#include <linux/screen_info.h>
#include <linux/platform_device.h>
#include <linux/serial_8250.h>
#include <linux/dma-mapping.h>
@ -76,14 +75,6 @@ void __init plat_mem_setup(void)
_machine_restart = jazz_machine_restart;
#ifdef CONFIG_VT
screen_info = (struct screen_info) {
.orig_video_cols = 160,
.orig_video_lines = 64,
.orig_video_points = 16,
};
#endif
add_preferred_console("ttyS", 0, "9600");
}

11
arch/mips/kernel/setup.c
View File

@ -15,7 +15,6 @@
#include <linux/delay.h>
#include <linux/ioport.h>
#include <linux/export.h>
#include <linux/screen_info.h>
#include <linux/memblock.h>
#include <linux/initrd.h>
#include <linux/root_dev.h>
@ -54,10 +53,6 @@ struct cpuinfo_mips cpu_data[NR_CPUS] __read_mostly;
EXPORT_SYMBOL(cpu_data);
#ifdef CONFIG_VT
struct screen_info screen_info;
#endif
/*
* Setup information
*
@ -793,12 +788,6 @@ void __init setup_arch(char **cmdline_p)
if (IS_ENABLED(CONFIG_CPU_R4X00_BUGS64))
check_bugs64_early();
#if defined(CONFIG_VT)
#if defined(CONFIG_VGA_CONSOLE)
conswitchp = &vga_con;
#endif
#endif
arch_mem_init(cmdline_p);
dmi_setup();

4
arch/mips/mti-malta/malta-setup.c
View File

@ -161,7 +161,7 @@ static void __init pci_clock_check(void)
#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)
static void __init screen_info_setup(void)
{
screen_info = (struct screen_info) {
static struct screen_info si = {
.orig_x = 0,
.orig_y = 25,
.ext_mem_k = 0,
@ -175,6 +175,8 @@ static void __init screen_info_setup(void)
.orig_video_isVGA = VIDEO_TYPE_VGAC,
.orig_video_points = 16
};
vgacon_register_screen(&si);
}
#endif

27
arch/mips/sibyte/swarm/setup.c
View File

@ -13,6 +13,7 @@
#include <linux/memblock.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/console.h>
#include <linux/screen_info.h>
#include <linux/initrd.h>
@ -112,6 +113,19 @@ int update_persistent_clock64(struct timespec64 now)
}
}
#ifdef CONFIG_VGA_CONSOLE
static struct screen_info vgacon_screen_info = {
.orig_video_page = 52,
.orig_video_mode = 3,
.orig_video_cols = 80,
.flags = 12,
.orig_video_ega_bx = 3,
.orig_video_lines = 25,
.orig_video_isVGA = 0x22,
.orig_video_points = 16,
};
#endif
void __init plat_mem_setup(void)
{
#ifdef CONFIG_SIBYTE_BCM1x80
@ -129,17 +143,8 @@ void __init plat_mem_setup(void)
if (m41t81_probe())
swarm_rtc_type = RTC_M41T81;
#ifdef CONFIG_VT
screen_info = (struct screen_info) {
.orig_video_page = 52,
.orig_video_mode = 3,
.orig_video_cols = 80,
.flags = 12,
.orig_video_ega_bx = 3,
.orig_video_lines = 25,
.orig_video_isVGA = 0x22,
.orig_video_points = 16,
};
#ifdef CONFIG_VGA_CONSOLE
vgacon_register_screen(&vgacon_screen_info);
/* XXXKW for CFE, get lines/cols from environment */
#endif
}

18
arch/mips/sni/setup.c
View File

@ -38,19 +38,21 @@ extern void sni_machine_power_off(void);
static void __init sni_display_setup(void)
{
#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE) && defined(CONFIG_FW_ARC)
struct screen_info *si = &screen_info;
#if defined(CONFIG_VGA_CONSOLE) && defined(CONFIG_FW_ARC)
static struct screen_info si;
DISPLAY_STATUS *di;
di = ArcGetDisplayStatus(1);
if (di) {
si->orig_x = di->CursorXPosition;
si->orig_y = di->CursorYPosition;
si->orig_video_cols = di->CursorMaxXPosition;
si->orig_video_lines = di->CursorMaxYPosition;
si->orig_video_isVGA = VIDEO_TYPE_VGAC;
si->orig_video_points = 16;
si.orig_x = di->CursorXPosition;
si.orig_y = di->CursorYPosition;
si.orig_video_cols = di->CursorMaxXPosition;
si.orig_video_lines = di->CursorMaxYPosition;
si.orig_video_isVGA = VIDEO_TYPE_VGAC;
si.orig_video_points = 16;
vgacon_register_screen(&si);
}
#endif
}

5
arch/nios2/kernel/setup.c
View File

@ -19,7 +19,6 @@
#include <linux/memblock.h>
#include <linux/initrd.h>
#include <linux/of_fdt.h>
#include <linux/screen_info.h>
#include <asm/mmu_context.h>
#include <asm/sections.h>
@ -36,10 +35,6 @@ static struct pt_regs fake_regs = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
0};
#ifdef CONFIG_VT
struct screen_info screen_info;
#endif
/* Copy a short hook instruction sequence to the exception address */
static inline void copy_exception_handler(unsigned int addr)
{

16
arch/powerpc/kernel/setup-common.c
View File

@ -22,7 +22,6 @@
#include <linux/seq_file.h>
#include <linux/ioport.h>
#include <linux/console.h>
#include <linux/screen_info.h>
#include <linux/root_dev.h>
#include <linux/cpu.h>
#include <linux/unistd.h>
@ -98,21 +97,6 @@ int boot_cpu_hwid = -1;
int dcache_bsize;
int icache_bsize;
/*
* This still seems to be needed... -- paulus
*/
struct screen_info screen_info = {
.orig_x = 0,
.orig_y = 25,
.orig_video_cols = 80,
.orig_video_lines = 25,
.orig_video_isVGA = 1,
.orig_video_points = 16
};
#if defined(CONFIG_FB_VGA16_MODULE)
EXPORT_SYMBOL(screen_info);
#endif
/* Variables required to store legacy IO irq routing */
int of_i8042_kbd_irq;
EXPORT_SYMBOL_GPL(of_i8042_kbd_irq);

2
arch/riscv/kernel/image-vars.h
View File

@ -28,7 +28,9 @@ __efistub__start_kernel = _start_kernel;
__efistub__end = _end;
__efistub__edata = _edata;
__efistub___init_text_end = __init_text_end;
#if defined(CONFIG_EFI_EARLYCON) || defined(CONFIG_SYSFB)
__efistub_screen_info = screen_info;
#endif
#endif

12
arch/riscv/kernel/setup.c
View File

@ -15,7 +15,6 @@
#include <linux/memblock.h>
#include <linux/sched.h>
#include <linux/console.h>
#include <linux/screen_info.h>
#include <linux/of_fdt.h>
#include <linux/sched/task.h>
#include <linux/smp.h>
@ -40,17 +39,6 @@
#include "head.h"
#if defined(CONFIG_DUMMY_CONSOLE) || defined(CONFIG_EFI)
struct screen_info screen_info __section(".data") = {
.orig_video_lines = 30,
.orig_video_cols = 80,
.orig_video_mode = 0,
.orig_video_ega_bx = 0,
.orig_video_isVGA = 1,
.orig_video_points = 8
};
#endif
/*
* The lucky hart to first increment this variable will boot the other cores.
* This is used before the kernel initializes the BSS so it can't be in the

5
arch/sh/kernel/setup.c
View File

@ -7,7 +7,6 @@
* Copyright (C) 1999 Niibe Yutaka
* Copyright (C) 2002 - 2010 Paul Mundt
*/
#include <linux/screen_info.h>
#include <linux/ioport.h>
#include <linux/init.h>
#include <linux/initrd.h>
@ -69,10 +68,6 @@ EXPORT_SYMBOL(cpu_data);
struct sh_machine_vector sh_mv = { .mv_name = "generic", };
EXPORT_SYMBOL(sh_mv);
#ifdef CONFIG_VT
struct screen_info screen_info;
#endif
extern int root_mountflags;
#define RAMDISK_IMAGE_START_MASK 0x07FF

13
arch/sparc/kernel/setup_32.c
View File

@ -17,7 +17,6 @@
#include <linux/initrd.h>
#include <asm/smp.h>
#include <linux/user.h>
#include <linux/screen_info.h>
#include <linux/delay.h>
#include <linux/fs.h>
#include <linux/seq_file.h>
@ -51,18 +50,6 @@
#include "kernel.h"
struct screen_info screen_info = {
0, 0, /* orig-x, orig-y */
0, /* unused */
0, /* orig-video-page */
0, /* orig-video-mode */
128, /* orig-video-cols */
0,0,0, /* ega_ax, ega_bx, ega_cx */
54, /* orig-video-lines */
0, /* orig-video-isVGA */
16 /* orig-video-points */
};
/* Typing sync at the prom prompt calls the function pointed to by
* romvec->pv_synchook which I set to the following function.
* This should sync all filesystems and return, for now it just

13
arch/sparc/kernel/setup_64.c
View File

@ -15,7 +15,6 @@
#include <linux/ptrace.h>
#include <asm/smp.h>
#include <linux/user.h>
#include <linux/screen_info.h>
#include <linux/delay.h>
#include <linux/fs.h>
#include <linux/seq_file.h>
@ -68,18 +67,6 @@
DEFINE_SPINLOCK(ns87303_lock);
EXPORT_SYMBOL(ns87303_lock);
struct screen_info screen_info = {
0, 0, /* orig-x, orig-y */
0, /* unused */
0, /* orig-video-page */
0, /* orig-video-mode */
128, /* orig-video-cols */
0, 0, 0, /* unused, ega_bx, unused */
54, /* orig-video-lines */
0, /* orig-video-isVGA */
16 /* orig-video-points */
};
static void
prom_console_write(struct console *con, const char *s, unsigned int n)
{

2
arch/x86/kernel/setup.c
View File

@ -1167,7 +1167,7 @@ void __init setup_arch(char **cmdline_p)
#ifdef CONFIG_VT
#if defined(CONFIG_VGA_CONSOLE)
if (!efi_enabled(EFI_BOOT) || (efi_mem_type(0xa0000) != EFI_CONVENTIONAL_MEMORY))
conswitchp = &vga_con;
vgacon_register_screen(&screen_info);
#endif
#endif
x86_init.oem.banner();

12
arch/xtensa/kernel/setup.c
View File

@ -19,7 +19,6 @@
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/proc_fs.h>
#include <linux/screen_info.h>
#include <linux/kernel.h>
#include <linux/percpu.h>
#include <linux/reboot.h>
@ -49,17 +48,6 @@
#include <asm/timex.h>
#include <asm/traps.h>
#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
struct screen_info screen_info = {
.orig_x = 0,
.orig_y = 24,
.orig_video_cols = 80,
.orig_video_lines = 24,
.orig_video_isVGA = 1,
.orig_video_points = 16,
};
#endif
#ifdef CONFIG_BLK_DEV_INITRD
extern unsigned long initrd_start;
extern unsigned long initrd_end;

14
drivers/firmware/efi/efi-init.c
View File

@ -55,6 +55,15 @@ static phys_addr_t __init efi_to_phys(unsigned long addr)
extern __weak const efi_config_table_type_t efi_arch_tables[];
/*
* x86 defines its own screen_info and uses it even without EFI,
* everything else can get it from here.
*/
#if !defined(CONFIG_X86) && (defined(CONFIG_SYSFB) || defined(CONFIG_EFI_EARLYCON))
struct screen_info screen_info __section(".data");
EXPORT_SYMBOL_GPL(screen_info);
#endif
static void __init init_screen_info(void)
{
struct screen_info *si;
@ -240,5 +249,8 @@ void __init efi_init(void)
memblock_reserve(data.phys_map & PAGE_MASK,
PAGE_ALIGN(data.size + (data.phys_map & ~PAGE_MASK)));
init_screen_info();
if (IS_ENABLED(CONFIG_X86) ||
IS_ENABLED(CONFIG_SYSFB) ||
IS_ENABLED(CONFIG_EFI_EARLYCON))
init_screen_info();
}

8
drivers/firmware/efi/libstub/efi-stub-entry.c
View File

@ -13,7 +13,13 @@ struct screen_info *alloc_screen_info(void)
{
if (IS_ENABLED(CONFIG_ARM))
return __alloc_screen_info();
return (void *)&screen_info + screen_info_offset;
if (IS_ENABLED(CONFIG_X86) ||
IS_ENABLED(CONFIG_EFI_EARLYCON) ||
IS_ENABLED(CONFIG_SYSFB))
return (void *)&screen_info + screen_info_offset;
return NULL;
}
/*

7
drivers/gpu/drm/hyperv/hyperv_drm_drv.c
View File

@ -73,9 +73,10 @@ static int hyperv_setup_vram(struct hyperv_drm_device *hv,
struct drm_device *dev = &hv->dev;
int ret;
drm_aperture_remove_conflicting_framebuffers(screen_info.lfb_base,
screen_info.lfb_size,
&hyperv_driver);
if (IS_ENABLED(CONFIG_SYSFB))
drm_aperture_remove_conflicting_framebuffers(screen_info.lfb_base,
screen_info.lfb_size,
&hyperv_driver);
hv->fb_size = (unsigned long)hv->mmio_megabytes * 1024 * 1024;

6
drivers/hv/vmbus_drv.c
View File

@ -2100,8 +2100,10 @@ static void __maybe_unused vmbus_reserve_fb(void)
if (efi_enabled(EFI_BOOT)) {
/* Gen2 VM: get FB base from EFI framebuffer */
start = screen_info.lfb_base;
size = max_t(__u32, screen_info.lfb_size, 0x800000);
if (IS_ENABLED(CONFIG_SYSFB)) {
start = screen_info.lfb_base;
size = max_t(__u32, screen_info.lfb_size, 0x800000);
}
} else {
/* Gen1 VM: get FB base from PCI */
pdev = pci_get_device(PCI_VENDOR_ID_MICROSOFT,

39
drivers/tty/hvc/hvc_xen.c
View File

@ -377,18 +377,21 @@ void xen_console_resume(void)
#ifdef CONFIG_HVC_XEN_FRONTEND
static void xencons_disconnect_backend(struct xencons_info *info)
{
if (info->irq > 0)
unbind_from_irqhandler(info->irq, NULL);
info->irq = 0;
if (info->hvc != NULL)
hvc_remove(info->hvc);
info->hvc = NULL;
if (info->irq > 0) {
evtchn_put(info->evtchn);
info->irq = 0;
info->evtchn = 0;
}
/* evtchn_put() will also close it so this is only an error path */
if (info->evtchn > 0)
xenbus_free_evtchn(info->xbdev, info->evtchn);
info->evtchn = 0;
if (info->gntref > 0)
gnttab_free_grant_references(info->gntref);
info->gntref = 0;
if (info->hvc != NULL)
hvc_remove(info->hvc);
info->hvc = NULL;
}
static void xencons_free(struct xencons_info *info)
@ -433,7 +436,7 @@ static int xencons_connect_backend(struct xenbus_device *dev,
if (ret)
return ret;
info->evtchn = evtchn;
irq = bind_interdomain_evtchn_to_irq_lateeoi(dev, evtchn);
irq = bind_evtchn_to_irq_lateeoi(evtchn);
if (irq < 0)
return irq;
info->irq = irq;
@ -553,10 +556,23 @@ static void xencons_backend_changed(struct xenbus_device *dev,
if (dev->state == XenbusStateClosed)
break;
fallthrough; /* Missed the backend's CLOSING state */
case XenbusStateClosing:
case XenbusStateClosing: {
struct xencons_info *info = dev_get_drvdata(&dev->dev);;
/*
* Don't tear down the evtchn and grant ref before the other
* end has disconnected, but do stop userspace from trying
* to use the device before we allow the backend to close.
*/
if (info->hvc) {
hvc_remove(info->hvc);
info->hvc = NULL;
}
xenbus_frontend_closed(dev);
break;
}
}
}
static const struct xenbus_device_id xencons_ids[] = {
@ -588,7 +604,7 @@ static int __init xen_hvc_init(void)
ops = &dom0_hvc_ops;
r = xen_initial_domain_console_init();
if (r < 0)
return r;
goto register_fe;
info = vtermno_to_xencons(HVC_COOKIE);
} else {
ops = &domU_hvc_ops;
@ -597,7 +613,7 @@ static int __init xen_hvc_init(void)
else
r = xen_pv_console_init();
if (r < 0)
return r;
goto register_fe;
info = vtermno_to_xencons(HVC_COOKIE);
info->irq = bind_evtchn_to_irq_lateeoi(info->evtchn);
@ -616,12 +632,13 @@ static int __init xen_hvc_init(void)
list_del(&info->list);
spin_unlock_irqrestore(&xencons_lock, flags);
if (info->irq)
unbind_from_irqhandler(info->irq, NULL);
evtchn_put(info->evtchn);
kfree(info);
return r;
}
r = 0;
register_fe:
#ifdef CONFIG_HVC_XEN_FRONTEND
r = xenbus_register_frontend(&xencons_driver);
#endif

2
drivers/tty/hvc/hvcs.c
View File

@ -664,7 +664,6 @@ static void hvcs_return_index(int index)
static void hvcs_destruct_port(struct tty_port *p)
{
struct hvcs_struct *hvcsd = container_of(p, struct hvcs_struct, port);
struct vio_dev *vdev;
struct completion *comp;
unsigned long flags;
@ -686,7 +685,6 @@ static void hvcs_destruct_port(struct tty_port *p)
printk(KERN_INFO "HVCS: Destroyed hvcs_struct for vty-server@%X.\n",
hvcsd->vdev->unit_address);
vdev = hvcsd->vdev;
hvcsd->vdev = NULL;
hvcsd->p_unit_address = 0;

2
drivers/tty/mxser.c
View File

@ -288,7 +288,7 @@ struct mxser_board {
enum mxser_must_hwid must_hwid;
speed_t max_baud;
struct mxser_port ports[];
struct mxser_port ports[] __counted_by(nports);
};
static DECLARE_BITMAP(mxser_boards, MXSER_BOARDS);

3
drivers/tty/n_gsm.c
View File

@ -2,6 +2,7 @@
/*
* n_gsm.c GSM 0710 tty multiplexor
* Copyright (c) 2009/10 Intel Corporation
* Copyright (c) 2022/23 Siemens Mobility GmbH
*
* * THIS IS A DEVELOPMENT SNAPSHOT IT IS NOT A FINAL RELEASE *
*
@ -4108,6 +4109,8 @@ static int gsm_modem_upd_via_msc(struct gsm_dlci *dlci, u8 brk)
static int gsm_modem_update(struct gsm_dlci *dlci, u8 brk)
{
if (dlci->gsm->dead)
return -EL2HLT;
if (dlci->adaption == 2) {
/* Send convergence layer type 2 empty data frame. */
gsm_modem_upd_via_data(dlci, brk);

75
drivers/tty/n_tty.c
View File

@ -249,15 +249,12 @@ static void n_tty_check_throttle(struct tty_struct *tty)
if (ldata->icanon && ldata->canon_head == ldata->read_tail)
return;
while (1) {
int throttled;
do {
tty_set_flow_change(tty, TTY_THROTTLE_SAFE);
if (N_TTY_BUF_SIZE - read_cnt(ldata) >= TTY_THRESHOLD_THROTTLE)
break;
throttled = tty_throttle_safe(tty);
if (!throttled)
break;
}
} while (!tty_throttle_safe(tty));
__tty_set_flow_change(tty, 0);
}
@ -279,16 +276,14 @@ static void n_tty_check_unthrottle(struct tty_struct *tty)
* we won't get any more characters.
*/
while (1) {
int unthrottled;
do {
tty_set_flow_change(tty, TTY_UNTHROTTLE_SAFE);
if (chars_in_buffer(tty) > TTY_THRESHOLD_UNTHROTTLE)
break;
n_tty_kick_worker(tty);
unthrottled = tty_unthrottle_safe(tty);
if (!unthrottled)
break;
}
} while (!tty_unthrottle_safe(tty));
__tty_set_flow_change(tty, 0);
}
@ -1965,26 +1960,27 @@ static bool copy_from_read_buf(const struct tty_struct *tty, u8 **kbp,
size_t head = smp_load_acquire(&ldata->commit_head);
size_t tail = MASK(ldata->read_tail);
n = min(head - ldata->read_tail, N_TTY_BUF_SIZE - tail);
n = min(*nr, n);
if (n) {
u8 *from = read_buf_addr(ldata, tail);
memcpy(*kbp, from, n);
is_eof = n == 1 && *from == EOF_CHAR(tty);
tty_audit_add_data(tty, from, n);
zero_buffer(tty, from, n);
smp_store_release(&ldata->read_tail, ldata->read_tail + n);
/* Turn single EOF into zero-length read */
if (L_EXTPROC(tty) && ldata->icanon && is_eof &&
(head == ldata->read_tail))
return false;
*kbp += n;
*nr -= n;
n = min3(head - ldata->read_tail, N_TTY_BUF_SIZE - tail, *nr);
if (!n)
return false;
/* If we have more to copy, let the caller know */
return head != ldata->read_tail;
}
return false;
u8 *from = read_buf_addr(ldata, tail);
memcpy(*kbp, from, n);
is_eof = n == 1 && *from == EOF_CHAR(tty);
tty_audit_add_data(tty, from, n);
zero_buffer(tty, from, n);
smp_store_release(&ldata->read_tail, ldata->read_tail + n);
/* Turn single EOF into zero-length read */
if (L_EXTPROC(tty) && ldata->icanon && is_eof &&
head == ldata->read_tail)
return false;
*kbp += n;
*nr -= n;
/* If we have more to copy, let the caller know */
return head != ldata->read_tail;
}
/**
@ -2154,9 +2150,8 @@ static ssize_t n_tty_read(struct tty_struct *tty, struct file *file, u8 *kbuf,
struct n_tty_data *ldata = tty->disc_data;
u8 *kb = kbuf;
DEFINE_WAIT_FUNC(wait, woken_wake_function);
int c;
int minimum, time;
ssize_t retval = 0;
ssize_t retval;
long timeout;
bool packet;
size_t old_tail;
@ -2192,9 +2187,9 @@ static ssize_t n_tty_read(struct tty_struct *tty, struct file *file, u8 *kbuf,
return kb - kbuf;
}
c = job_control(tty, file);
if (c < 0)
return c;
retval = job_control(tty, file);
if (retval < 0)
return retval;
/*
* Internal serialization of reads.
@ -2499,7 +2494,7 @@ static int n_tty_ioctl(struct tty_struct *tty, unsigned int cmd,
unsigned long arg)
{
struct n_tty_data *ldata = tty->disc_data;
int retval;
unsigned int num;
switch (cmd) {
case TIOCOUTQ:
@ -2507,11 +2502,11 @@ static int n_tty_ioctl(struct tty_struct *tty, unsigned int cmd,
case TIOCINQ:
down_write(&tty->termios_rwsem);
if (L_ICANON(tty) && !L_EXTPROC(tty))
retval = inq_canon(ldata);
num = inq_canon(ldata);
else
retval = read_cnt(ldata);
num = read_cnt(ldata);
up_write(&tty->termios_rwsem);
return put_user(retval, (unsigned int __user *) arg);
return put_user(num, (unsigned int __user *) arg);
default:
return n_tty_ioctl_helper(tty, cmd, arg);
}

24
drivers/tty/serdev/core.c
View File

@ -15,9 +15,11 @@
#include <linux/of_device.h>
#include <linux/pm_domain.h>
#include <linux/pm_runtime.h>
#include <linux/property.h>
#include <linux/sched.h>
#include <linux/serdev.h>
#include <linux/slab.h>
#include <linux/platform_data/x86/apple.h>
static bool is_registered;
@ -185,30 +187,20 @@ void serdev_device_close(struct serdev_device *serdev)
}
EXPORT_SYMBOL_GPL(serdev_device_close);
static void devm_serdev_device_release(struct device *dev, void *dr)
static void devm_serdev_device_close(void *serdev)
{
serdev_device_close(*(struct serdev_device **)dr);
serdev_device_close(serdev);
}
int devm_serdev_device_open(struct device *dev, struct serdev_device *serdev)
{
struct serdev_device **dr;
int ret;
dr = devres_alloc(devm_serdev_device_release, sizeof(*dr), GFP_KERNEL);
if (!dr)
return -ENOMEM;
ret = serdev_device_open(serdev);
if (ret) {
devres_free(dr);
if (ret)
return ret;
}
*dr = serdev;
devres_add(dev, dr);
return 0;
return devm_add_action_or_reset(dev, devm_serdev_device_close, serdev);
}
EXPORT_SYMBOL_GPL(devm_serdev_device_open);
@ -510,7 +502,7 @@ struct serdev_controller *serdev_controller_alloc(struct device *parent,
ctrl->dev.type = &serdev_ctrl_type;
ctrl->dev.bus = &serdev_bus_type;
ctrl->dev.parent = parent;
ctrl->dev.of_node = parent->of_node;
device_set_node(&ctrl->dev, dev_fwnode(parent));
serdev_controller_set_drvdata(ctrl, &ctrl[1]);
dev_set_name(&ctrl->dev, "serial%d", id);
@ -673,7 +665,7 @@ static int acpi_serdev_check_resources(struct serdev_controller *ctrl,
acpi_get_parent(adev->handle, &lookup.controller_handle);
/* Make sure controller and ResourceSource handle match */
if (ACPI_HANDLE(ctrl->dev.parent) != lookup.controller_handle)
if (!device_match_acpi_handle(ctrl->dev.parent, lookup.controller_handle))
return -ENODEV;
return 0;

8
drivers/tty/serial/21285.c
View File

@ -185,14 +185,14 @@ static void serial21285_break_ctl(struct uart_port *port, int break_state)
unsigned long flags;
unsigned int h_lcr;
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
h_lcr = *CSR_H_UBRLCR;
if (break_state)
h_lcr |= H_UBRLCR_BREAK;
else
h_lcr &= ~H_UBRLCR_BREAK;
*CSR_H_UBRLCR = h_lcr;
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
}
static int serial21285_startup(struct uart_port *port)
@ -272,7 +272,7 @@ serial21285_set_termios(struct uart_port *port, struct ktermios *termios,
if (port->fifosize)
h_lcr |= H_UBRLCR_FIFO;
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
/*
* Update the per-port timeout.
@ -309,7 +309,7 @@ serial21285_set_termios(struct uart_port *port, struct ktermios *termios,
*CSR_H_UBRLCR = h_lcr;
*CSR_UARTCON = 1;
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
}
static const char *serial21285_type(struct uart_port *port)

33
drivers/tty/serial/8250/8250_aspeed_vuart.c
View File

@ -34,7 +34,6 @@
struct aspeed_vuart {
struct device *dev;
struct clk *clk;
int line;
struct timer_list unthrottle_timer;
struct uart_8250_port *port;
@ -288,9 +287,9 @@ static void aspeed_vuart_set_throttle(struct uart_port *port, bool throttle)
struct uart_8250_port *up = up_to_u8250p(port);
unsigned long flags;
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
__aspeed_vuart_set_throttle(up, throttle);
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
}
static void aspeed_vuart_throttle(struct uart_port *port)
@ -340,7 +339,7 @@ static int aspeed_vuart_handle_irq(struct uart_port *port)
if (iir & UART_IIR_NO_INT)
return 0;
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
lsr = serial_port_in(port, UART_LSR);
@ -415,12 +414,14 @@ static int aspeed_vuart_map_irq_polarity(u32 dt)
static int aspeed_vuart_probe(struct platform_device *pdev)
{
struct of_phandle_args sirq_polarity_sense_args;
struct device *dev = &pdev->dev;
struct uart_8250_port port;
struct aspeed_vuart *vuart;
struct device_node *np;
struct resource *res;
u32 clk, prop, sirq[2];
int rc, sirq_polarity;
struct clk *vclk;
np = pdev->dev.of_node;
@ -453,19 +454,13 @@ static int aspeed_vuart_probe(struct platform_device *pdev)
return rc;
if (of_property_read_u32(np, "clock-frequency", &clk)) {
vuart->clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(vuart->clk)) {
dev_warn(&pdev->dev,
"clk or clock-frequency not defined\n");
rc = PTR_ERR(vuart->clk);
vclk = devm_clk_get_enabled(dev, NULL);
if (IS_ERR(vclk)) {
rc = dev_err_probe(dev, PTR_ERR(vclk), "clk or clock-frequency not defined\n");
goto err_sysfs_remove;
}
rc = clk_prepare_enable(vuart->clk);
if (rc < 0)
goto err_sysfs_remove;
clk = clk_get_rate(vuart->clk);
clk = clk_get_rate(vclk);
}
/* If current-speed was set, then try not to change it. */
@ -533,7 +528,7 @@ static int aspeed_vuart_probe(struct platform_device *pdev)
rc = aspeed_vuart_set_lpc_address(vuart, prop);
if (rc < 0) {
dev_err(&pdev->dev, "invalid value in aspeed,lpc-io-reg property\n");
dev_err_probe(dev, rc, "invalid value in aspeed,lpc-io-reg property\n");
goto err_clk_disable;
}
@ -545,14 +540,14 @@ static int aspeed_vuart_probe(struct platform_device *pdev)
rc = aspeed_vuart_set_sirq(vuart, sirq[0]);
if (rc < 0) {
dev_err(&pdev->dev, "invalid sirq number in aspeed,lpc-interrupts property\n");
dev_err_probe(dev, rc, "invalid sirq number in aspeed,lpc-interrupts property\n");
goto err_clk_disable;
}
sirq_polarity = aspeed_vuart_map_irq_polarity(sirq[1]);
if (sirq_polarity < 0) {
dev_err(&pdev->dev, "invalid sirq polarity in aspeed,lpc-interrupts property\n");
rc = sirq_polarity;
rc = dev_err_probe(dev, sirq_polarity,
"invalid sirq polarity in aspeed,lpc-interrupts property\n");
goto err_clk_disable;
}
@ -565,7 +560,6 @@ static int aspeed_vuart_probe(struct platform_device *pdev)
return 0;
err_clk_disable:
clk_disable_unprepare(vuart->clk);
irq_dispose_mapping(port.port.irq);
err_sysfs_remove:
sysfs_remove_group(&vuart->dev->kobj, &aspeed_vuart_attr_group);
@ -580,7 +574,6 @@ static int aspeed_vuart_remove(struct platform_device *pdev)
aspeed_vuart_set_enabled(vuart, false);
serial8250_unregister_port(vuart->line);
sysfs_remove_group(&vuart->dev->kobj, &aspeed_vuart_attr_group);
clk_disable_unprepare(vuart->clk);
return 0;
}

69
drivers/tty/serial/8250/8250_bcm7271.c
View File

@ -567,7 +567,7 @@ static irqreturn_t brcmuart_isr(int irq, void *dev_id)
if (interrupts == 0)
return IRQ_NONE;
spin_lock_irqsave(&up->lock, flags);
uart_port_lock_irqsave(up, &flags);
/* Clear all interrupts */
udma_writel(priv, REGS_DMA_ISR, UDMA_INTR_CLEAR, interrupts);
@ -581,7 +581,7 @@ static irqreturn_t brcmuart_isr(int irq, void *dev_id)
if ((rval | tval) == 0)
dev_warn(dev, "Spurious interrupt: 0x%x\n", interrupts);
spin_unlock_irqrestore(&up->lock, flags);
uart_port_unlock_irqrestore(up, flags);
return IRQ_HANDLED;
}
@ -608,10 +608,10 @@ static int brcmuart_startup(struct uart_port *port)
*
* Synchronize UART_IER access against the console.
*/
spin_lock_irq(&port->lock);
uart_port_lock_irq(port);
up->ier &= ~UART_IER_RDI;
serial_port_out(port, UART_IER, up->ier);
spin_unlock_irq(&port->lock);
uart_port_unlock_irq(port);
priv->tx_running = false;
priv->dma.rx_dma = NULL;
@ -629,7 +629,7 @@ static void brcmuart_shutdown(struct uart_port *port)
struct brcmuart_priv *priv = up->port.private_data;
unsigned long flags;
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
priv->shutdown = true;
if (priv->dma_enabled) {
stop_rx_dma(up);
@ -645,7 +645,7 @@ static void brcmuart_shutdown(struct uart_port *port)
*/
up->dma = NULL;
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
serial8250_do_shutdown(port);
}
@ -788,7 +788,7 @@ static int brcmuart_handle_irq(struct uart_port *p)
* interrupt but there is no data ready.
*/
if (((iir & UART_IIR_ID) == UART_IIR_RX_TIMEOUT) && !(priv->shutdown)) {
spin_lock_irqsave(&p->lock, flags);
uart_port_lock_irqsave(p, &flags);
status = serial_port_in(p, UART_LSR);
if ((status & UART_LSR_DR) == 0) {
@ -813,7 +813,7 @@ static int brcmuart_handle_irq(struct uart_port *p)
handled = 1;
}
spin_unlock_irqrestore(&p->lock, flags);
uart_port_unlock_irqrestore(p, flags);
if (handled)
return 1;
}
@ -831,7 +831,7 @@ static enum hrtimer_restart brcmuart_hrtimer_func(struct hrtimer *t)
if (priv->shutdown)
return HRTIMER_NORESTART;
spin_lock_irqsave(&p->lock, flags);
uart_port_lock_irqsave(p, &flags);
status = serial_port_in(p, UART_LSR);
/*
@ -855,7 +855,7 @@ static enum hrtimer_restart brcmuart_hrtimer_func(struct hrtimer *t)
status |= UART_MCR_RTS;
serial_port_out(p, UART_MCR, status);
}
spin_unlock_irqrestore(&p->lock, flags);
uart_port_unlock_irqrestore(p, flags);
return HRTIMER_NORESTART;
}
@ -984,10 +984,9 @@ static int brcmuart_probe(struct platform_device *pdev)
}
/* We should have just the uart base registers or all the registers */
if (x != 1 && x != REGS_MAX) {
dev_warn(dev, "%s registers not specified\n", reg_names[x]);
return -EINVAL;
}
if (x != 1 && x != REGS_MAX)
return dev_err_probe(dev, -EINVAL, "%s registers not specified\n",
reg_names[x]);
/* if the DMA registers were specified, try to enable DMA */
if (x > REGS_DMA_RX) {
@ -1016,27 +1015,23 @@ static int brcmuart_probe(struct platform_device *pdev)
of_property_read_u32(np, "clock-frequency", &clk_rate);
/* See if a Baud clock has been specified */
baud_mux_clk = devm_clk_get(dev, "sw_baud");
if (IS_ERR(baud_mux_clk)) {
if (PTR_ERR(baud_mux_clk) == -EPROBE_DEFER) {
ret = -EPROBE_DEFER;
goto release_dma;
}
dev_dbg(dev, "BAUD MUX clock not specified\n");
} else {
baud_mux_clk = devm_clk_get_optional_enabled(dev, "sw_baud");
ret = PTR_ERR_OR_ZERO(baud_mux_clk);
if (ret)
goto release_dma;
if (baud_mux_clk) {
dev_dbg(dev, "BAUD MUX clock found\n");
ret = clk_prepare_enable(baud_mux_clk);
if (ret)
goto release_dma;
priv->baud_mux_clk = baud_mux_clk;
init_real_clk_rates(dev, priv);
clk_rate = priv->default_mux_rate;
} else {
dev_dbg(dev, "BAUD MUX clock not specified\n");
}
if (clk_rate == 0) {
dev_err(dev, "clock-frequency or clk not defined\n");
ret = -EINVAL;
goto err_clk_disable;
ret = dev_err_probe(dev, -EINVAL, "clock-frequency or clk not defined\n");
goto release_dma;
}
dev_dbg(dev, "DMA is %senabled\n", priv->dma_enabled ? "" : "not ");
@ -1093,7 +1088,7 @@ static int brcmuart_probe(struct platform_device *pdev)
ret = serial8250_register_8250_port(&up);
if (ret < 0) {
dev_err(dev, "unable to register 8250 port\n");
dev_err_probe(dev, ret, "unable to register 8250 port\n");
goto err;
}
priv->line = ret;
@ -1102,14 +1097,13 @@ static int brcmuart_probe(struct platform_device *pdev)
if (priv->dma_enabled) {
dma_irq = platform_get_irq_byname(pdev, "dma");
if (dma_irq < 0) {
ret = dma_irq;
dev_err(dev, "no IRQ resource info\n");
ret = dev_err_probe(dev, dma_irq, "no IRQ resource info\n");
goto err1;
}
ret = devm_request_irq(dev, dma_irq, brcmuart_isr,
IRQF_SHARED, "uart DMA irq", &new_port->port);
if (ret) {
dev_err(dev, "unable to register IRQ handler\n");
dev_err_probe(dev, ret, "unable to register IRQ handler\n");
goto err1;
}
}
@ -1121,8 +1115,6 @@ err1:
serial8250_unregister_port(priv->line);
err:
brcmuart_free_bufs(dev, priv);
err_clk_disable:
clk_disable_unprepare(baud_mux_clk);
release_dma:
if (priv->dma_enabled)
brcmuart_arbitration(priv, 0);
@ -1137,7 +1129,6 @@ static int brcmuart_remove(struct platform_device *pdev)
hrtimer_cancel(&priv->hrt);
serial8250_unregister_port(priv->line);
brcmuart_free_bufs(&pdev->dev, priv);
clk_disable_unprepare(priv->baud_mux_clk);
if (priv->dma_enabled)
brcmuart_arbitration(priv, 0);
return 0;
@ -1154,10 +1145,10 @@ static int __maybe_unused brcmuart_suspend(struct device *dev)
* This will prevent resume from enabling RTS before the
* baud rate has been restored.
*/
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
priv->saved_mctrl = port->mctrl;
port->mctrl &= ~TIOCM_RTS;
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
serial8250_suspend_port(priv->line);
clk_disable_unprepare(priv->baud_mux_clk);
@ -1196,10 +1187,10 @@ static int __maybe_unused brcmuart_resume(struct device *dev)
if (priv->saved_mctrl & TIOCM_RTS) {
/* Restore RTS */
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
port->mctrl |= TIOCM_RTS;
port->ops->set_mctrl(port, port->mctrl);
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
}
return 0;

14
drivers/tty/serial/8250/8250_core.c
View File

@ -259,7 +259,7 @@ static void serial8250_backup_timeout(struct timer_list *t)
unsigned int iir, ier = 0, lsr;
unsigned long flags;
spin_lock_irqsave(&up->port.lock, flags);
uart_port_lock_irqsave(&up->port, &flags);
/*
* Must disable interrupts or else we risk racing with the interrupt
@ -292,7 +292,7 @@ static void serial8250_backup_timeout(struct timer_list *t)
if (up->port.irq)
serial_out(up, UART_IER, ier);
spin_unlock_irqrestore(&up->port.lock, flags);
uart_port_unlock_irqrestore(&up->port, flags);
/* Standard timer interval plus 0.2s to keep the port running */
mod_timer(&up->timer,
@ -611,7 +611,7 @@ static int univ8250_console_setup(struct console *co, char *options)
* if so, search for the first available port that does have
* console support.
*/
if (co->index >= UART_NR)
if (co->index < 0 || co->index >= UART_NR)
co->index = 0;
/*
@ -992,11 +992,11 @@ static void serial_8250_overrun_backoff_work(struct work_struct *work)
struct uart_port *port = &up->port;
unsigned long flags;
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
up->ier |= UART_IER_RLSI | UART_IER_RDI;
up->port.read_status_mask |= UART_LSR_DR;
serial_out(up, UART_IER, up->ier);
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
}
/**
@ -1194,9 +1194,9 @@ void serial8250_unregister_port(int line)
if (uart->em485) {
unsigned long flags;
spin_lock_irqsave(&uart->port.lock, flags);
uart_port_lock_irqsave(&uart->port, &flags);
serial8250_em485_destroy(uart);
spin_unlock_irqrestore(&uart->port.lock, flags);
uart_port_unlock_irqrestore(&uart->port, flags);
}
uart_remove_one_port(&serial8250_reg, &uart->port);

8
drivers/tty/serial/8250/8250_dma.c
View File

@ -22,7 +22,7 @@ static void __dma_tx_complete(void *param)
dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr,
UART_XMIT_SIZE, DMA_TO_DEVICE);
spin_lock_irqsave(&p->port.lock, flags);
uart_port_lock_irqsave(&p->port, &flags);
dma->tx_running = 0;
@ -35,7 +35,7 @@ static void __dma_tx_complete(void *param)
if (ret || !dma->tx_running)
serial8250_set_THRI(p);
spin_unlock_irqrestore(&p->port.lock, flags);
uart_port_unlock_irqrestore(&p->port, flags);
}
static void __dma_rx_complete(struct uart_8250_port *p)
@ -70,7 +70,7 @@ static void dma_rx_complete(void *param)
struct uart_8250_dma *dma = p->dma;
unsigned long flags;
spin_lock_irqsave(&p->port.lock, flags);
uart_port_lock_irqsave(&p->port, &flags);
if (dma->rx_running)
__dma_rx_complete(p);
@ -80,7 +80,7 @@ static void dma_rx_complete(void *param)
*/
if (!dma->rx_running && (serial_lsr_in(p) & UART_LSR_DR))
p->dma->rx_dma(p);
spin_unlock_irqrestore(&p->port.lock, flags);
uart_port_unlock_irqrestore(&p->port, flags);
}
int serial8250_tx_dma(struct uart_8250_port *p)

35
drivers/tty/serial/8250/8250_dw.c
View File

@ -263,20 +263,20 @@ static int dw8250_handle_irq(struct uart_port *p)
* so we limit the workaround only to non-DMA mode.
*/
if (!up->dma && rx_timeout) {
spin_lock_irqsave(&p->lock, flags);
uart_port_lock_irqsave(p, &flags);
status = serial_lsr_in(up);
if (!(status & (UART_LSR_DR | UART_LSR_BI)))
(void) p->serial_in(p, UART_RX);
spin_unlock_irqrestore(&p->lock, flags);
uart_port_unlock_irqrestore(p, flags);
}
/* Manually stop the Rx DMA transfer when acting as flow controller */
if (quirks & DW_UART_QUIRK_IS_DMA_FC && up->dma && up->dma->rx_running && rx_timeout) {
spin_lock_irqsave(&p->lock, flags);
uart_port_lock_irqsave(p, &flags);
status = serial_lsr_in(up);
spin_unlock_irqrestore(&p->lock, flags);
uart_port_unlock_irqrestore(p, flags);
if (status & (UART_LSR_DR | UART_LSR_BI)) {
dw8250_writel_ext(p, RZN1_UART_RDMACR, 0);
@ -498,11 +498,6 @@ static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data)
}
}
static void dw8250_clk_disable_unprepare(void *data)
{
clk_disable_unprepare(data);
}
static void dw8250_reset_control_assert(void *data)
{
reset_control_assert(data);
@ -598,23 +593,15 @@ static int dw8250_probe(struct platform_device *pdev)
device_property_read_u32(dev, "clock-frequency", &p->uartclk);
/* If there is separate baudclk, get the rate from it. */
data->clk = devm_clk_get_optional(dev, "baudclk");
data->clk = devm_clk_get_optional_enabled(dev, "baudclk");
if (data->clk == NULL)
data->clk = devm_clk_get_optional(dev, NULL);
data->clk = devm_clk_get_optional_enabled(dev, NULL);
if (IS_ERR(data->clk))
return PTR_ERR(data->clk);
INIT_WORK(&data->clk_work, dw8250_clk_work_cb);
data->clk_notifier.notifier_call = dw8250_clk_notifier_cb;
err = clk_prepare_enable(data->clk);
if (err)
return dev_err_probe(dev, err, "could not enable optional baudclk\n");
err = devm_add_action_or_reset(dev, dw8250_clk_disable_unprepare, data->clk);
if (err)
return err;
if (data->clk)
p->uartclk = clk_get_rate(data->clk);
@ -622,18 +609,10 @@ static int dw8250_probe(struct platform_device *pdev)
if (!p->uartclk)
return dev_err_probe(dev, -EINVAL, "clock rate not defined\n");
data->pclk = devm_clk_get_optional(dev, "apb_pclk");
data->pclk = devm_clk_get_optional_enabled(dev, "apb_pclk");
if (IS_ERR(data->pclk))
return PTR_ERR(data->pclk);
err = clk_prepare_enable(data->pclk);
if (err)
return dev_err_probe(dev, err, "could not enable apb_pclk\n");
err = devm_add_action_or_reset(dev, dw8250_clk_disable_unprepare, data->pclk);
if (err)
return err;
data->rst = devm_reset_control_get_optional_exclusive(dev, NULL);
if (IS_ERR(data->rst))
return PTR_ERR(data->rst);

63
drivers/tty/serial/8250/8250_exar.c
View File

@ -18,7 +18,6 @@
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/tty.h>
#include <linux/8250_pci.h>
#include <linux/delay.h>
#include <asm/byteorder.h>
@ -47,12 +46,6 @@
#define PCI_SUBDEVICE_ID_USR_2980 0x0128
#define PCI_SUBDEVICE_ID_USR_2981 0x0129
#define PCI_DEVICE_ID_SEALEVEL_710xC 0x1001
#define PCI_DEVICE_ID_SEALEVEL_720xC 0x1002
#define PCI_DEVICE_ID_SEALEVEL_740xC 0x1004
#define PCI_DEVICE_ID_SEALEVEL_780xC 0x1008
#define PCI_DEVICE_ID_SEALEVEL_716xC 0x1010
#define UART_EXAR_INT0 0x80
#define UART_EXAR_8XMODE 0x88 /* 8X sampling rate select */
#define UART_EXAR_SLEEP 0x8b /* Sleep mode */
@ -84,6 +77,9 @@
#define UART_EXAR_RS485_DLY(x) ((x) << 4)
#define UART_EXAR_DLD 0x02 /* Divisor Fractional */
#define UART_EXAR_DLD_485_POLARITY 0x80 /* RS-485 Enable Signal Polarity */
/*
* IOT2040 MPIO wiring semantics:
*
@ -201,9 +197,9 @@ static int xr17v35x_startup(struct uart_port *port)
*
* Synchronize UART_IER access against the console.
*/
spin_lock_irq(&port->lock);
uart_port_lock_irq(port);
serial_port_out(port, UART_IER, 0);
spin_unlock_irq(&port->lock);
uart_port_unlock_irq(port);
return serial8250_do_startup(port);
}
@ -445,6 +441,44 @@ static int generic_rs485_config(struct uart_port *port, struct ktermios *termios
return 0;
}
static int sealevel_rs485_config(struct uart_port *port, struct ktermios *termios,
struct serial_rs485 *rs485)
{
u8 __iomem *p = port->membase;
u8 old_lcr;
u8 efr;
u8 dld;
int ret;
ret = generic_rs485_config(port, termios, rs485);
if (ret)
return ret;
if (rs485->flags & SER_RS485_ENABLED) {
old_lcr = readb(p + UART_LCR);
/* Set EFR[4]=1 to enable enhanced feature registers */
efr = readb(p + UART_XR_EFR);
efr |= UART_EFR_ECB;
writeb(efr, p + UART_XR_EFR);
/* Set MCR to use DTR as Auto-RS485 Enable signal */
writeb(UART_MCR_OUT1, p + UART_MCR);
/* Set LCR[7]=1 to enable access to DLD register */
writeb(old_lcr | UART_LCR_DLAB, p + UART_LCR);
/* Set DLD[7]=1 for inverted RS485 Enable logic */
dld = readb(p + UART_EXAR_DLD);
dld |= UART_EXAR_DLD_485_POLARITY;
writeb(dld, p + UART_EXAR_DLD);
writeb(old_lcr, p + UART_LCR);
}
return 0;
}
static const struct serial_rs485 generic_rs485_supported = {
.flags = SER_RS485_ENABLED,
};
@ -566,6 +600,9 @@ pci_xr17v35x_setup(struct exar8250 *priv, struct pci_dev *pcidev,
port->port.rs485_config = platform->rs485_config;
port->port.rs485_supported = *(platform->rs485_supported);
if (pcidev->subsystem_vendor == PCI_VENDOR_ID_SEALEVEL)
port->port.rs485_config = sealevel_rs485_config;
/*
* Setup the UART clock for the devices on expansion slot to
* half the clock speed of the main chip (which is 125MHz)
@ -652,8 +689,6 @@ exar_pci_probe(struct pci_dev *pcidev, const struct pci_device_id *ent)
nr_ports = BIT(((pcidev->device & 0x38) >> 3) - 1);
else if (board->num_ports)
nr_ports = board->num_ports;
else if (pcidev->vendor == PCI_VENDOR_ID_SEALEVEL)
nr_ports = pcidev->device & 0xff;
else
nr_ports = pcidev->device & 0x0f;
@ -893,12 +928,6 @@ static const struct pci_device_id exar_pci_tbl[] = {
EXAR_DEVICE(COMMTECH, 4224PCI335, pbn_fastcom335_4),
EXAR_DEVICE(COMMTECH, 2324PCI335, pbn_fastcom335_4),
EXAR_DEVICE(COMMTECH, 2328PCI335, pbn_fastcom335_8),
EXAR_DEVICE(SEALEVEL, 710xC, pbn_exar_XR17V35x),
EXAR_DEVICE(SEALEVEL, 720xC, pbn_exar_XR17V35x),
EXAR_DEVICE(SEALEVEL, 740xC, pbn_exar_XR17V35x),
EXAR_DEVICE(SEALEVEL, 780xC, pbn_exar_XR17V35x),
EXAR_DEVICE(SEALEVEL, 716xC, pbn_exar_XR17V35x),
{ 0, }
};
MODULE_DEVICE_TABLE(pci, exar_pci_tbl);

6
drivers/tty/serial/8250/8250_fsl.c
View File

@ -30,11 +30,11 @@ int fsl8250_handle_irq(struct uart_port *port)
unsigned int iir;
struct uart_8250_port *up = up_to_u8250p(port);
spin_lock_irqsave(&up->port.lock, flags);
uart_port_lock_irqsave(&up->port, &flags);
iir = port->serial_in(port, UART_IIR);
if (iir & UART_IIR_NO_INT) {
spin_unlock_irqrestore(&up->port.lock, flags);
uart_port_unlock_irqrestore(&up->port, flags);
return 0;
}
@ -54,7 +54,7 @@ int fsl8250_handle_irq(struct uart_port *port)
if (unlikely(up->lsr_saved_flags & UART_LSR_BI)) {
up->lsr_saved_flags &= ~UART_LSR_BI;
port->serial_in(port, UART_RX);
spin_unlock_irqrestore(&up->port.lock, flags);
uart_port_unlock_irqrestore(&up->port, flags);
return 1;
}

18
drivers/tty/serial/8250/8250_mid.c
View File

@ -12,7 +12,6 @@
#include <linux/rational.h>
#include <linux/dma/hsu.h>
#include <linux/8250_pci.h>
#include "8250.h"
@ -32,9 +31,9 @@
struct mid8250;
struct mid8250_board {
unsigned int flags;
unsigned long freq;
unsigned int base_baud;
unsigned int bar;
int (*setup)(struct mid8250 *, struct uart_port *p);
void (*exit)(struct mid8250 *);
};
@ -169,7 +168,6 @@ static int dnv_setup(struct mid8250 *mid, struct uart_port *p)
{
struct hsu_dma_chip *chip = &mid->dma_chip;
struct pci_dev *pdev = to_pci_dev(p->dev);
unsigned int bar = FL_GET_BASE(mid->board->flags);
int ret;
pci_set_master(pdev);
@ -183,7 +181,7 @@ static int dnv_setup(struct mid8250 *mid, struct uart_port *p)
chip->dev = &pdev->dev;
chip->irq = pci_irq_vector(pdev, 0);
chip->regs = p->membase;
chip->length = pci_resource_len(pdev, bar);
chip->length = pci_resource_len(pdev, mid->board->bar);
chip->offset = DNV_DMA_CHAN_OFFSET;
/* Falling back to PIO mode if DMA probing fails */
@ -291,7 +289,6 @@ static int mid8250_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
struct uart_8250_port uart;
struct mid8250 *mid;
unsigned int bar;
int ret;
ret = pcim_enable_device(pdev);
@ -303,7 +300,6 @@ static int mid8250_probe(struct pci_dev *pdev, const struct pci_device_id *id)
return -ENOMEM;
mid->board = (struct mid8250_board *)id->driver_data;
bar = FL_GET_BASE(mid->board->flags);
memset(&uart, 0, sizeof(struct uart_8250_port));
@ -316,8 +312,8 @@ static int mid8250_probe(struct pci_dev *pdev, const struct pci_device_id *id)
uart.port.flags = UPF_SHARE_IRQ | UPF_FIXED_PORT | UPF_FIXED_TYPE;
uart.port.set_termios = mid8250_set_termios;
uart.port.mapbase = pci_resource_start(pdev, bar);
uart.port.membase = pcim_iomap(pdev, bar, 0);
uart.port.mapbase = pci_resource_start(pdev, mid->board->bar);
uart.port.membase = pcim_iomap(pdev, mid->board->bar, 0);
if (!uart.port.membase)
return -ENOMEM;
@ -353,25 +349,25 @@ static void mid8250_remove(struct pci_dev *pdev)
}
static const struct mid8250_board pnw_board = {
.flags = FL_BASE0,
.freq = 50000000,
.base_baud = 115200,
.bar = 0,
.setup = pnw_setup,
.exit = pnw_exit,
};
static const struct mid8250_board tng_board = {
.flags = FL_BASE0,
.freq = 38400000,
.base_baud = 1843200,
.bar = 0,
.setup = tng_setup,
.exit = tng_exit,
};
static const struct mid8250_board dnv_board = {
.flags = FL_BASE1,
.freq = 133333333,
.base_baud = 115200,
.bar = 1,
.setup = dnv_setup,
.exit = dnv_exit,
};

8
drivers/tty/serial/8250/8250_mtk.c
View File

@ -102,7 +102,7 @@ static void mtk8250_dma_rx_complete(void *param)
if (data->rx_status == DMA_RX_SHUTDOWN)
return;
spin_lock_irqsave(&up->port.lock, flags);
uart_port_lock_irqsave(&up->port, &flags);
dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state);
total = dma->rx_size - state.residue;
@ -128,7 +128,7 @@ static void mtk8250_dma_rx_complete(void *param)
mtk8250_rx_dma(up);
spin_unlock_irqrestore(&up->port.lock, flags);
uart_port_unlock_irqrestore(&up->port, flags);
}
static void mtk8250_rx_dma(struct uart_8250_port *up)
@ -368,7 +368,7 @@ mtk8250_set_termios(struct uart_port *port, struct ktermios *termios,
* Ok, we're now changing the port state. Do it with
* interrupts disabled.
*/
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
/*
* Update the per-port timeout.
@ -416,7 +416,7 @@ mtk8250_set_termios(struct uart_port *port, struct ktermios *termios,
if (uart_console(port))
up->port.cons->cflag = termios->c_cflag;
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
/* Don't rewrite B0 */
if (tty_termios_baud_rate(termios))
tty_termios_encode_baud_rate(termios, baud, baud);

44
drivers/tty/serial/8250/8250_of.c
View File

@ -33,7 +33,8 @@ static int of_platform_serial_setup(struct platform_device *ofdev,
struct of_serial_info *info)
{
struct resource resource;
struct device_node *np = ofdev->dev.of_node;
struct device *dev = &ofdev->dev;
struct device_node *np = dev->of_node;
struct uart_port *port = &up->port;
u32 clk, spd, prop;
int ret, irq;
@ -46,19 +47,12 @@ static int of_platform_serial_setup(struct platform_device *ofdev,
if (of_property_read_u32(np, "clock-frequency", &clk)) {
/* Get clk rate through clk driver if present */
info->clk = devm_clk_get(&ofdev->dev, NULL);
info->clk = devm_clk_get_enabled(dev, NULL);
if (IS_ERR(info->clk)) {
ret = PTR_ERR(info->clk);
if (ret != -EPROBE_DEFER)
dev_warn(&ofdev->dev,
"failed to get clock: %d\n", ret);
ret = dev_err_probe(dev, PTR_ERR(info->clk), "failed to get clock\n");
goto err_pmruntime;
}
ret = clk_prepare_enable(info->clk);
if (ret < 0)
goto err_pmruntime;
clk = clk_get_rate(info->clk);
}
/* If current-speed was set, then try not to change it. */
@ -67,8 +61,8 @@ static int of_platform_serial_setup(struct platform_device *ofdev,
ret = of_address_to_resource(np, 0, &resource);
if (ret) {
dev_warn(&ofdev->dev, "invalid address\n");
goto err_unprepare;
dev_err_probe(dev, ret, "invalid address\n");
goto err_pmruntime;
}
port->flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_FIXED_PORT |
@ -85,10 +79,9 @@ static int of_platform_serial_setup(struct platform_device *ofdev,
/* Check for shifted address mapping */
if (of_property_read_u32(np, "reg-offset", &prop) == 0) {
if (prop >= port->mapsize) {
dev_warn(&ofdev->dev, "reg-offset %u exceeds region size %pa\n",
prop, &port->mapsize);
ret = -EINVAL;
goto err_unprepare;
ret = dev_err_probe(dev, -EINVAL, "reg-offset %u exceeds region size %pa\n",
prop, &port->mapsize);
goto err_pmruntime;
}
port->mapbase += prop;
@ -109,10 +102,9 @@ static int of_platform_serial_setup(struct platform_device *ofdev,
UPIO_MEM32BE : UPIO_MEM32;
break;
default:
dev_warn(&ofdev->dev, "unsupported reg-io-width (%d)\n",
prop);
ret = -EINVAL;
goto err_unprepare;
ret = dev_err_probe(dev, -EINVAL, "unsupported reg-io-width (%u)\n",
prop);
goto err_pmruntime;
}
}
port->flags |= UPF_IOREMAP;
@ -139,7 +131,7 @@ static int of_platform_serial_setup(struct platform_device *ofdev,
if (irq < 0) {
if (irq == -EPROBE_DEFER) {
ret = -EPROBE_DEFER;
goto err_unprepare;
goto err_pmruntime;
}
/* IRQ support not mandatory */
irq = 0;
@ -150,12 +142,12 @@ static int of_platform_serial_setup(struct platform_device *ofdev,
info->rst = devm_reset_control_get_optional_shared(&ofdev->dev, NULL);
if (IS_ERR(info->rst)) {
ret = PTR_ERR(info->rst);
goto err_unprepare;
goto err_pmruntime;
}
ret = reset_control_deassert(info->rst);
if (ret)
goto err_unprepare;
goto err_pmruntime;
port->type = type;
port->uartclk = clk;
@ -173,7 +165,7 @@ static int of_platform_serial_setup(struct platform_device *ofdev,
case PORT_RT2880:
ret = rt288x_setup(port);
if (ret)
goto err_unprepare;
goto err_pmruntime;
break;
}
@ -185,8 +177,6 @@ static int of_platform_serial_setup(struct platform_device *ofdev,
}
return 0;
err_unprepare:
clk_disable_unprepare(info->clk);
err_pmruntime:
pm_runtime_put_sync(&ofdev->dev);
pm_runtime_disable(&ofdev->dev);
@ -253,7 +243,6 @@ err_dispose:
irq_dispose_mapping(port8250.port.irq);
pm_runtime_put_sync(&ofdev->dev);
pm_runtime_disable(&ofdev->dev);
clk_disable_unprepare(info->clk);
err_free:
kfree(info);
return ret;
@ -271,7 +260,6 @@ static int of_platform_serial_remove(struct platform_device *ofdev)
reset_control_assert(info->rst);
pm_runtime_put_sync(&ofdev->dev);
pm_runtime_disable(&ofdev->dev);
clk_disable_unprepare(info->clk);
kfree(info);
return 0;
}

114
drivers/tty/serial/8250/8250_omap.c
View File

@ -8,6 +8,7 @@
*
*/
#include <linux/atomic.h>
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/io.h>
@ -27,6 +28,7 @@
#include <linux/pm_wakeirq.h>
#include <linux/dma-mapping.h>
#include <linux/sys_soc.h>
#include <linux/pm_domain.h>
#include "8250.h"
@ -114,6 +116,12 @@
/* RX FIFO occupancy indicator */
#define UART_OMAP_RX_LVL 0x19
/*
* Copy of the genpd flags for the console.
* Only used if console suspend is disabled
*/
static unsigned int genpd_flags_console;
struct omap8250_priv {
void __iomem *membase;
int line;
@ -130,6 +138,7 @@ struct omap8250_priv {
u8 tx_trigger;
u8 rx_trigger;
atomic_t active;
bool is_suspending;
int wakeirq;
int wakeups_enabled;
@ -401,7 +410,7 @@ static void omap_8250_set_termios(struct uart_port *port,
* interrupts disabled.
*/
pm_runtime_get_sync(port->dev);
spin_lock_irq(&port->lock);
uart_port_lock_irq(port);
/*
* Update the per-port timeout.
@ -504,7 +513,7 @@ static void omap_8250_set_termios(struct uart_port *port,
}
omap8250_restore_regs(up);
spin_unlock_irq(&up->port.lock);
uart_port_unlock_irq(&up->port);
pm_runtime_mark_last_busy(port->dev);
pm_runtime_put_autosuspend(port->dev);
@ -529,7 +538,7 @@ static void omap_8250_pm(struct uart_port *port, unsigned int state,
pm_runtime_get_sync(port->dev);
/* Synchronize UART_IER access against the console. */
spin_lock_irq(&port->lock);
uart_port_lock_irq(port);
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
efr = serial_in(up, UART_EFR);
@ -541,7 +550,7 @@ static void omap_8250_pm(struct uart_port *port, unsigned int state,
serial_out(up, UART_EFR, efr);
serial_out(up, UART_LCR, 0);
spin_unlock_irq(&port->lock);
uart_port_unlock_irq(port);
pm_runtime_mark_last_busy(port->dev);
pm_runtime_put_autosuspend(port->dev);
@ -632,14 +641,23 @@ static irqreturn_t omap8250_irq(int irq, void *dev_id)
unsigned int iir, lsr;
int ret;
pm_runtime_get_noresume(port->dev);
/* Shallow idle state wake-up to an IO interrupt? */
if (atomic_add_unless(&priv->active, 1, 1)) {
priv->latency = priv->calc_latency;
schedule_work(&priv->qos_work);
}
#ifdef CONFIG_SERIAL_8250_DMA
if (up->dma) {
ret = omap_8250_dma_handle_irq(port);
pm_runtime_mark_last_busy(port->dev);
pm_runtime_put(port->dev);
return IRQ_RETVAL(ret);
}
#endif
serial8250_rpm_get(up);
lsr = serial_port_in(port, UART_LSR);
iir = serial_port_in(port, UART_IIR);
ret = serial8250_handle_irq(port, iir);
@ -660,7 +678,7 @@ static irqreturn_t omap8250_irq(int irq, void *dev_id)
unsigned long delay;
/* Synchronize UART_IER access against the console. */
spin_lock(&port->lock);
uart_port_lock(port);
up->ier = port->serial_in(port, UART_IER);
if (up->ier & (UART_IER_RLSI | UART_IER_RDI)) {
port->ops->stop_rx(port);
@ -670,13 +688,14 @@ static irqreturn_t omap8250_irq(int irq, void *dev_id)
*/
cancel_delayed_work(&up->overrun_backoff);
}
spin_unlock(&port->lock);
uart_port_unlock(port);
delay = msecs_to_jiffies(up->overrun_backoff_time_ms);
schedule_delayed_work(&up->overrun_backoff, delay);
}
serial8250_rpm_put(up);
pm_runtime_mark_last_busy(port->dev);
pm_runtime_put(port->dev);
return IRQ_RETVAL(ret);
}
@ -717,10 +736,10 @@ static int omap_8250_startup(struct uart_port *port)
}
/* Synchronize UART_IER access against the console. */
spin_lock_irq(&port->lock);
uart_port_lock_irq(port);
up->ier = UART_IER_RLSI | UART_IER_RDI;
serial_out(up, UART_IER, up->ier);
spin_unlock_irq(&port->lock);
uart_port_unlock_irq(port);
#ifdef CONFIG_PM
up->capabilities |= UART_CAP_RPM;
@ -733,9 +752,9 @@ static int omap_8250_startup(struct uart_port *port)
serial_out(up, UART_OMAP_WER, priv->wer);
if (up->dma && !(priv->habit & UART_HAS_EFR2)) {
spin_lock_irq(&port->lock);
uart_port_lock_irq(port);
up->dma->rx_dma(up);
spin_unlock_irq(&port->lock);
uart_port_unlock_irq(port);
}
enable_irq(up->port.irq);
@ -761,10 +780,10 @@ static void omap_8250_shutdown(struct uart_port *port)
serial_out(up, UART_OMAP_EFR2, 0x0);
/* Synchronize UART_IER access against the console. */
spin_lock_irq(&port->lock);
uart_port_lock_irq(port);
up->ier = 0;
serial_out(up, UART_IER, 0);
spin_unlock_irq(&port->lock);
uart_port_unlock_irq(port);
disable_irq_nosync(up->port.irq);
dev_pm_clear_wake_irq(port->dev);
@ -789,10 +808,10 @@ static void omap_8250_throttle(struct uart_port *port)
pm_runtime_get_sync(port->dev);
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
port->ops->stop_rx(port);
priv->throttled = true;
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
pm_runtime_mark_last_busy(port->dev);
pm_runtime_put_autosuspend(port->dev);
@ -807,14 +826,14 @@ static void omap_8250_unthrottle(struct uart_port *port)
pm_runtime_get_sync(port->dev);
/* Synchronize UART_IER access against the console. */
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
priv->throttled = false;
if (up->dma)
up->dma->rx_dma(up);
up->ier |= UART_IER_RLSI | UART_IER_RDI;
port->read_status_mask |= UART_LSR_DR;
serial_out(up, UART_IER, up->ier);
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
pm_runtime_mark_last_busy(port->dev);
pm_runtime_put_autosuspend(port->dev);
@ -958,7 +977,7 @@ static void __dma_rx_complete(void *param)
unsigned long flags;
/* Synchronize UART_IER access against the console. */
spin_lock_irqsave(&p->port.lock, flags);
uart_port_lock_irqsave(&p->port, &flags);
/*
* If the tx status is not DMA_COMPLETE, then this is a delayed
@ -967,7 +986,7 @@ static void __dma_rx_complete(void *param)
*/
if (dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state) !=
DMA_COMPLETE) {
spin_unlock_irqrestore(&p->port.lock, flags);
uart_port_unlock_irqrestore(&p->port, flags);
return;
}
__dma_rx_do_complete(p);
@ -978,7 +997,7 @@ static void __dma_rx_complete(void *param)
omap_8250_rx_dma(p);
}
spin_unlock_irqrestore(&p->port.lock, flags);
uart_port_unlock_irqrestore(&p->port, flags);
}
static void omap_8250_rx_dma_flush(struct uart_8250_port *p)
@ -1083,7 +1102,7 @@ static void omap_8250_dma_tx_complete(void *param)
dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr,
UART_XMIT_SIZE, DMA_TO_DEVICE);
spin_lock_irqsave(&p->port.lock, flags);
uart_port_lock_irqsave(&p->port, &flags);
dma->tx_running = 0;
@ -1112,7 +1131,7 @@ static void omap_8250_dma_tx_complete(void *param)
serial8250_set_THRI(p);
}
spin_unlock_irqrestore(&p->port.lock, flags);
uart_port_unlock_irqrestore(&p->port, flags);
}
static int omap_8250_tx_dma(struct uart_8250_port *p)
@ -1270,15 +1289,12 @@ static int omap_8250_dma_handle_irq(struct uart_port *port)
u16 status;
u8 iir;
serial8250_rpm_get(up);
iir = serial_port_in(port, UART_IIR);
if (iir & UART_IIR_NO_INT) {
serial8250_rpm_put(up);
return IRQ_HANDLED;
}
spin_lock(&port->lock);
uart_port_lock(port);
status = serial_port_in(port, UART_LSR);
@ -1305,7 +1321,6 @@ static int omap_8250_dma_handle_irq(struct uart_port *port)
uart_unlock_and_check_sysrq(port);
serial8250_rpm_put(up);
return 1;
}
@ -1503,8 +1518,6 @@ static int omap8250_probe(struct platform_device *pdev)
if (!of_get_available_child_count(pdev->dev.of_node))
pm_runtime_set_autosuspend_delay(&pdev->dev, -1);
pm_runtime_irq_safe(&pdev->dev);
pm_runtime_get_sync(&pdev->dev);
omap_serial_fill_features_erratas(&up, priv);
@ -1617,6 +1630,7 @@ static int omap8250_suspend(struct device *dev)
{
struct omap8250_priv *priv = dev_get_drvdata(dev);
struct uart_8250_port *up = serial8250_get_port(priv->line);
struct generic_pm_domain *genpd = pd_to_genpd(dev->pm_domain);
int err = 0;
serial8250_suspend_port(priv->line);
@ -1627,8 +1641,19 @@ static int omap8250_suspend(struct device *dev)
if (!device_may_wakeup(dev))
priv->wer = 0;
serial_out(up, UART_OMAP_WER, priv->wer);
if (uart_console(&up->port) && console_suspend_enabled)
err = pm_runtime_force_suspend(dev);
if (uart_console(&up->port)) {
if (console_suspend_enabled)
err = pm_runtime_force_suspend(dev);
else {
/*
* The pd shall not be powered-off (no console suspend).
* Make copy of genpd flags before to set it always on.
* The original value is restored during the resume.
*/
genpd_flags_console = genpd->flags;
genpd->flags |= GENPD_FLAG_ALWAYS_ON;
}
}
flush_work(&priv->qos_work);
return err;
@ -1638,12 +1663,16 @@ static int omap8250_resume(struct device *dev)
{
struct omap8250_priv *priv = dev_get_drvdata(dev);
struct uart_8250_port *up = serial8250_get_port(priv->line);
struct generic_pm_domain *genpd = pd_to_genpd(dev->pm_domain);
int err;
if (uart_console(&up->port) && console_suspend_enabled) {
err = pm_runtime_force_resume(dev);
if (err)
return err;
if (console_suspend_enabled) {
err = pm_runtime_force_resume(dev);
if (err)
return err;
} else
genpd->flags = genpd_flags_console;
}
serial8250_resume_port(priv->line);
@ -1743,6 +1772,7 @@ static int omap8250_runtime_suspend(struct device *dev)
priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
schedule_work(&priv->qos_work);
atomic_set(&priv->active, 0);
return 0;
}
@ -1752,23 +1782,29 @@ static int omap8250_runtime_resume(struct device *dev)
struct omap8250_priv *priv = dev_get_drvdata(dev);
struct uart_8250_port *up = NULL;
/* Did the hardware wake to a device IO interrupt before a wakeirq? */
if (atomic_read(&priv->active))
return 0;
if (priv->line >= 0)
up = serial8250_get_port(priv->line);
if (up && omap8250_lost_context(up)) {
spin_lock_irq(&up->port.lock);
uart_port_lock_irq(&up->port);
omap8250_restore_regs(up);
spin_unlock_irq(&up->port.lock);
uart_port_unlock_irq(&up->port);
}
if (up && up->dma && up->dma->rxchan && !(priv->habit & UART_HAS_EFR2)) {
spin_lock_irq(&up->port.lock);
uart_port_lock_irq(&up->port);
omap_8250_rx_dma(up);
spin_unlock_irq(&up->port.lock);
uart_port_unlock_irq(&up->port);
}
atomic_set(&priv->active, 1);
priv->latency = priv->calc_latency;
schedule_work(&priv->qos_work);
return 0;
}

597
drivers/tty/serial/8250/8250_pci.c
View File

@ -26,6 +26,84 @@
#include "8250.h"
#include "8250_pcilib.h"
#define PCI_VENDOR_ID_SBSMODULARIO 0x124B
#define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
#define PCI_DEVICE_ID_OCTPRO 0x0001
#define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
#define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
#define PCI_SUBDEVICE_ID_POCTAL232 0x0308
#define PCI_SUBDEVICE_ID_POCTAL422 0x0408
#define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
#define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
#define PCI_VENDOR_ID_ADVANTECH 0x13fe
#define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
#define PCI_DEVICE_ID_ADVANTECH_PCI1600 0x1600
#define PCI_DEVICE_ID_ADVANTECH_PCI1600_1611 0x1611
#define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
#define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
#define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
#define PCI_DEVICE_ID_TITAN_200I 0x8028
#define PCI_DEVICE_ID_TITAN_400I 0x8048
#define PCI_DEVICE_ID_TITAN_800I 0x8088
#define PCI_DEVICE_ID_TITAN_800EH 0xA007
#define PCI_DEVICE_ID_TITAN_800EHB 0xA008
#define PCI_DEVICE_ID_TITAN_400EH 0xA009
#define PCI_DEVICE_ID_TITAN_100E 0xA010
#define PCI_DEVICE_ID_TITAN_200E 0xA012
#define PCI_DEVICE_ID_TITAN_400E 0xA013
#define PCI_DEVICE_ID_TITAN_800E 0xA014
#define PCI_DEVICE_ID_TITAN_200EI 0xA016
#define PCI_DEVICE_ID_TITAN_200EISI 0xA017
#define PCI_DEVICE_ID_TITAN_200V3 0xA306
#define PCI_DEVICE_ID_TITAN_400V3 0xA310
#define PCI_DEVICE_ID_TITAN_410V3 0xA312
#define PCI_DEVICE_ID_TITAN_800V3 0xA314
#define PCI_DEVICE_ID_TITAN_800V3B 0xA315
#define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
#define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
#define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
#define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
#define PCI_VENDOR_ID_WCH 0x4348
#define PCI_DEVICE_ID_WCH_CH352_2S 0x3253
#define PCI_DEVICE_ID_WCH_CH353_4S 0x3453
#define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046
#define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053
#define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053
#define PCI_DEVICE_ID_WCH_CH355_4S 0x7173
#define PCI_VENDOR_ID_AGESTAR 0x5372
#define PCI_DEVICE_ID_AGESTAR_9375 0x6872
#define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
#define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
#define PCIE_VENDOR_ID_WCH 0x1c00
#define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250
#define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470
#define PCIE_DEVICE_ID_WCH_CH384_8S 0x3853
#define PCIE_DEVICE_ID_WCH_CH382_2S 0x3253
#define PCI_DEVICE_ID_MOXA_CP102E 0x1024
#define PCI_DEVICE_ID_MOXA_CP102EL 0x1025
#define PCI_DEVICE_ID_MOXA_CP102N 0x1027
#define PCI_DEVICE_ID_MOXA_CP104EL_A 0x1045
#define PCI_DEVICE_ID_MOXA_CP104N 0x1046
#define PCI_DEVICE_ID_MOXA_CP112N 0x1121
#define PCI_DEVICE_ID_MOXA_CP114EL 0x1144
#define PCI_DEVICE_ID_MOXA_CP114N 0x1145
#define PCI_DEVICE_ID_MOXA_CP116E_A_A 0x1160
#define PCI_DEVICE_ID_MOXA_CP116E_A_B 0x1161
#define PCI_DEVICE_ID_MOXA_CP118EL_A 0x1182
#define PCI_DEVICE_ID_MOXA_CP118E_A_I 0x1183
#define PCI_DEVICE_ID_MOXA_CP132EL 0x1322
#define PCI_DEVICE_ID_MOXA_CP132N 0x1323
#define PCI_DEVICE_ID_MOXA_CP134EL_A 0x1342
#define PCI_DEVICE_ID_MOXA_CP134N 0x1343
#define PCI_DEVICE_ID_MOXA_CP138E_A 0x1381
#define PCI_DEVICE_ID_MOXA_CP168EL_A 0x1683
/* Unknown vendors/cards - this should not be in linux/pci_ids.h */
#define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
#define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
/*
* init function returns:
* > 0 - number of ports
@ -1887,6 +1965,49 @@ pci_sunix_setup(struct serial_private *priv,
return setup_port(priv, port, bar, offset, 0);
}
#define MOXA_PUART_GPIO_EN 0x09
#define MOXA_PUART_GPIO_OUT 0x0A
#define MOXA_GPIO_PIN2 BIT(2)
static bool pci_moxa_is_mini_pcie(unsigned short device)
{
if (device == PCI_DEVICE_ID_MOXA_CP102N ||
device == PCI_DEVICE_ID_MOXA_CP104N ||
device == PCI_DEVICE_ID_MOXA_CP112N ||
device == PCI_DEVICE_ID_MOXA_CP114N ||
device == PCI_DEVICE_ID_MOXA_CP132N ||
device == PCI_DEVICE_ID_MOXA_CP134N)
return true;
return false;
}
static int pci_moxa_init(struct pci_dev *dev)
{
unsigned short device = dev->device;
resource_size_t iobar_addr = pci_resource_start(dev, 2);
unsigned int num_ports = (device & 0x00F0) >> 4;
u8 val;
/*
* Enable hardware buffer to prevent break signal output when system boots up.
* This hardware buffer is only supported on Mini PCIe series.
*/
if (pci_moxa_is_mini_pcie(device)) {
/* Set GPIO direction */
val = inb(iobar_addr + MOXA_PUART_GPIO_EN);
val |= MOXA_GPIO_PIN2;
outb(val, iobar_addr + MOXA_PUART_GPIO_EN);
/* Enable low GPIO */
val = inb(iobar_addr + MOXA_PUART_GPIO_OUT);
val &= ~MOXA_GPIO_PIN2;
outb(val, iobar_addr + MOXA_PUART_GPIO_OUT);
}
return num_ports;
}
static int
pci_moxa_setup(struct serial_private *priv,
const struct pciserial_board *board,
@ -1903,78 +2024,6 @@ pci_moxa_setup(struct serial_private *priv,
return setup_port(priv, port, bar, offset, 0);
}
#define PCI_VENDOR_ID_SBSMODULARIO 0x124B
#define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
#define PCI_DEVICE_ID_OCTPRO 0x0001
#define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
#define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
#define PCI_SUBDEVICE_ID_POCTAL232 0x0308
#define PCI_SUBDEVICE_ID_POCTAL422 0x0408
#define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
#define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
#define PCI_VENDOR_ID_ADVANTECH 0x13fe
#define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
#define PCI_DEVICE_ID_ADVANTECH_PCI1600 0x1600
#define PCI_DEVICE_ID_ADVANTECH_PCI1600_1611 0x1611
#define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
#define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
#define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
#define PCI_DEVICE_ID_TITAN_200I 0x8028
#define PCI_DEVICE_ID_TITAN_400I 0x8048
#define PCI_DEVICE_ID_TITAN_800I 0x8088
#define PCI_DEVICE_ID_TITAN_800EH 0xA007
#define PCI_DEVICE_ID_TITAN_800EHB 0xA008
#define PCI_DEVICE_ID_TITAN_400EH 0xA009
#define PCI_DEVICE_ID_TITAN_100E 0xA010
#define PCI_DEVICE_ID_TITAN_200E 0xA012
#define PCI_DEVICE_ID_TITAN_400E 0xA013
#define PCI_DEVICE_ID_TITAN_800E 0xA014
#define PCI_DEVICE_ID_TITAN_200EI 0xA016
#define PCI_DEVICE_ID_TITAN_200EISI 0xA017
#define PCI_DEVICE_ID_TITAN_200V3 0xA306
#define PCI_DEVICE_ID_TITAN_400V3 0xA310
#define PCI_DEVICE_ID_TITAN_410V3 0xA312
#define PCI_DEVICE_ID_TITAN_800V3 0xA314
#define PCI_DEVICE_ID_TITAN_800V3B 0xA315
#define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
#define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
#define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
#define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
#define PCI_VENDOR_ID_WCH 0x4348
#define PCI_DEVICE_ID_WCH_CH352_2S 0x3253
#define PCI_DEVICE_ID_WCH_CH353_4S 0x3453
#define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046
#define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053
#define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053
#define PCI_DEVICE_ID_WCH_CH355_4S 0x7173
#define PCI_VENDOR_ID_AGESTAR 0x5372
#define PCI_DEVICE_ID_AGESTAR_9375 0x6872
#define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
#define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
#define PCIE_VENDOR_ID_WCH 0x1c00
#define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250
#define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470
#define PCIE_DEVICE_ID_WCH_CH384_8S 0x3853
#define PCIE_DEVICE_ID_WCH_CH382_2S 0x3253
#define PCI_DEVICE_ID_MOXA_CP102E 0x1024
#define PCI_DEVICE_ID_MOXA_CP102EL 0x1025
#define PCI_DEVICE_ID_MOXA_CP104EL_A 0x1045
#define PCI_DEVICE_ID_MOXA_CP114EL 0x1144
#define PCI_DEVICE_ID_MOXA_CP116E_A_A 0x1160
#define PCI_DEVICE_ID_MOXA_CP116E_A_B 0x1161
#define PCI_DEVICE_ID_MOXA_CP118EL_A 0x1182
#define PCI_DEVICE_ID_MOXA_CP118E_A_I 0x1183
#define PCI_DEVICE_ID_MOXA_CP132EL 0x1322
#define PCI_DEVICE_ID_MOXA_CP134EL_A 0x1342
#define PCI_DEVICE_ID_MOXA_CP138E_A 0x1381
#define PCI_DEVICE_ID_MOXA_CP168EL_A 0x1683
/* Unknown vendors/cards - this should not be in linux/pci_ids.h */
#define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
#define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
/*
* Master list of serial port init/setup/exit quirks.
* This does not describe the general nature of the port.
@ -2429,6 +2478,153 @@ static struct pci_serial_quirk pci_serial_quirks[] = {
.init = pci_oxsemi_tornado_init,
.setup = pci_oxsemi_tornado_setup,
},
/*
* Brainboxes devices - all Oxsemi based
*/
{
.vendor = PCI_VENDOR_ID_INTASHIELD,
.device = 0x4027,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.init = pci_oxsemi_tornado_init,
.setup = pci_oxsemi_tornado_setup,
},
{
.vendor = PCI_VENDOR_ID_INTASHIELD,
.device = 0x4028,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.init = pci_oxsemi_tornado_init,
.setup = pci_oxsemi_tornado_setup,
},
{
.vendor = PCI_VENDOR_ID_INTASHIELD,
.device = 0x4029,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.init = pci_oxsemi_tornado_init,
.setup = pci_oxsemi_tornado_setup,
},
{
.vendor = PCI_VENDOR_ID_INTASHIELD,
.device = 0x4019,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.init = pci_oxsemi_tornado_init,
.setup = pci_oxsemi_tornado_setup,
},
{
.vendor = PCI_VENDOR_ID_INTASHIELD,
.device = 0x4016,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.init = pci_oxsemi_tornado_init,
.setup = pci_oxsemi_tornado_setup,
},
{
.vendor = PCI_VENDOR_ID_INTASHIELD,
.device = 0x4015,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.init = pci_oxsemi_tornado_init,
.setup = pci_oxsemi_tornado_setup,
},
{
.vendor = PCI_VENDOR_ID_INTASHIELD,
.device = 0x400A,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.init = pci_oxsemi_tornado_init,
.setup = pci_oxsemi_tornado_setup,
},
{
.vendor = PCI_VENDOR_ID_INTASHIELD,
.device = 0x400E,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.init = pci_oxsemi_tornado_init,
.setup = pci_oxsemi_tornado_setup,
},
{
.vendor = PCI_VENDOR_ID_INTASHIELD,
.device = 0x400C,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.init = pci_oxsemi_tornado_init,
.setup = pci_oxsemi_tornado_setup,
},
{
.vendor = PCI_VENDOR_ID_INTASHIELD,
.device = 0x400B,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.init = pci_oxsemi_tornado_init,
.setup = pci_oxsemi_tornado_setup,
},
{
.vendor = PCI_VENDOR_ID_INTASHIELD,
.device = 0x400F,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.init = pci_oxsemi_tornado_init,
.setup = pci_oxsemi_tornado_setup,
},
{
.vendor = PCI_VENDOR_ID_INTASHIELD,
.device = 0x4010,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.init = pci_oxsemi_tornado_init,
.setup = pci_oxsemi_tornado_setup,
},
{
.vendor = PCI_VENDOR_ID_INTASHIELD,
.device = 0x4011,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.init = pci_oxsemi_tornado_init,
.setup = pci_oxsemi_tornado_setup,
},
{
.vendor = PCI_VENDOR_ID_INTASHIELD,
.device = 0x401D,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.init = pci_oxsemi_tornado_init,
.setup = pci_oxsemi_tornado_setup,
},
{
.vendor = PCI_VENDOR_ID_INTASHIELD,
.device = 0x401E,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.init = pci_oxsemi_tornado_init,
.setup = pci_oxsemi_tornado_setup,
},
{
.vendor = PCI_VENDOR_ID_INTASHIELD,
.device = 0x4013,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.init = pci_oxsemi_tornado_init,
.setup = pci_oxsemi_tornado_setup,
},
{
.vendor = PCI_VENDOR_ID_INTASHIELD,
.device = 0x4017,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.init = pci_oxsemi_tornado_init,
.setup = pci_oxsemi_tornado_setup,
},
{
.vendor = PCI_VENDOR_ID_INTASHIELD,
.device = 0x4018,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.init = pci_oxsemi_tornado_init,
.setup = pci_oxsemi_tornado_setup,
},
{
.vendor = PCI_VENDOR_ID_INTEL,
.device = 0x8811,
@ -2635,6 +2831,7 @@ static struct pci_serial_quirk pci_serial_quirks[] = {
.device = PCI_ANY_ID,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.init = pci_moxa_init,
.setup = pci_moxa_setup,
},
{
@ -2854,9 +3051,9 @@ enum pci_board_num_t {
pbn_titan_2_4000000,
pbn_titan_4_4000000,
pbn_titan_8_4000000,
pbn_moxa8250_2p,
pbn_moxa8250_4p,
pbn_moxa8250_8p,
pbn_moxa_2,
pbn_moxa_4,
pbn_moxa_8,
};
/*
@ -3628,19 +3825,19 @@ static struct pciserial_board pci_boards[] = {
.uart_offset = 0x200,
.first_offset = 0x1000,
},
[pbn_moxa8250_2p] = {
[pbn_moxa_2] = {
.flags = FL_BASE1,
.num_ports = 2,
.base_baud = 921600,
.uart_offset = 0x200,
},
[pbn_moxa8250_4p] = {
[pbn_moxa_4] = {
.flags = FL_BASE1,
.num_ports = 4,
.base_baud = 921600,
.uart_offset = 0x200,
},
[pbn_moxa8250_8p] = {
[pbn_moxa_8] = {
.flags = FL_BASE1,
.num_ports = 8,
.base_baud = 921600,
@ -4913,11 +5110,17 @@ static const struct pci_device_id serial_pci_tbl[] = {
0, 0,
pbn_b1_bt_1_115200 },
/*
* IntaShield IS-100
*/
{ PCI_VENDOR_ID_INTASHIELD, 0x0D60,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b2_1_115200 },
/*
* IntaShield IS-200
*/
{ PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0d80 */
pbn_b2_2_115200 },
/*
* IntaShield IS-400
@ -4925,6 +5128,27 @@ static const struct pci_device_id serial_pci_tbl[] = {
{ PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
pbn_b2_4_115200 },
/*
* IntaShield IX-100
*/
{ PCI_VENDOR_ID_INTASHIELD, 0x4027,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_oxsemi_1_15625000 },
/*
* IntaShield IX-200
*/
{ PCI_VENDOR_ID_INTASHIELD, 0x4028,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_oxsemi_2_15625000 },
/*
* IntaShield IX-400
*/
{ PCI_VENDOR_ID_INTASHIELD, 0x4029,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_oxsemi_4_15625000 },
/* Brainboxes Devices */
/*
* Brainboxes UC-101
@ -4940,10 +5164,14 @@ static const struct pci_device_id serial_pci_tbl[] = {
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_b2_1_115200 },
{ PCI_VENDOR_ID_INTASHIELD, 0x0AA2,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_b2_1_115200 },
/*
* Brainboxes UC-257
* Brainboxes UC-253/UC-734
*/
{ PCI_VENDOR_ID_INTASHIELD, 0x0861,
{ PCI_VENDOR_ID_INTASHIELD, 0x0CA1,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_b2_2_115200 },
@ -4979,6 +5207,14 @@ static const struct pci_device_id serial_pci_tbl[] = {
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_b2_2_115200 },
{ PCI_VENDOR_ID_INTASHIELD, 0x08E2,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_b2_2_115200 },
{ PCI_VENDOR_ID_INTASHIELD, 0x08E3,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_b2_2_115200 },
/*
* Brainboxes UC-310
*/
@ -4989,6 +5225,14 @@ static const struct pci_device_id serial_pci_tbl[] = {
/*
* Brainboxes UC-313
*/
{ PCI_VENDOR_ID_INTASHIELD, 0x08A1,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_b2_2_115200 },
{ PCI_VENDOR_ID_INTASHIELD, 0x08A2,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_b2_2_115200 },
{ PCI_VENDOR_ID_INTASHIELD, 0x08A3,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
@ -5003,6 +5247,10 @@ static const struct pci_device_id serial_pci_tbl[] = {
/*
* Brainboxes UC-346
*/
{ PCI_VENDOR_ID_INTASHIELD, 0x0B01,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_b2_4_115200 },
{ PCI_VENDOR_ID_INTASHIELD, 0x0B02,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
@ -5014,6 +5262,10 @@ static const struct pci_device_id serial_pci_tbl[] = {
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_b2_2_115200 },
{ PCI_VENDOR_ID_INTASHIELD, 0x0A82,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_b2_2_115200 },
{ PCI_VENDOR_ID_INTASHIELD, 0x0A83,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
@ -5026,12 +5278,94 @@ static const struct pci_device_id serial_pci_tbl[] = {
0, 0,
pbn_b2_4_115200 },
/*
* Brainboxes UC-420/431
* Brainboxes UC-420
*/
{ PCI_VENDOR_ID_INTASHIELD, 0x0921,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_b2_4_115200 },
/*
* Brainboxes UC-607
*/
{ PCI_VENDOR_ID_INTASHIELD, 0x09A1,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_b2_2_115200 },
{ PCI_VENDOR_ID_INTASHIELD, 0x09A2,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_b2_2_115200 },
{ PCI_VENDOR_ID_INTASHIELD, 0x09A3,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_b2_2_115200 },
/*
* Brainboxes UC-836
*/
{ PCI_VENDOR_ID_INTASHIELD, 0x0D41,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_b2_4_115200 },
/*
* Brainboxes UP-189
*/
{ PCI_VENDOR_ID_INTASHIELD, 0x0AC1,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_b2_2_115200 },
{ PCI_VENDOR_ID_INTASHIELD, 0x0AC2,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_b2_2_115200 },
{ PCI_VENDOR_ID_INTASHIELD, 0x0AC3,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_b2_2_115200 },
/*
* Brainboxes UP-200
*/
{ PCI_VENDOR_ID_INTASHIELD, 0x0B21,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_b2_2_115200 },
{ PCI_VENDOR_ID_INTASHIELD, 0x0B22,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_b2_2_115200 },
{ PCI_VENDOR_ID_INTASHIELD, 0x0B23,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_b2_2_115200 },
/*
* Brainboxes UP-869
*/
{ PCI_VENDOR_ID_INTASHIELD, 0x0C01,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_b2_2_115200 },
{ PCI_VENDOR_ID_INTASHIELD, 0x0C02,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_b2_2_115200 },
{ PCI_VENDOR_ID_INTASHIELD, 0x0C03,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_b2_2_115200 },
/*
* Brainboxes UP-880
*/
{ PCI_VENDOR_ID_INTASHIELD, 0x0C21,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_b2_2_115200 },
{ PCI_VENDOR_ID_INTASHIELD, 0x0C22,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_b2_2_115200 },
{ PCI_VENDOR_ID_INTASHIELD, 0x0C23,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_b2_2_115200 },
/*
* Brainboxes PX-101
*/
@ -5064,7 +5398,7 @@ static const struct pci_device_id serial_pci_tbl[] = {
{ PCI_VENDOR_ID_INTASHIELD, 0x4015,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_oxsemi_4_15625000 },
pbn_oxsemi_2_15625000 },
/*
* Brainboxes PX-260/PX-701
*/
@ -5072,6 +5406,13 @@ static const struct pci_device_id serial_pci_tbl[] = {
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_oxsemi_4_15625000 },
/*
* Brainboxes PX-275/279
*/
{ PCI_VENDOR_ID_INTASHIELD, 0x0E41,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_b2_8_115200 },
/*
* Brainboxes PX-310
*/
@ -5119,18 +5460,40 @@ static const struct pci_device_id serial_pci_tbl[] = {
0, 0,
pbn_oxsemi_4_15625000 },
/*
* Brainboxes PX-803
* Brainboxes PX-475
*/
{ PCI_VENDOR_ID_INTASHIELD, 0x4009,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_b0_1_115200 },
{ PCI_VENDOR_ID_INTASHIELD, 0x401E,
{ PCI_VENDOR_ID_INTASHIELD, 0x401D,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_oxsemi_1_15625000 },
/*
* Brainboxes PX-846
* Brainboxes PX-803/PX-857
*/
{ PCI_VENDOR_ID_INTASHIELD, 0x4009,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_b0_2_115200 },
{ PCI_VENDOR_ID_INTASHIELD, 0x4018,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_oxsemi_2_15625000 },
{ PCI_VENDOR_ID_INTASHIELD, 0x401E,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_oxsemi_2_15625000 },
/*
* Brainboxes PX-820
*/
{ PCI_VENDOR_ID_INTASHIELD, 0x4002,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_b0_4_115200 },
{ PCI_VENDOR_ID_INTASHIELD, 0x4013,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_oxsemi_4_15625000 },
/*
* Brainboxes PX-835/PX-846
*/
{ PCI_VENDOR_ID_INTASHIELD, 0x4008,
PCI_ANY_ID, PCI_ANY_ID,
@ -5349,42 +5712,24 @@ static const struct pci_device_id serial_pci_tbl[] = {
/*
* MOXA
*/
{ PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102E,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_moxa8250_2p },
{ PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102EL,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_moxa8250_2p },
{ PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP104EL_A,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_moxa8250_4p },
{ PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP114EL,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_moxa8250_4p },
{ PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_A,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_moxa8250_8p },
{ PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_B,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_moxa8250_8p },
{ PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118EL_A,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_moxa8250_8p },
{ PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118E_A_I,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_moxa8250_8p },
{ PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP132EL,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_moxa8250_2p },
{ PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP134EL_A,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_moxa8250_4p },
{ PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP138E_A,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_moxa8250_8p },
{ PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP168EL_A,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_moxa8250_8p },
{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102E), pbn_moxa_2 },
{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102EL), pbn_moxa_2 },
{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102N), pbn_moxa_2 },
{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104EL_A), pbn_moxa_4 },
{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104N), pbn_moxa_4 },
{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP112N), pbn_moxa_2 },
{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114EL), pbn_moxa_4 },
{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114N), pbn_moxa_4 },
{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_A), pbn_moxa_8 },
{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_B), pbn_moxa_8 },
{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118EL_A), pbn_moxa_8 },
{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118E_A_I), pbn_moxa_8 },
{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132EL), pbn_moxa_2 },
{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132N), pbn_moxa_2 },
{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134EL_A), pbn_moxa_4 },
{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134N), pbn_moxa_4 },
{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP138E_A), pbn_moxa_8 },
{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168EL_A), pbn_moxa_8 },
/*
* ADDI-DATA GmbH communication cards <info@addi-data.com>

10
drivers/tty/serial/8250/8250_pci1xxxx.c
View File

@ -107,7 +107,7 @@ static const int logical_to_physical_port_idx[][MAX_PORTS] = {
struct pci1xxxx_8250 {
unsigned int nr;
void __iomem *membase;
int line[];
int line[] __counted_by(nr);
};
static int pci1xxxx_get_num_ports(struct pci_dev *dev)
@ -225,10 +225,10 @@ static bool pci1xxxx_port_suspend(int line)
if (port->suspended == 0 && port->dev) {
wakeup_mask = readb(up->port.membase + UART_WAKE_MASK_REG);
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
port->mctrl &= ~TIOCM_OUT2;
port->ops->set_mctrl(port, port->mctrl);
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
ret = (wakeup_mask & UART_WAKE_SRCS) != UART_WAKE_SRCS;
}
@ -251,10 +251,10 @@ static void pci1xxxx_port_resume(int line)
writeb(UART_WAKE_SRCS, port->membase + UART_WAKE_REG);
if (port->suspended == 0) {
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
port->mctrl |= TIOCM_OUT2;
port->ops->set_mctrl(port, port->mctrl);
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
}
mutex_unlock(&tport->mutex);
}

111
drivers/tty/serial/8250/8250_port.c
View File

@ -689,7 +689,7 @@ static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
if (p->capabilities & UART_CAP_SLEEP) {
/* Synchronize UART_IER access against the console. */
spin_lock_irq(&p->port.lock);
uart_port_lock_irq(&p->port);
if (p->capabilities & UART_CAP_EFR) {
lcr = serial_in(p, UART_LCR);
efr = serial_in(p, UART_EFR);
@ -703,7 +703,7 @@ static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
serial_out(p, UART_EFR, efr);
serial_out(p, UART_LCR, lcr);
}
spin_unlock_irq(&p->port.lock);
uart_port_unlock_irq(&p->port);
}
serial8250_rpm_put(p);
@ -746,9 +746,9 @@ static void enable_rsa(struct uart_8250_port *up)
{
if (up->port.type == PORT_RSA) {
if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
spin_lock_irq(&up->port.lock);
uart_port_lock_irq(&up->port);
__enable_rsa(up);
spin_unlock_irq(&up->port.lock);
uart_port_unlock_irq(&up->port);
}
if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
serial_out(up, UART_RSA_FRR, 0);
@ -768,7 +768,7 @@ static void disable_rsa(struct uart_8250_port *up)
if (up->port.type == PORT_RSA &&
up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
spin_lock_irq(&up->port.lock);
uart_port_lock_irq(&up->port);
mode = serial_in(up, UART_RSA_MSR);
result = !(mode & UART_RSA_MSR_FIFO);
@ -781,7 +781,7 @@ static void disable_rsa(struct uart_8250_port *up)
if (result)
up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
spin_unlock_irq(&up->port.lock);
uart_port_unlock_irq(&up->port);
}
}
#endif /* CONFIG_SERIAL_8250_RSA */
@ -1008,12 +1008,11 @@ static void autoconfig_16550a(struct uart_8250_port *up)
serial_out(up, UART_LCR, 0);
serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
UART_FCR7_64BYTE);
status1 = serial_in(up, UART_IIR) & (UART_IIR_64BYTE_FIFO |
UART_IIR_FIFO_ENABLED);
status1 = serial_in(up, UART_IIR) & UART_IIR_FIFO_ENABLED_16750;
serial_out(up, UART_FCR, 0);
serial_out(up, UART_LCR, 0);
if (status1 == (UART_IIR_64BYTE_FIFO | UART_IIR_FIFO_ENABLED))
if (status1 == UART_IIR_FIFO_ENABLED_16750)
up->port.type = PORT_16550A_FSL64;
else
DEBUG_AUTOCONF("Motorola 8xxx DUART ");
@ -1081,12 +1080,12 @@ static void autoconfig_16550a(struct uart_8250_port *up)
*/
serial_out(up, UART_LCR, 0);
serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
status1 = serial_in(up, UART_IIR) & (UART_IIR_64BYTE_FIFO | UART_IIR_FIFO_ENABLED);
status1 = serial_in(up, UART_IIR) & UART_IIR_FIFO_ENABLED_16750;
serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
status2 = serial_in(up, UART_IIR) & (UART_IIR_64BYTE_FIFO | UART_IIR_FIFO_ENABLED);
status2 = serial_in(up, UART_IIR) & UART_IIR_FIFO_ENABLED_16750;
serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
serial_out(up, UART_LCR, 0);
@ -1094,7 +1093,7 @@ static void autoconfig_16550a(struct uart_8250_port *up)
DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
if (status1 == UART_IIR_FIFO_ENABLED_16550A &&
status2 == (UART_IIR_64BYTE_FIFO | UART_IIR_FIFO_ENABLED_16550A)) {
status2 == UART_IIR_FIFO_ENABLED_16750) {
up->port.type = PORT_16750;
up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
return;
@ -1172,7 +1171,7 @@ static void autoconfig(struct uart_8250_port *up)
*
* Synchronize UART_IER access against the console.
*/
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
up->capabilities = 0;
up->bugs = 0;
@ -1211,7 +1210,7 @@ static void autoconfig(struct uart_8250_port *up)
/*
* We failed; there's nothing here
*/
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
scratch2, scratch3);
goto out;
@ -1235,7 +1234,7 @@ static void autoconfig(struct uart_8250_port *up)
status1 = serial_in(up, UART_MSR) & UART_MSR_STATUS_BITS;
serial8250_out_MCR(up, save_mcr);
if (status1 != (UART_MSR_DCD | UART_MSR_CTS)) {
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
DEBUG_AUTOCONF("LOOP test failed (%02x) ",
status1);
goto out;
@ -1304,7 +1303,7 @@ static void autoconfig(struct uart_8250_port *up)
serial8250_clear_IER(up);
out_unlock:
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
/*
* Check if the device is a Fintek F81216A
@ -1344,9 +1343,9 @@ static void autoconfig_irq(struct uart_8250_port *up)
probe_irq_off(probe_irq_on());
save_mcr = serial8250_in_MCR(up);
/* Synchronize UART_IER access against the console. */
spin_lock_irq(&port->lock);
uart_port_lock_irq(port);
save_ier = serial_in(up, UART_IER);
spin_unlock_irq(&port->lock);
uart_port_unlock_irq(port);
serial8250_out_MCR(up, UART_MCR_OUT1 | UART_MCR_OUT2);
irqs = probe_irq_on();
@ -1359,9 +1358,9 @@ static void autoconfig_irq(struct uart_8250_port *up)
UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
}
/* Synchronize UART_IER access against the console. */
spin_lock_irq(&port->lock);
uart_port_lock_irq(port);
serial_out(up, UART_IER, UART_IER_ALL_INTR);
spin_unlock_irq(&port->lock);
uart_port_unlock_irq(port);
serial_in(up, UART_LSR);
serial_in(up, UART_RX);
serial_in(up, UART_IIR);
@ -1372,9 +1371,9 @@ static void autoconfig_irq(struct uart_8250_port *up)
serial8250_out_MCR(up, save_mcr);
/* Synchronize UART_IER access against the console. */
spin_lock_irq(&port->lock);
uart_port_lock_irq(port);
serial_out(up, UART_IER, save_ier);
spin_unlock_irq(&port->lock);
uart_port_unlock_irq(port);
if (port->flags & UPF_FOURPORT)
outb_p(save_ICP, ICP);
@ -1442,13 +1441,13 @@ static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t)
unsigned long flags;
serial8250_rpm_get(p);
spin_lock_irqsave(&p->port.lock, flags);
uart_port_lock_irqsave(&p->port, &flags);
if (em485->active_timer == &em485->stop_tx_timer) {
p->rs485_stop_tx(p);
em485->active_timer = NULL;
em485->tx_stopped = true;
}
spin_unlock_irqrestore(&p->port.lock, flags);
uart_port_unlock_irqrestore(&p->port, flags);
serial8250_rpm_put(p);
return HRTIMER_NORESTART;
@ -1630,12 +1629,12 @@ static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t)
struct uart_8250_port *p = em485->port;
unsigned long flags;
spin_lock_irqsave(&p->port.lock, flags);
uart_port_lock_irqsave(&p->port, &flags);
if (em485->active_timer == &em485->start_tx_timer) {
__start_tx(&p->port);
em485->active_timer = NULL;
}
spin_unlock_irqrestore(&p->port.lock, flags);
uart_port_unlock_irqrestore(&p->port, flags);
return HRTIMER_NORESTART;
}
@ -1918,7 +1917,7 @@ int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
if (iir & UART_IIR_NO_INT)
return 0;
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
status = serial_lsr_in(up);
@ -1988,9 +1987,9 @@ static int serial8250_tx_threshold_handle_irq(struct uart_port *port)
if ((iir & UART_IIR_ID) == UART_IIR_THRI) {
struct uart_8250_port *up = up_to_u8250p(port);
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
serial8250_tx_chars(up);
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
}
iir = serial_port_in(port, UART_IIR);
@ -2005,10 +2004,10 @@ static unsigned int serial8250_tx_empty(struct uart_port *port)
serial8250_rpm_get(up);
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
if (!serial8250_tx_dma_running(up) && uart_lsr_tx_empty(serial_lsr_in(up)))
result = TIOCSER_TEMT;
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
serial8250_rpm_put(up);
@ -2070,13 +2069,13 @@ static void serial8250_break_ctl(struct uart_port *port, int break_state)
unsigned long flags;
serial8250_rpm_get(up);
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
if (break_state == -1)
up->lcr |= UART_LCR_SBC;
else
up->lcr &= ~UART_LCR_SBC;
serial_port_out(port, UART_LCR, up->lcr);
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
serial8250_rpm_put(up);
}
@ -2211,7 +2210,7 @@ int serial8250_do_startup(struct uart_port *port)
*
* Synchronize UART_IER access against the console.
*/
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
up->acr = 0;
serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
serial_port_out(port, UART_EFR, UART_EFR_ECB);
@ -2221,7 +2220,7 @@ int serial8250_do_startup(struct uart_port *port)
serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
serial_port_out(port, UART_EFR, UART_EFR_ECB);
serial_port_out(port, UART_LCR, 0);
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
}
if (port->type == PORT_DA830) {
@ -2230,10 +2229,10 @@ int serial8250_do_startup(struct uart_port *port)
*
* Synchronize UART_IER access against the console.
*/
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
serial_port_out(port, UART_IER, 0);
serial_port_out(port, UART_DA830_PWREMU_MGMT, 0);
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
mdelay(10);
/* Enable Tx, Rx and free run mode */
@ -2347,7 +2346,7 @@ int serial8250_do_startup(struct uart_port *port)
*
* Synchronize UART_IER access against the console.
*/
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
wait_for_xmitr(up, UART_LSR_THRE);
serial_port_out_sync(port, UART_IER, UART_IER_THRI);
@ -2359,7 +2358,7 @@ int serial8250_do_startup(struct uart_port *port)
iir = serial_port_in(port, UART_IIR);
serial_port_out(port, UART_IER, 0);
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
if (port->irqflags & IRQF_SHARED)
enable_irq(port->irq);
@ -2382,7 +2381,7 @@ int serial8250_do_startup(struct uart_port *port)
*/
serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
if (up->port.flags & UPF_FOURPORT) {
if (!up->port.irq)
up->port.mctrl |= TIOCM_OUT1;
@ -2428,7 +2427,7 @@ int serial8250_do_startup(struct uart_port *port)
}
dont_test_tx_en:
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
/*
* Clear the interrupt registers again for luck, and clear the
@ -2499,17 +2498,17 @@ void serial8250_do_shutdown(struct uart_port *port)
*
* Synchronize UART_IER access against the console.
*/
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
up->ier = 0;
serial_port_out(port, UART_IER, 0);
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
synchronize_irq(port->irq);
if (up->dma)
serial8250_release_dma(up);
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
if (port->flags & UPF_FOURPORT) {
/* reset interrupts on the AST Fourport board */
inb((port->iobase & 0xfe0) | 0x1f);
@ -2518,7 +2517,7 @@ void serial8250_do_shutdown(struct uart_port *port)
port->mctrl &= ~TIOCM_OUT2;
serial8250_set_mctrl(port, port->mctrl);
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
/*
* Disable break condition and FIFOs
@ -2754,14 +2753,14 @@ void serial8250_update_uartclk(struct uart_port *port, unsigned int uartclk)
quot = serial8250_get_divisor(port, baud, &frac);
serial8250_rpm_get(up);
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
uart_update_timeout(port, termios->c_cflag, baud);
serial8250_set_divisor(port, baud, quot, frac);
serial_port_out(port, UART_LCR, up->lcr);
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
serial8250_rpm_put(up);
out_unlock:
@ -2798,7 +2797,7 @@ serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
* Synchronize UART_IER access against the console.
*/
serial8250_rpm_get(up);
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
up->lcr = cval; /* Save computed LCR */
@ -2901,7 +2900,7 @@ serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
serial_port_out(port, UART_FCR, up->fcr); /* set fcr */
}
serial8250_set_mctrl(port, port->mctrl);
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
serial8250_rpm_put(up);
/* Don't rewrite B0 */
@ -2924,15 +2923,15 @@ void serial8250_do_set_ldisc(struct uart_port *port, struct ktermios *termios)
{
if (termios->c_line == N_PPS) {
port->flags |= UPF_HARDPPS_CD;
spin_lock_irq(&port->lock);
uart_port_lock_irq(port);
serial8250_enable_ms(port);
spin_unlock_irq(&port->lock);
uart_port_unlock_irq(port);
} else {
port->flags &= ~UPF_HARDPPS_CD;
if (!UART_ENABLE_MS(port, termios->c_cflag)) {
spin_lock_irq(&port->lock);
uart_port_lock_irq(port);
serial8250_disable_ms(port);
spin_unlock_irq(&port->lock);
uart_port_unlock_irq(port);
}
}
}
@ -3406,9 +3405,9 @@ void serial8250_console_write(struct uart_8250_port *up, const char *s,
touch_nmi_watchdog();
if (oops_in_progress)
locked = spin_trylock_irqsave(&port->lock, flags);
locked = uart_port_trylock_irqsave(port, &flags);
else
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
/*
* First save the IER then disable the interrupts
@ -3478,7 +3477,7 @@ void serial8250_console_write(struct uart_8250_port *up, const char *s,
serial8250_modem_status(up);
if (locked)
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
}
static unsigned int probe_baud(struct uart_port *port)

2
drivers/tty/serial/8250/Kconfig
View File

@ -148,7 +148,7 @@ config SERIAL_8250_PCI
config SERIAL_8250_EXAR
tristate "8250/16550 Exar/Commtech PCI/PCIe device support"
depends on SERIAL_8250_PCI
depends on SERIAL_8250 && PCI
default SERIAL_8250
help
This builds support for XR17C1xx, XR17V3xx and some Commtech

44
drivers/tty/serial/8250/Makefile
View File

@ -13,39 +13,41 @@ obj-$(CONFIG_SERIAL_8250) += 8250.o 8250_base.o
8250_base-$(CONFIG_SERIAL_8250_DWLIB) += 8250_dwlib.o
8250_base-$(CONFIG_SERIAL_8250_FINTEK) += 8250_fintek.o
8250_base-$(CONFIG_SERIAL_8250_PCILIB) += 8250_pcilib.o
obj-$(CONFIG_SERIAL_8250_PARISC) += 8250_parisc.o
obj-$(CONFIG_SERIAL_8250_PCI) += 8250_pci.o
obj-$(CONFIG_SERIAL_8250_EXAR) += 8250_exar.o
obj-$(CONFIG_SERIAL_8250_HP300) += 8250_hp300.o
obj-$(CONFIG_SERIAL_8250_CS) += serial_cs.o
obj-$(CONFIG_SERIAL_8250_CONSOLE) += 8250_early.o
obj-$(CONFIG_SERIAL_8250_ACCENT) += 8250_accent.o
obj-$(CONFIG_SERIAL_8250_ACORN) += 8250_acorn.o
obj-$(CONFIG_SERIAL_8250_ASPEED_VUART) += 8250_aspeed_vuart.o
obj-$(CONFIG_SERIAL_8250_BCM2835AUX) += 8250_bcm2835aux.o
obj-$(CONFIG_SERIAL_8250_CONSOLE) += 8250_early.o
obj-$(CONFIG_SERIAL_8250_FOURPORT) += 8250_fourport.o
obj-$(CONFIG_SERIAL_8250_ACCENT) += 8250_accent.o
obj-$(CONFIG_SERIAL_8250_BCM7271) += 8250_bcm7271.o
obj-$(CONFIG_SERIAL_8250_BOCA) += 8250_boca.o
obj-$(CONFIG_SERIAL_8250_EXAR_ST16C554) += 8250_exar_st16c554.o
obj-$(CONFIG_SERIAL_8250_HUB6) += 8250_hub6.o
obj-$(CONFIG_SERIAL_8250_PCI1XXXX) += 8250_pci1xxxx.o
obj-$(CONFIG_SERIAL_8250_FSL) += 8250_fsl.o
obj-$(CONFIG_SERIAL_8250_MEN_MCB) += 8250_men_mcb.o
obj-$(CONFIG_SERIAL_8250_DFL) += 8250_dfl.o
obj-$(CONFIG_SERIAL_8250_DW) += 8250_dw.o
obj-$(CONFIG_SERIAL_8250_EM) += 8250_em.o
obj-$(CONFIG_SERIAL_8250_IOC3) += 8250_ioc3.o
obj-$(CONFIG_SERIAL_8250_OMAP) += 8250_omap.o
obj-$(CONFIG_SERIAL_8250_RT288X) += 8250_rt288x.o
obj-$(CONFIG_SERIAL_8250_LPC18XX) += 8250_lpc18xx.o
obj-$(CONFIG_SERIAL_8250_MT6577) += 8250_mtk.o
obj-$(CONFIG_SERIAL_8250_UNIPHIER) += 8250_uniphier.o
obj-$(CONFIG_SERIAL_8250_EXAR) += 8250_exar.o
obj-$(CONFIG_SERIAL_8250_EXAR_ST16C554) += 8250_exar_st16c554.o
obj-$(CONFIG_SERIAL_8250_FOURPORT) += 8250_fourport.o
obj-$(CONFIG_SERIAL_8250_FSL) += 8250_fsl.o
obj-$(CONFIG_SERIAL_8250_HP300) += 8250_hp300.o
obj-$(CONFIG_SERIAL_8250_HUB6) += 8250_hub6.o
obj-$(CONFIG_SERIAL_8250_INGENIC) += 8250_ingenic.o
obj-$(CONFIG_SERIAL_8250_IOC3) += 8250_ioc3.o
obj-$(CONFIG_SERIAL_8250_LPC18XX) += 8250_lpc18xx.o
obj-$(CONFIG_SERIAL_8250_LPSS) += 8250_lpss.o
obj-$(CONFIG_SERIAL_8250_MEN_MCB) += 8250_men_mcb.o
obj-$(CONFIG_SERIAL_8250_MID) += 8250_mid.o
obj-$(CONFIG_SERIAL_8250_MT6577) += 8250_mtk.o
obj-$(CONFIG_SERIAL_OF_PLATFORM) += 8250_of.o
obj-$(CONFIG_SERIAL_8250_OMAP) += 8250_omap.o
obj-$(CONFIG_SERIAL_8250_PARISC) += 8250_parisc.o
obj-$(CONFIG_SERIAL_8250_PCI) += 8250_pci.o
obj-$(CONFIG_SERIAL_8250_PCI1XXXX) += 8250_pci1xxxx.o
obj-$(CONFIG_SERIAL_8250_PERICOM) += 8250_pericom.o
obj-$(CONFIG_SERIAL_8250_PXA) += 8250_pxa.o
obj-$(CONFIG_SERIAL_8250_RT288X) += 8250_rt288x.o
obj-$(CONFIG_SERIAL_8250_CS) += serial_cs.o
obj-$(CONFIG_SERIAL_8250_UNIPHIER) += 8250_uniphier.o
obj-$(CONFIG_SERIAL_8250_TEGRA) += 8250_tegra.o
obj-$(CONFIG_SERIAL_8250_BCM7271) += 8250_bcm7271.o
obj-$(CONFIG_SERIAL_OF_PLATFORM) += 8250_of.o
CFLAGS_8250_ingenic.o += -I$(srctree)/scripts/dtc/libfdt

26
drivers/tty/serial/Kconfig
View File

@ -1578,6 +1578,32 @@ config SERIAL_NUVOTON_MA35D1_CONSOLE
but you can alter that using a kernel command line option such as
"console=ttyNVTx".
config SERIAL_ESP32
tristate "Espressif ESP32 UART support"
depends on XTENSA_PLATFORM_ESP32 || (COMPILE_TEST && OF)
select SERIAL_CORE
select SERIAL_CORE_CONSOLE
select SERIAL_EARLYCON
help
Driver for the UART controllers of the Espressif ESP32xx SoCs.
When earlycon option is enabled the following kernel command line
snippets may be used:
earlycon=esp32s3uart,mmio32,0x60000000,115200n8,40000000
earlycon=esp32uart,mmio32,0x3ff40000,115200n8
config SERIAL_ESP32_ACM
tristate "Espressif ESP32 USB ACM gadget support"
depends on XTENSA_PLATFORM_ESP32 || (COMPILE_TEST && OF)
select SERIAL_CORE
select SERIAL_CORE_CONSOLE
select SERIAL_EARLYCON
help
Driver for the CDC ACM gadget controller of the Espressif ESP32S3
SoCs that share separate USB controller with the JTAG adapter.
When earlycon option is enabled the following kernel command line
snippet may be used:
earlycon=esp32s3acm,mmio32,0x60038000
endmenu
config SERIAL_MCTRL_GPIO

126
drivers/tty/serial/Makefile
View File

@ -24,70 +24,72 @@ obj-$(CONFIG_SERIAL_21285) += 21285.o
# Now bring in any enabled 8250/16450/16550 type drivers.
obj-y += 8250/
obj-$(CONFIG_SERIAL_AMBA_PL010) += amba-pl010.o
obj-$(CONFIG_SERIAL_AMBA_PL011) += amba-pl011.o
obj-$(CONFIG_SERIAL_CLPS711X) += clps711x.o
obj-$(CONFIG_SERIAL_PXA_NON8250) += pxa.o
obj-$(CONFIG_SERIAL_SA1100) += sa1100.o
obj-$(CONFIG_SERIAL_BCM63XX) += bcm63xx_uart.o
obj-$(CONFIG_SERIAL_SAMSUNG) += samsung_tty.o
obj-$(CONFIG_SERIAL_MAX3100) += max3100.o
obj-$(CONFIG_SERIAL_MAX310X) += max310x.o
obj-$(CONFIG_SERIAL_IP22_ZILOG) += ip22zilog.o
obj-$(CONFIG_SERIAL_MUX) += mux.o
obj-$(CONFIG_SERIAL_MCF) += mcf.o
obj-$(CONFIG_SERIAL_PMACZILOG) += pmac_zilog.o
obj-$(CONFIG_SERIAL_HS_LPC32XX) += lpc32xx_hs.o
obj-$(CONFIG_SERIAL_DZ) += dz.o
obj-$(CONFIG_SERIAL_ZS) += zs.o
obj-$(CONFIG_SERIAL_SH_SCI) += sh-sci.o
obj-$(CONFIG_SERIAL_CPM) += cpm_uart.o
obj-$(CONFIG_SERIAL_IMX) += imx.o
obj-$(CONFIG_SERIAL_IMX_EARLYCON) += imx_earlycon.o
obj-$(CONFIG_SERIAL_MPC52xx) += mpc52xx_uart.o
obj-$(CONFIG_SERIAL_ICOM) += icom.o
obj-$(CONFIG_SERIAL_MESON) += meson_uart.o
obj-$(CONFIG_SERIAL_SB1250_DUART) += sb1250-duart.o
obj-$(CONFIG_SERIAL_SCCNXP) += sccnxp.o
obj-$(CONFIG_SERIAL_SC16IS7XX_CORE) += sc16is7xx.o
obj-$(CONFIG_SERIAL_JSM) += jsm/
obj-$(CONFIG_SERIAL_TXX9) += serial_txx9.o
obj-$(CONFIG_SERIAL_ATMEL) += atmel_serial.o
obj-$(CONFIG_SERIAL_UARTLITE) += uartlite.o
obj-$(CONFIG_SERIAL_MSM) += msm_serial.o
obj-$(CONFIG_SERIAL_QCOM_GENI) += qcom_geni_serial.o
obj-$(CONFIG_SERIAL_OMAP) += omap-serial.o
obj-$(CONFIG_SERIAL_ALTERA_UART) += altera_uart.o
obj-$(CONFIG_SERIAL_ST_ASC) += st-asc.o
obj-$(CONFIG_SERIAL_QE) += ucc_uart.o
obj-$(CONFIG_SERIAL_TIMBERDALE) += timbuart.o
obj-$(CONFIG_SERIAL_ALTERA_JTAGUART) += altera_jtaguart.o
obj-$(CONFIG_SERIAL_ALTERA_UART) += altera_uart.o
obj-$(CONFIG_SERIAL_AMBA_PL010) += amba-pl010.o
obj-$(CONFIG_SERIAL_AMBA_PL011) += amba-pl011.o
obj-$(CONFIG_SERIAL_GRLIB_GAISLER_APBUART) += apbuart.o
obj-$(CONFIG_SERIAL_ALTERA_JTAGUART) += altera_jtaguart.o
obj-$(CONFIG_SERIAL_VT8500) += vt8500_serial.o
obj-$(CONFIG_SERIAL_PCH_UART) += pch_uart.o
obj-$(CONFIG_SERIAL_MXS_AUART) += mxs-auart.o
obj-$(CONFIG_SERIAL_LANTIQ) += lantiq.o
obj-$(CONFIG_SERIAL_XILINX_PS_UART) += xilinx_uartps.o
obj-$(CONFIG_SERIAL_TEGRA) += serial-tegra.o
obj-$(CONFIG_SERIAL_TEGRA_TCU) += tegra-tcu.o
obj-$(CONFIG_SERIAL_AR933X) += ar933x_uart.o
obj-$(CONFIG_SERIAL_ARC) += arc_uart.o
obj-$(CONFIG_SERIAL_RP2) += rp2.o
obj-$(CONFIG_SERIAL_FSL_LPUART) += fsl_lpuart.o
obj-$(CONFIG_SERIAL_FSL_LINFLEXUART) += fsl_linflexuart.o
obj-$(CONFIG_SERIAL_AR933X) += ar933x_uart.o
obj-$(CONFIG_SERIAL_ARC) += arc_uart.o
obj-$(CONFIG_SERIAL_ATMEL) += atmel_serial.o
obj-$(CONFIG_SERIAL_BCM63XX) += bcm63xx_uart.o
obj-$(CONFIG_SERIAL_CLPS711X) += clps711x.o
obj-$(CONFIG_SERIAL_CPM) += cpm_uart.o
obj-$(CONFIG_SERIAL_CONEXANT_DIGICOLOR) += digicolor-usart.o
obj-$(CONFIG_SERIAL_MEN_Z135) += men_z135_uart.o
obj-$(CONFIG_SERIAL_SPRD) += sprd_serial.o
obj-$(CONFIG_SERIAL_STM32) += stm32-usart.o
obj-$(CONFIG_SERIAL_MVEBU_UART) += mvebu-uart.o
obj-$(CONFIG_SERIAL_PIC32) += pic32_uart.o
obj-$(CONFIG_SERIAL_MPS2_UART) += mps2-uart.o
obj-$(CONFIG_SERIAL_OWL) += owl-uart.o
obj-$(CONFIG_SERIAL_RDA) += rda-uart.o
obj-$(CONFIG_SERIAL_MILBEAUT_USIO) += milbeaut_usio.o
obj-$(CONFIG_SERIAL_SIFIVE) += sifive.o
obj-$(CONFIG_SERIAL_LITEUART) += liteuart.o
obj-$(CONFIG_SERIAL_SUNPLUS) += sunplus-uart.o
obj-$(CONFIG_SERIAL_DZ) += dz.o
obj-$(CONFIG_SERIAL_ESP32) += esp32_uart.o
obj-$(CONFIG_SERIAL_ESP32_ACM) += esp32_acm.o
obj-$(CONFIG_SERIAL_FSL_LINFLEXUART) += fsl_linflexuart.o
obj-$(CONFIG_SERIAL_FSL_LPUART) += fsl_lpuart.o
obj-$(CONFIG_SERIAL_ICOM) += icom.o
obj-$(CONFIG_SERIAL_IMX) += imx.o
obj-$(CONFIG_SERIAL_IMX_EARLYCON) += imx_earlycon.o
obj-$(CONFIG_SERIAL_IP22_ZILOG) += ip22zilog.o
obj-$(CONFIG_SERIAL_JSM) += jsm/
obj-$(CONFIG_SERIAL_LANTIQ) += lantiq.o
obj-$(CONFIG_SERIAL_LITEUART) += liteuart.o
obj-$(CONFIG_SERIAL_HS_LPC32XX) += lpc32xx_hs.o
obj-$(CONFIG_SERIAL_MAX3100) += max3100.o
obj-$(CONFIG_SERIAL_MAX310X) += max310x.o
obj-$(CONFIG_SERIAL_MCF) += mcf.o
obj-$(CONFIG_SERIAL_MEN_Z135) += men_z135_uart.o
obj-$(CONFIG_SERIAL_MILBEAUT_USIO) += milbeaut_usio.o
obj-$(CONFIG_SERIAL_MESON) += meson_uart.o
obj-$(CONFIG_SERIAL_MPC52xx) += mpc52xx_uart.o
obj-$(CONFIG_SERIAL_MPS2_UART) += mps2-uart.o
obj-$(CONFIG_SERIAL_MSM) += msm_serial.o
obj-$(CONFIG_SERIAL_MUX) += mux.o
obj-$(CONFIG_SERIAL_MVEBU_UART) += mvebu-uart.o
obj-$(CONFIG_SERIAL_MXS_AUART) += mxs-auart.o
obj-$(CONFIG_SERIAL_OMAP) += omap-serial.o
obj-$(CONFIG_SERIAL_OWL) += owl-uart.o
obj-$(CONFIG_SERIAL_PCH_UART) += pch_uart.o
obj-$(CONFIG_SERIAL_PIC32) += pic32_uart.o
obj-$(CONFIG_SERIAL_PXA_NON8250) += pxa.o
obj-$(CONFIG_SERIAL_PMACZILOG) += pmac_zilog.o
obj-$(CONFIG_SERIAL_QCOM_GENI) += qcom_geni_serial.o
obj-$(CONFIG_SERIAL_QE) += ucc_uart.o
obj-$(CONFIG_SERIAL_RDA) += rda-uart.o
obj-$(CONFIG_SERIAL_RP2) += rp2.o
obj-$(CONFIG_SERIAL_SA1100) += sa1100.o
obj-$(CONFIG_SERIAL_SAMSUNG) += samsung_tty.o
obj-$(CONFIG_SERIAL_SB1250_DUART) += sb1250-duart.o
obj-$(CONFIG_SERIAL_SCCNXP) += sccnxp.o
obj-$(CONFIG_SERIAL_SC16IS7XX_CORE) += sc16is7xx.o
obj-$(CONFIG_SERIAL_SH_SCI) += sh-sci.o
obj-$(CONFIG_SERIAL_SIFIVE) += sifive.o
obj-$(CONFIG_SERIAL_SPRD) += sprd_serial.o
obj-$(CONFIG_SERIAL_ST_ASC) += st-asc.o
obj-$(CONFIG_SERIAL_STM32) += stm32-usart.o
obj-$(CONFIG_SERIAL_SUNPLUS) += sunplus-uart.o
obj-$(CONFIG_SERIAL_TEGRA) += serial-tegra.o
obj-$(CONFIG_SERIAL_TEGRA_TCU) += tegra-tcu.o
obj-$(CONFIG_SERIAL_TIMBERDALE) += timbuart.o
obj-$(CONFIG_SERIAL_TXX9) += serial_txx9.o
obj-$(CONFIG_SERIAL_UARTLITE) += uartlite.o
obj-$(CONFIG_SERIAL_VT8500) += vt8500_serial.o
obj-$(CONFIG_SERIAL_XILINX_PS_UART) += xilinx_uartps.o
obj-$(CONFIG_SERIAL_ZS) += zs.o
# GPIOLIB helpers for modem control lines
obj-$(CONFIG_SERIAL_MCTRL_GPIO) += serial_mctrl_gpio.o

28
drivers/tty/serial/altera_jtaguart.c
View File

@ -147,14 +147,14 @@ static irqreturn_t altera_jtaguart_interrupt(int irq, void *data)
isr = (readl(port->membase + ALTERA_JTAGUART_CONTROL_REG) >>
ALTERA_JTAGUART_CONTROL_RI_OFF) & port->read_status_mask;
spin_lock(&port->lock);
uart_port_lock(port);
if (isr & ALTERA_JTAGUART_CONTROL_RE_MSK)
altera_jtaguart_rx_chars(port);
if (isr & ALTERA_JTAGUART_CONTROL_WE_MSK)
altera_jtaguart_tx_chars(port);
spin_unlock(&port->lock);
uart_port_unlock(port);
return IRQ_RETVAL(isr);
}
@ -180,14 +180,14 @@ static int altera_jtaguart_startup(struct uart_port *port)
return ret;
}
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
/* Enable RX interrupts now */
port->read_status_mask = ALTERA_JTAGUART_CONTROL_RE_MSK;
writel(port->read_status_mask,
port->membase + ALTERA_JTAGUART_CONTROL_REG);
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
return 0;
}
@ -196,14 +196,14 @@ static void altera_jtaguart_shutdown(struct uart_port *port)
{
unsigned long flags;
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
/* Disable all interrupts now */
port->read_status_mask = 0;
writel(port->read_status_mask,
port->membase + ALTERA_JTAGUART_CONTROL_REG);
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
free_irq(port->irq, port);
}
@ -264,33 +264,33 @@ static void altera_jtaguart_console_putc(struct uart_port *port, unsigned char c
unsigned long flags;
u32 status;
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
while (!altera_jtaguart_tx_space(port, &status)) {
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
if ((status & ALTERA_JTAGUART_CONTROL_AC_MSK) == 0) {
return; /* no connection activity */
}
cpu_relax();
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
}
writel(c, port->membase + ALTERA_JTAGUART_DATA_REG);
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
}
#else
static void altera_jtaguart_console_putc(struct uart_port *port, unsigned char c)
{
unsigned long flags;
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
while (!altera_jtaguart_tx_space(port, NULL)) {
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
cpu_relax();
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
}
writel(c, port->membase + ALTERA_JTAGUART_DATA_REG);
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
}
#endif

20
drivers/tty/serial/altera_uart.c
View File

@ -164,13 +164,13 @@ static void altera_uart_break_ctl(struct uart_port *port, int break_state)
struct altera_uart *pp = container_of(port, struct altera_uart, port);
unsigned long flags;
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
if (break_state == -1)
pp->imr |= ALTERA_UART_CONTROL_TRBK_MSK;
else
pp->imr &= ~ALTERA_UART_CONTROL_TRBK_MSK;
altera_uart_update_ctrl_reg(pp);
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
}
static void altera_uart_set_termios(struct uart_port *port,
@ -187,10 +187,10 @@ static void altera_uart_set_termios(struct uart_port *port,
tty_termios_copy_hw(termios, old);
tty_termios_encode_baud_rate(termios, baud, baud);
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
uart_update_timeout(port, termios->c_cflag, baud);
altera_uart_writel(port, baudclk, ALTERA_UART_DIVISOR_REG);
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
/*
* FIXME: port->read_status_mask and port->ignore_status_mask
@ -264,12 +264,12 @@ static irqreturn_t altera_uart_interrupt(int irq, void *data)
isr = altera_uart_readl(port, ALTERA_UART_STATUS_REG) & pp->imr;
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
if (isr & ALTERA_UART_STATUS_RRDY_MSK)
altera_uart_rx_chars(port);
if (isr & ALTERA_UART_STATUS_TRDY_MSK)
altera_uart_tx_chars(port);
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
return IRQ_RETVAL(isr);
}
@ -313,13 +313,13 @@ static int altera_uart_startup(struct uart_port *port)
}
}
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
/* Enable RX interrupts now */
pp->imr = ALTERA_UART_CONTROL_RRDY_MSK;
altera_uart_update_ctrl_reg(pp);
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
return 0;
}
@ -329,13 +329,13 @@ static void altera_uart_shutdown(struct uart_port *port)
struct altera_uart *pp = container_of(port, struct altera_uart, port);
unsigned long flags;
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
/* Disable all interrupts now */
pp->imr = 0;
altera_uart_update_ctrl_reg(pp);
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
if (port->irq)
free_irq(port->irq, port);

20
drivers/tty/serial/amba-pl010.c
View File

@ -207,7 +207,7 @@ static irqreturn_t pl010_int(int irq, void *dev_id)
unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
int handled = 0;
spin_lock(&port->lock);
uart_port_lock(port);
status = readb(port->membase + UART010_IIR);
if (status) {
@ -228,7 +228,7 @@ static irqreturn_t pl010_int(int irq, void *dev_id)
handled = 1;
}
spin_unlock(&port->lock);
uart_port_unlock(port);
return IRQ_RETVAL(handled);
}
@ -270,14 +270,14 @@ static void pl010_break_ctl(struct uart_port *port, int break_state)
unsigned long flags;
unsigned int lcr_h;
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
lcr_h = readb(port->membase + UART010_LCRH);
if (break_state == -1)
lcr_h |= UART01x_LCRH_BRK;
else
lcr_h &= ~UART01x_LCRH_BRK;
writel(lcr_h, port->membase + UART010_LCRH);
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
}
static int pl010_startup(struct uart_port *port)
@ -385,7 +385,7 @@ pl010_set_termios(struct uart_port *port, struct ktermios *termios,
if (port->fifosize > 1)
lcr_h |= UART01x_LCRH_FEN;
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
/*
* Update the per-port timeout.
@ -438,22 +438,22 @@ pl010_set_termios(struct uart_port *port, struct ktermios *termios,
writel(lcr_h, port->membase + UART010_LCRH);
writel(old_cr, port->membase + UART010_CR);
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
}
static void pl010_set_ldisc(struct uart_port *port, struct ktermios *termios)
{
if (termios->c_line == N_PPS) {
port->flags |= UPF_HARDPPS_CD;
spin_lock_irq(&port->lock);
uart_port_lock_irq(port);
pl010_enable_ms(port);
spin_unlock_irq(&port->lock);
uart_port_unlock_irq(port);
} else {
port->flags &= ~UPF_HARDPPS_CD;
if (!UART_ENABLE_MS(port, termios->c_cflag)) {
spin_lock_irq(&port->lock);
uart_port_lock_irq(port);
pl010_disable_ms(port);
spin_unlock_irq(&port->lock);
uart_port_unlock_irq(port);
}
}
}

74
drivers/tty/serial/amba-pl011.c
View File

@ -345,9 +345,9 @@ static int pl011_fifo_to_tty(struct uart_amba_port *uap)
flag = TTY_FRAME;
}
spin_unlock(&uap->port.lock);
uart_port_unlock(&uap->port);
sysrq = uart_handle_sysrq_char(&uap->port, ch & 255);
spin_lock(&uap->port.lock);
uart_port_lock(&uap->port);
if (!sysrq)
uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
@ -421,7 +421,7 @@ static void pl011_dma_probe(struct uart_amba_port *uap)
/* We need platform data */
if (!plat || !plat->dma_filter) {
dev_info(uap->port.dev, "no DMA platform data\n");
dev_dbg(uap->port.dev, "no DMA platform data\n");
return;
}
@ -550,7 +550,7 @@ static void pl011_dma_tx_callback(void *data)
unsigned long flags;
u16 dmacr;
spin_lock_irqsave(&uap->port.lock, flags);
uart_port_lock_irqsave(&uap->port, &flags);
if (uap->dmatx.queued)
dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1,
DMA_TO_DEVICE);
@ -571,7 +571,7 @@ static void pl011_dma_tx_callback(void *data)
if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) ||
uart_circ_empty(&uap->port.state->xmit)) {
uap->dmatx.queued = false;
spin_unlock_irqrestore(&uap->port.lock, flags);
uart_port_unlock_irqrestore(&uap->port, flags);
return;
}
@ -582,7 +582,7 @@ static void pl011_dma_tx_callback(void *data)
*/
pl011_start_tx_pio(uap);
spin_unlock_irqrestore(&uap->port.lock, flags);
uart_port_unlock_irqrestore(&uap->port, flags);
}
/*
@ -1009,7 +1009,7 @@ static void pl011_dma_rx_callback(void *data)
* routine to flush out the secondary DMA buffer while
* we immediately trigger the next DMA job.
*/
spin_lock_irq(&uap->port.lock);
uart_port_lock_irq(&uap->port);
/*
* Rx data can be taken by the UART interrupts during
* the DMA irq handler. So we check the residue here.
@ -1025,7 +1025,7 @@ static void pl011_dma_rx_callback(void *data)
ret = pl011_dma_rx_trigger_dma(uap);
pl011_dma_rx_chars(uap, pending, lastbuf, false);
spin_unlock_irq(&uap->port.lock);
uart_port_unlock_irq(&uap->port);
/*
* Do this check after we picked the DMA chars so we don't
* get some IRQ immediately from RX.
@ -1091,11 +1091,11 @@ static void pl011_dma_rx_poll(struct timer_list *t)
if (jiffies_to_msecs(jiffies - dmarx->last_jiffies)
> uap->dmarx.poll_timeout) {
spin_lock_irqsave(&uap->port.lock, flags);
uart_port_lock_irqsave(&uap->port, &flags);
pl011_dma_rx_stop(uap);
uap->im |= UART011_RXIM;
pl011_write(uap->im, uap, REG_IMSC);
spin_unlock_irqrestore(&uap->port.lock, flags);
uart_port_unlock_irqrestore(&uap->port, flags);
uap->dmarx.running = false;
dmaengine_terminate_all(rxchan);
@ -1191,10 +1191,10 @@ static void pl011_dma_shutdown(struct uart_amba_port *uap)
while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy)
cpu_relax();
spin_lock_irq(&uap->port.lock);
uart_port_lock_irq(&uap->port);
uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE);
pl011_write(uap->dmacr, uap, REG_DMACR);
spin_unlock_irq(&uap->port.lock);
uart_port_unlock_irq(&uap->port);
if (uap->using_tx_dma) {
/* In theory, this should already be done by pl011_dma_flush_buffer */
@ -1374,9 +1374,9 @@ static void pl011_throttle_rx(struct uart_port *port)
{
unsigned long flags;
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
pl011_stop_rx(port);
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
}
static void pl011_enable_ms(struct uart_port *port)
@ -1394,7 +1394,7 @@ __acquires(&uap->port.lock)
{
pl011_fifo_to_tty(uap);
spin_unlock(&uap->port.lock);
uart_port_unlock(&uap->port);
tty_flip_buffer_push(&uap->port.state->port);
/*
* If we were temporarily out of DMA mode for a while,
@ -1419,7 +1419,7 @@ __acquires(&uap->port.lock)
#endif
}
}
spin_lock(&uap->port.lock);
uart_port_lock(&uap->port);
}
static bool pl011_tx_char(struct uart_amba_port *uap, unsigned char c,
@ -1555,7 +1555,7 @@ static irqreturn_t pl011_int(int irq, void *dev_id)
unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
int handled = 0;
spin_lock_irqsave(&uap->port.lock, flags);
uart_port_lock_irqsave(&uap->port, &flags);
status = pl011_read(uap, REG_RIS) & uap->im;
if (status) {
do {
@ -1585,7 +1585,7 @@ static irqreturn_t pl011_int(int irq, void *dev_id)
handled = 1;
}
spin_unlock_irqrestore(&uap->port.lock, flags);
uart_port_unlock_irqrestore(&uap->port, flags);
return IRQ_RETVAL(handled);
}
@ -1657,14 +1657,14 @@ static void pl011_break_ctl(struct uart_port *port, int break_state)
unsigned long flags;
unsigned int lcr_h;
spin_lock_irqsave(&uap->port.lock, flags);
uart_port_lock_irqsave(&uap->port, &flags);
lcr_h = pl011_read(uap, REG_LCRH_TX);
if (break_state == -1)
lcr_h |= UART01x_LCRH_BRK;
else
lcr_h &= ~UART01x_LCRH_BRK;
pl011_write(lcr_h, uap, REG_LCRH_TX);
spin_unlock_irqrestore(&uap->port.lock, flags);
uart_port_unlock_irqrestore(&uap->port, flags);
}
#ifdef CONFIG_CONSOLE_POLL
@ -1803,7 +1803,7 @@ static void pl011_enable_interrupts(struct uart_amba_port *uap)
unsigned long flags;
unsigned int i;
spin_lock_irqsave(&uap->port.lock, flags);
uart_port_lock_irqsave(&uap->port, &flags);
/* Clear out any spuriously appearing RX interrupts */
pl011_write(UART011_RTIS | UART011_RXIS, uap, REG_ICR);
@ -1825,7 +1825,7 @@ static void pl011_enable_interrupts(struct uart_amba_port *uap)
if (!pl011_dma_rx_running(uap))
uap->im |= UART011_RXIM;
pl011_write(uap->im, uap, REG_IMSC);
spin_unlock_irqrestore(&uap->port.lock, flags);
uart_port_unlock_irqrestore(&uap->port, flags);
}
static void pl011_unthrottle_rx(struct uart_port *port)
@ -1833,7 +1833,7 @@ static void pl011_unthrottle_rx(struct uart_port *port)
struct uart_amba_port *uap = container_of(port, struct uart_amba_port, port);
unsigned long flags;
spin_lock_irqsave(&uap->port.lock, flags);
uart_port_lock_irqsave(&uap->port, &flags);
uap->im = UART011_RTIM;
if (!pl011_dma_rx_running(uap))
@ -1841,7 +1841,7 @@ static void pl011_unthrottle_rx(struct uart_port *port)
pl011_write(uap->im, uap, REG_IMSC);
spin_unlock_irqrestore(&uap->port.lock, flags);
uart_port_unlock_irqrestore(&uap->port, flags);
}
static int pl011_startup(struct uart_port *port)
@ -1861,7 +1861,7 @@ static int pl011_startup(struct uart_port *port)
pl011_write(uap->vendor->ifls, uap, REG_IFLS);
spin_lock_irq(&uap->port.lock);
uart_port_lock_irq(&uap->port);
cr = pl011_read(uap, REG_CR);
cr &= UART011_CR_RTS | UART011_CR_DTR;
@ -1872,7 +1872,7 @@ static int pl011_startup(struct uart_port *port)
pl011_write(cr, uap, REG_CR);
spin_unlock_irq(&uap->port.lock);
uart_port_unlock_irq(&uap->port);
/*
* initialise the old status of the modem signals
@ -1933,12 +1933,12 @@ static void pl011_disable_uart(struct uart_amba_port *uap)
unsigned int cr;
uap->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
spin_lock_irq(&uap->port.lock);
uart_port_lock_irq(&uap->port);
cr = pl011_read(uap, REG_CR);
cr &= UART011_CR_RTS | UART011_CR_DTR;
cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
pl011_write(cr, uap, REG_CR);
spin_unlock_irq(&uap->port.lock);
uart_port_unlock_irq(&uap->port);
/*
* disable break condition and fifos
@ -1950,14 +1950,14 @@ static void pl011_disable_uart(struct uart_amba_port *uap)
static void pl011_disable_interrupts(struct uart_amba_port *uap)
{
spin_lock_irq(&uap->port.lock);
uart_port_lock_irq(&uap->port);
/* mask all interrupts and clear all pending ones */
uap->im = 0;
pl011_write(uap->im, uap, REG_IMSC);
pl011_write(0xffff, uap, REG_ICR);
spin_unlock_irq(&uap->port.lock);
uart_port_unlock_irq(&uap->port);
}
static void pl011_shutdown(struct uart_port *port)
@ -2102,7 +2102,7 @@ pl011_set_termios(struct uart_port *port, struct ktermios *termios,
bits = tty_get_frame_size(termios->c_cflag);
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
/*
* Update the per-port timeout.
@ -2176,7 +2176,7 @@ pl011_set_termios(struct uart_port *port, struct ktermios *termios,
old_cr |= UART011_CR_RXE;
pl011_write(old_cr, uap, REG_CR);
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
}
static void
@ -2194,10 +2194,10 @@ sbsa_uart_set_termios(struct uart_port *port, struct ktermios *termios,
termios->c_cflag &= ~(CMSPAR | CRTSCTS);
termios->c_cflag |= CS8 | CLOCAL;
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
uart_update_timeout(port, CS8, uap->fixed_baud);
pl011_setup_status_masks(port, termios);
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
}
static const char *pl011_type(struct uart_port *port)
@ -2336,9 +2336,9 @@ pl011_console_write(struct console *co, const char *s, unsigned int count)
if (uap->port.sysrq)
locked = 0;
else if (oops_in_progress)
locked = spin_trylock(&uap->port.lock);
locked = uart_port_trylock(&uap->port);
else
spin_lock(&uap->port.lock);
uart_port_lock(&uap->port);
/*
* First save the CR then disable the interrupts
@ -2364,7 +2364,7 @@ pl011_console_write(struct console *co, const char *s, unsigned int count)
pl011_write(old_cr, uap, REG_CR);
if (locked)
spin_unlock(&uap->port.lock);
uart_port_unlock(&uap->port);
local_irq_restore(flags);
clk_disable(uap->clk);

8
drivers/tty/serial/apbuart.c
View File

@ -133,7 +133,7 @@ static irqreturn_t apbuart_int(int irq, void *dev_id)
struct uart_port *port = dev_id;
unsigned int status;
spin_lock(&port->lock);
uart_port_lock(port);
status = UART_GET_STATUS(port);
if (status & UART_STATUS_DR)
@ -141,7 +141,7 @@ static irqreturn_t apbuart_int(int irq, void *dev_id)
if (status & UART_STATUS_THE)
apbuart_tx_chars(port);
spin_unlock(&port->lock);
uart_port_unlock(port);
return IRQ_HANDLED;
}
@ -228,7 +228,7 @@ static void apbuart_set_termios(struct uart_port *port,
if (termios->c_cflag & CRTSCTS)
cr |= UART_CTRL_FL;
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
/* Update the per-port timeout. */
uart_update_timeout(port, termios->c_cflag, baud);
@ -251,7 +251,7 @@ static void apbuart_set_termios(struct uart_port *port,
UART_PUT_SCAL(port, quot);
UART_PUT_CTRL(port, cr);
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
}
static const char *apbuart_type(struct uart_port *port)

26
drivers/tty/serial/ar933x_uart.c
View File

@ -133,9 +133,9 @@ static unsigned int ar933x_uart_tx_empty(struct uart_port *port)
unsigned long flags;
unsigned int rdata;
spin_lock_irqsave(&up->port.lock, flags);
uart_port_lock_irqsave(&up->port, &flags);
rdata = ar933x_uart_read(up, AR933X_UART_DATA_REG);
spin_unlock_irqrestore(&up->port.lock, flags);
uart_port_unlock_irqrestore(&up->port, flags);
return (rdata & AR933X_UART_DATA_TX_CSR) ? 0 : TIOCSER_TEMT;
}
@ -220,14 +220,14 @@ static void ar933x_uart_break_ctl(struct uart_port *port, int break_state)
container_of(port, struct ar933x_uart_port, port);
unsigned long flags;
spin_lock_irqsave(&up->port.lock, flags);
uart_port_lock_irqsave(&up->port, &flags);
if (break_state == -1)
ar933x_uart_rmw_set(up, AR933X_UART_CS_REG,
AR933X_UART_CS_TX_BREAK);
else
ar933x_uart_rmw_clear(up, AR933X_UART_CS_REG,
AR933X_UART_CS_TX_BREAK);
spin_unlock_irqrestore(&up->port.lock, flags);
uart_port_unlock_irqrestore(&up->port, flags);
}
/*
@ -318,7 +318,7 @@ static void ar933x_uart_set_termios(struct uart_port *port,
* Ok, we're now changing the port state. Do it with
* interrupts disabled.
*/
spin_lock_irqsave(&up->port.lock, flags);
uart_port_lock_irqsave(&up->port, &flags);
/* disable the UART */
ar933x_uart_rmw_clear(up, AR933X_UART_CS_REG,
@ -352,7 +352,7 @@ static void ar933x_uart_set_termios(struct uart_port *port,
AR933X_UART_CS_IF_MODE_M << AR933X_UART_CS_IF_MODE_S,
AR933X_UART_CS_IF_MODE_DCE << AR933X_UART_CS_IF_MODE_S);
spin_unlock_irqrestore(&up->port.lock, flags);
uart_port_unlock_irqrestore(&up->port, flags);
if (tty_termios_baud_rate(new))
tty_termios_encode_baud_rate(new, baud, baud);
@ -450,7 +450,7 @@ static irqreturn_t ar933x_uart_interrupt(int irq, void *dev_id)
if ((status & AR933X_UART_CS_HOST_INT) == 0)
return IRQ_NONE;
spin_lock(&up->port.lock);
uart_port_lock(&up->port);
status = ar933x_uart_read(up, AR933X_UART_INT_REG);
status &= ar933x_uart_read(up, AR933X_UART_INT_EN_REG);
@ -468,7 +468,7 @@ static irqreturn_t ar933x_uart_interrupt(int irq, void *dev_id)
ar933x_uart_tx_chars(up);
}
spin_unlock(&up->port.lock);
uart_port_unlock(&up->port);
return IRQ_HANDLED;
}
@ -485,7 +485,7 @@ static int ar933x_uart_startup(struct uart_port *port)
if (ret)
return ret;
spin_lock_irqsave(&up->port.lock, flags);
uart_port_lock_irqsave(&up->port, &flags);
/* Enable HOST interrupts */
ar933x_uart_rmw_set(up, AR933X_UART_CS_REG,
@ -498,7 +498,7 @@ static int ar933x_uart_startup(struct uart_port *port)
/* Enable RX interrupts */
ar933x_uart_start_rx_interrupt(up);
spin_unlock_irqrestore(&up->port.lock, flags);
uart_port_unlock_irqrestore(&up->port, flags);
return 0;
}
@ -632,9 +632,9 @@ static void ar933x_uart_console_write(struct console *co, const char *s,
if (up->port.sysrq)
locked = 0;
else if (oops_in_progress)
locked = spin_trylock(&up->port.lock);
locked = uart_port_trylock(&up->port);
else
spin_lock(&up->port.lock);
uart_port_lock(&up->port);
/*
* First save the IER then disable the interrupts
@ -654,7 +654,7 @@ static void ar933x_uart_console_write(struct console *co, const char *s,
ar933x_uart_write(up, AR933X_UART_INT_REG, AR933X_UART_INT_ALLINTS);
if (locked)
spin_unlock(&up->port.lock);
uart_port_unlock(&up->port);
local_irq_restore(flags);
}

16
drivers/tty/serial/arc_uart.c
View File

@ -279,9 +279,9 @@ static irqreturn_t arc_serial_isr(int irq, void *dev_id)
if (status & RXIENB) {
/* already in ISR, no need of xx_irqsave */
spin_lock(&port->lock);
uart_port_lock(port);
arc_serial_rx_chars(port, status);
spin_unlock(&port->lock);
uart_port_unlock(port);
}
if ((status & TXIENB) && (status & TXEMPTY)) {
@ -291,12 +291,12 @@ static irqreturn_t arc_serial_isr(int irq, void *dev_id)
*/
UART_TX_IRQ_DISABLE(port);
spin_lock(&port->lock);
uart_port_lock(port);
if (!uart_tx_stopped(port))
arc_serial_tx_chars(port);
spin_unlock(&port->lock);
uart_port_unlock(port);
}
return IRQ_HANDLED;
@ -366,7 +366,7 @@ arc_serial_set_termios(struct uart_port *port, struct ktermios *new,
uartl = hw_val & 0xFF;
uarth = (hw_val >> 8) & 0xFF;
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
UART_ALL_IRQ_DISABLE(port);
@ -391,7 +391,7 @@ arc_serial_set_termios(struct uart_port *port, struct ktermios *new,
uart_update_timeout(port, new->c_cflag, baud);
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
}
static const char *arc_serial_type(struct uart_port *port)
@ -521,9 +521,9 @@ static void arc_serial_console_write(struct console *co, const char *s,
struct uart_port *port = &arc_uart_ports[co->index].port;
unsigned long flags;
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
uart_console_write(port, s, count, arc_serial_console_putchar);
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
}
static struct console arc_console = {

24
drivers/tty/serial/atmel_serial.c
View File

@ -861,7 +861,7 @@ static void atmel_complete_tx_dma(void *arg)
struct dma_chan *chan = atmel_port->chan_tx;
unsigned long flags;
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
if (chan)
dmaengine_terminate_all(chan);
@ -893,7 +893,7 @@ static void atmel_complete_tx_dma(void *arg)
atmel_port->tx_done_mask);
}
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
}
static void atmel_release_tx_dma(struct uart_port *port)
@ -1711,9 +1711,9 @@ static void atmel_tasklet_rx_func(struct tasklet_struct *t)
struct uart_port *port = &atmel_port->uart;
/* The interrupt handler does not take the lock */
spin_lock(&port->lock);
uart_port_lock(port);
atmel_port->schedule_rx(port);
spin_unlock(&port->lock);
uart_port_unlock(port);
}
static void atmel_tasklet_tx_func(struct tasklet_struct *t)
@ -1723,9 +1723,9 @@ static void atmel_tasklet_tx_func(struct tasklet_struct *t)
struct uart_port *port = &atmel_port->uart;
/* The interrupt handler does not take the lock */
spin_lock(&port->lock);
uart_port_lock(port);
atmel_port->schedule_tx(port);
spin_unlock(&port->lock);
uart_port_unlock(port);
}
static void atmel_init_property(struct atmel_uart_port *atmel_port,
@ -2175,7 +2175,7 @@ static void atmel_set_termios(struct uart_port *port,
} else
mode |= ATMEL_US_PAR_NONE;
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
port->read_status_mask = ATMEL_US_OVRE;
if (termios->c_iflag & INPCK)
@ -2377,22 +2377,22 @@ gclk_fail:
else
atmel_disable_ms(port);
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
}
static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios)
{
if (termios->c_line == N_PPS) {
port->flags |= UPF_HARDPPS_CD;
spin_lock_irq(&port->lock);
uart_port_lock_irq(port);
atmel_enable_ms(port);
spin_unlock_irq(&port->lock);
uart_port_unlock_irq(port);
} else {
port->flags &= ~UPF_HARDPPS_CD;
if (!UART_ENABLE_MS(port, termios->c_cflag)) {
spin_lock_irq(&port->lock);
uart_port_lock_irq(port);
atmel_disable_ms(port);
spin_unlock_irq(&port->lock);
uart_port_unlock_irq(port);
}
}
}

22
drivers/tty/serial/bcm63xx_uart.c
View File

@ -201,7 +201,7 @@ static void bcm_uart_break_ctl(struct uart_port *port, int ctl)
unsigned long flags;
unsigned int val;
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
val = bcm_uart_readl(port, UART_CTL_REG);
if (ctl)
@ -210,7 +210,7 @@ static void bcm_uart_break_ctl(struct uart_port *port, int ctl)
val &= ~UART_CTL_XMITBRK_MASK;
bcm_uart_writel(port, val, UART_CTL_REG);
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
}
/*
@ -332,7 +332,7 @@ static irqreturn_t bcm_uart_interrupt(int irq, void *dev_id)
unsigned int irqstat;
port = dev_id;
spin_lock(&port->lock);
uart_port_lock(port);
irqstat = bcm_uart_readl(port, UART_IR_REG);
if (irqstat & UART_RX_INT_STAT)
@ -353,7 +353,7 @@ static irqreturn_t bcm_uart_interrupt(int irq, void *dev_id)
estat & UART_EXTINP_DCD_MASK);
}
spin_unlock(&port->lock);
uart_port_unlock(port);
return IRQ_HANDLED;
}
@ -451,9 +451,9 @@ static void bcm_uart_shutdown(struct uart_port *port)
{
unsigned long flags;
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
bcm_uart_writel(port, 0, UART_IR_REG);
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
bcm_uart_disable(port);
bcm_uart_flush(port);
@ -470,7 +470,7 @@ static void bcm_uart_set_termios(struct uart_port *port, struct ktermios *new,
unsigned long flags;
int tries;
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
/* Drain the hot tub fully before we power it off for the winter. */
for (tries = 3; !bcm_uart_tx_empty(port) && tries; tries--)
@ -546,7 +546,7 @@ static void bcm_uart_set_termios(struct uart_port *port, struct ktermios *new,
uart_update_timeout(port, new->c_cflag, baud);
bcm_uart_enable(port);
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
}
/*
@ -712,9 +712,9 @@ static void bcm_console_write(struct console *co, const char *s,
/* bcm_uart_interrupt() already took the lock */
locked = 0;
} else if (oops_in_progress) {
locked = spin_trylock(&port->lock);
locked = uart_port_trylock(port);
} else {
spin_lock(&port->lock);
uart_port_lock(port);
locked = 1;
}
@ -725,7 +725,7 @@ static void bcm_console_write(struct console *co, const char *s,
wait_for_xmitr(port);
if (locked)
spin_unlock(&port->lock);
uart_port_unlock(port);
local_irq_restore(flags);
}

8
drivers/tty/serial/cpm_uart.c
View File

@ -569,7 +569,7 @@ static void cpm_uart_set_termios(struct uart_port *port,
if ((termios->c_cflag & CREAD) == 0)
port->read_status_mask &= ~BD_SC_EMPTY;
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
if (IS_SMC(pinfo)) {
unsigned int bits = tty_get_frame_size(termios->c_cflag);
@ -609,7 +609,7 @@ static void cpm_uart_set_termios(struct uart_port *port,
clk_set_rate(pinfo->clk, baud);
else
cpm_setbrg(pinfo->brg - 1, baud);
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
}
static const char *cpm_uart_type(struct uart_port *port)
@ -1386,9 +1386,9 @@ static void cpm_uart_console_write(struct console *co, const char *s,
cpm_uart_early_write(pinfo, s, count, true);
local_irq_restore(flags);
} else {
spin_lock_irqsave(&pinfo->port.lock, flags);
uart_port_lock_irqsave(&pinfo->port, &flags);
cpm_uart_early_write(pinfo, s, count, true);
spin_unlock_irqrestore(&pinfo->port.lock, flags);
uart_port_unlock_irqrestore(&pinfo->port, flags);
}
}

18
drivers/tty/serial/digicolor-usart.c
View File

@ -133,7 +133,7 @@ static void digicolor_uart_rx(struct uart_port *port)
{
unsigned long flags;
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
while (1) {
u8 status, ch, ch_flag;
@ -172,7 +172,7 @@ static void digicolor_uart_rx(struct uart_port *port)
ch_flag);
}
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
tty_flip_buffer_push(&port->state->port);
}
@ -185,7 +185,7 @@ static void digicolor_uart_tx(struct uart_port *port)
if (digicolor_uart_tx_full(port))
return;
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
if (port->x_char) {
writeb_relaxed(port->x_char, port->membase + UA_EMI_REC);
@ -211,7 +211,7 @@ static void digicolor_uart_tx(struct uart_port *port)
uart_write_wakeup(port);
out:
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
}
static irqreturn_t digicolor_uart_int(int irq, void *dev_id)
@ -333,7 +333,7 @@ static void digicolor_uart_set_termios(struct uart_port *port,
port->ignore_status_mask |= UA_STATUS_OVERRUN_ERR
| UA_STATUS_PARITY_ERR | UA_STATUS_FRAME_ERR;
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
uart_update_timeout(port, termios->c_cflag, baud);
@ -341,7 +341,7 @@ static void digicolor_uart_set_termios(struct uart_port *port,
writeb_relaxed(divisor & 0xff, port->membase + UA_HBAUD_LO);
writeb_relaxed(divisor >> 8, port->membase + UA_HBAUD_HI);
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
}
static const char *digicolor_uart_type(struct uart_port *port)
@ -398,14 +398,14 @@ static void digicolor_uart_console_write(struct console *co, const char *c,
int locked = 1;
if (oops_in_progress)
locked = spin_trylock_irqsave(&port->lock, flags);
locked = uart_port_trylock_irqsave(port, &flags);
else
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
uart_console_write(port, c, n, digicolor_uart_console_putchar);
if (locked)
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
/* Wait for transmitter to become empty */
do {

32
drivers/tty/serial/dz.c
View File

@ -268,9 +268,9 @@ static inline void dz_transmit_chars(struct dz_mux *mux)
}
/* If nothing to do or stopped or hardware stopped. */
if (uart_circ_empty(xmit) || uart_tx_stopped(&dport->port)) {
spin_lock(&dport->port.lock);
uart_port_lock(&dport->port);
dz_stop_tx(&dport->port);
spin_unlock(&dport->port.lock);
uart_port_unlock(&dport->port);
return;
}
@ -287,9 +287,9 @@ static inline void dz_transmit_chars(struct dz_mux *mux)
/* Are we are done. */
if (uart_circ_empty(xmit)) {
spin_lock(&dport->port.lock);
uart_port_lock(&dport->port);
dz_stop_tx(&dport->port);
spin_unlock(&dport->port.lock);
uart_port_unlock(&dport->port);
}
}
@ -415,14 +415,14 @@ static int dz_startup(struct uart_port *uport)
return ret;
}
spin_lock_irqsave(&dport->port.lock, flags);
uart_port_lock_irqsave(&dport->port, &flags);
/* Enable interrupts. */
tmp = dz_in(dport, DZ_CSR);
tmp |= DZ_RIE | DZ_TIE;
dz_out(dport, DZ_CSR, tmp);
spin_unlock_irqrestore(&dport->port.lock, flags);
uart_port_unlock_irqrestore(&dport->port, flags);
return 0;
}
@ -443,9 +443,9 @@ static void dz_shutdown(struct uart_port *uport)
int irq_guard;
u16 tmp;
spin_lock_irqsave(&dport->port.lock, flags);
uart_port_lock_irqsave(&dport->port, &flags);
dz_stop_tx(&dport->port);
spin_unlock_irqrestore(&dport->port.lock, flags);
uart_port_unlock_irqrestore(&dport->port, flags);
irq_guard = atomic_add_return(-1, &mux->irq_guard);
if (!irq_guard) {
@ -491,14 +491,14 @@ static void dz_break_ctl(struct uart_port *uport, int break_state)
unsigned long flags;
unsigned short tmp, mask = 1 << dport->port.line;
spin_lock_irqsave(&uport->lock, flags);
uart_port_lock_irqsave(uport, &flags);
tmp = dz_in(dport, DZ_TCR);
if (break_state)
tmp |= mask;
else
tmp &= ~mask;
dz_out(dport, DZ_TCR, tmp);
spin_unlock_irqrestore(&uport->lock, flags);
uart_port_unlock_irqrestore(uport, flags);
}
static int dz_encode_baud_rate(unsigned int baud)
@ -608,7 +608,7 @@ static void dz_set_termios(struct uart_port *uport, struct ktermios *termios,
if (termios->c_cflag & CREAD)
cflag |= DZ_RXENAB;
spin_lock_irqsave(&dport->port.lock, flags);
uart_port_lock_irqsave(&dport->port, &flags);
uart_update_timeout(uport, termios->c_cflag, baud);
@ -631,7 +631,7 @@ static void dz_set_termios(struct uart_port *uport, struct ktermios *termios,
if (termios->c_iflag & IGNBRK)
dport->port.ignore_status_mask |= DZ_BREAK;
spin_unlock_irqrestore(&dport->port.lock, flags);
uart_port_unlock_irqrestore(&dport->port, flags);
}
/*
@ -645,12 +645,12 @@ static void dz_pm(struct uart_port *uport, unsigned int state,
struct dz_port *dport = to_dport(uport);
unsigned long flags;
spin_lock_irqsave(&dport->port.lock, flags);
uart_port_lock_irqsave(&dport->port, &flags);
if (state < 3)
dz_start_tx(&dport->port);
else
dz_stop_tx(&dport->port);
spin_unlock_irqrestore(&dport->port.lock, flags);
uart_port_unlock_irqrestore(&dport->port, flags);
}
@ -811,7 +811,7 @@ static void dz_console_putchar(struct uart_port *uport, unsigned char ch)
unsigned short csr, tcr, trdy, mask;
int loops = 10000;
spin_lock_irqsave(&dport->port.lock, flags);
uart_port_lock_irqsave(&dport->port, &flags);
csr = dz_in(dport, DZ_CSR);
dz_out(dport, DZ_CSR, csr & ~DZ_TIE);
tcr = dz_in(dport, DZ_TCR);
@ -819,7 +819,7 @@ static void dz_console_putchar(struct uart_port *uport, unsigned char ch)
mask = tcr;
dz_out(dport, DZ_TCR, mask);
iob();
spin_unlock_irqrestore(&dport->port.lock, flags);
uart_port_unlock_irqrestore(&dport->port, flags);
do {
trdy = dz_in(dport, DZ_CSR);

459
drivers/tty/serial/esp32_acm.c Normal file
View File

@ -0,0 +1,459 @@
// SPDX-License-Identifier: GPL-2.0-or-later
#include <linux/bitfield.h>
#include <linux/bits.h>
#include <linux/console.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/serial_core.h>
#include <linux/slab.h>
#include <linux/tty_flip.h>
#include <asm/serial.h>
#define DRIVER_NAME "esp32s3-acm"
#define DEV_NAME "ttyGS"
#define UART_NR 4
#define ESP32S3_ACM_TX_FIFO_SIZE 64
#define USB_SERIAL_JTAG_EP1_REG 0x00
#define USB_SERIAL_JTAG_EP1_CONF_REG 0x04
#define USB_SERIAL_JTAG_WR_DONE BIT(0)
#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE BIT(1)
#define USB_SERIAL_JTAG_INT_ST_REG 0x0c
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST BIT(2)
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST BIT(3)
#define USB_SERIAL_JTAG_INT_ENA_REG 0x10
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA BIT(2)
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA BIT(3)
#define USB_SERIAL_JTAG_INT_CLR_REG 0x14
#define USB_SERIAL_JTAG_IN_EP1_ST_REG 0x2c
#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR GENMASK(8, 2)
#define USB_SERIAL_JTAG_OUT_EP1_ST_REG 0x3c
#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT GENMASK(22, 16)
static const struct of_device_id esp32s3_acm_dt_ids[] = {
{
.compatible = "esp,esp32s3-acm",
}, { /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, esp32s3_acm_dt_ids);
static struct uart_port *esp32s3_acm_ports[UART_NR];
static void esp32s3_acm_write(struct uart_port *port, unsigned long reg, u32 v)
{
writel(v, port->membase + reg);
}
static u32 esp32s3_acm_read(struct uart_port *port, unsigned long reg)
{
return readl(port->membase + reg);
}
static u32 esp32s3_acm_tx_fifo_free(struct uart_port *port)
{
u32 status = esp32s3_acm_read(port, USB_SERIAL_JTAG_EP1_CONF_REG);
return status & USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE;
}
static u32 esp32s3_acm_tx_fifo_cnt(struct uart_port *port)
{
u32 status = esp32s3_acm_read(port, USB_SERIAL_JTAG_IN_EP1_ST_REG);
return FIELD_GET(USB_SERIAL_JTAG_IN_EP1_WR_ADDR, status);
}
static u32 esp32s3_acm_rx_fifo_cnt(struct uart_port *port)
{
u32 status = esp32s3_acm_read(port, USB_SERIAL_JTAG_OUT_EP1_ST_REG);
return FIELD_GET(USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT, status);
}
/* return TIOCSER_TEMT when transmitter is not busy */
static unsigned int esp32s3_acm_tx_empty(struct uart_port *port)
{
return esp32s3_acm_tx_fifo_cnt(port) == 0 ? TIOCSER_TEMT : 0;
}
static void esp32s3_acm_set_mctrl(struct uart_port *port, unsigned int mctrl)
{
}
static unsigned int esp32s3_acm_get_mctrl(struct uart_port *port)
{
return TIOCM_CAR;
}
static void esp32s3_acm_stop_tx(struct uart_port *port)
{
u32 int_ena;
int_ena = esp32s3_acm_read(port, USB_SERIAL_JTAG_INT_ENA_REG);
int_ena &= ~USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA;
esp32s3_acm_write(port, USB_SERIAL_JTAG_INT_ENA_REG, int_ena);
}
static void esp32s3_acm_rxint(struct uart_port *port)
{
struct tty_port *tty_port = &port->state->port;
u32 rx_fifo_cnt = esp32s3_acm_rx_fifo_cnt(port);
unsigned long flags;
u32 i;
if (!rx_fifo_cnt)
return;
spin_lock_irqsave(&port->lock, flags);
for (i = 0; i < rx_fifo_cnt; ++i) {
u32 rx = esp32s3_acm_read(port, USB_SERIAL_JTAG_EP1_REG);
++port->icount.rx;
tty_insert_flip_char(tty_port, rx, TTY_NORMAL);
}
spin_unlock_irqrestore(&port->lock, flags);
tty_flip_buffer_push(tty_port);
}
static void esp32s3_acm_push(struct uart_port *port)
{
if (esp32s3_acm_tx_fifo_free(port))
esp32s3_acm_write(port, USB_SERIAL_JTAG_EP1_CONF_REG,
USB_SERIAL_JTAG_WR_DONE);
}
static void esp32s3_acm_put_char(struct uart_port *port, u8 c)
{
esp32s3_acm_write(port, USB_SERIAL_JTAG_EP1_REG, c);
}
static void esp32s3_acm_put_char_sync(struct uart_port *port, u8 c)
{
unsigned long timeout = jiffies + HZ;
while (!esp32s3_acm_tx_fifo_free(port)) {
if (time_after(jiffies, timeout)) {
dev_warn(port->dev, "timeout waiting for TX FIFO\n");
return;
}
cpu_relax();
}
esp32s3_acm_put_char(port, c);
esp32s3_acm_push(port);
}
static void esp32s3_acm_transmit_buffer(struct uart_port *port)
{
u32 tx_fifo_used;
unsigned int pending;
u8 ch;
if (!esp32s3_acm_tx_fifo_free(port))
return;
tx_fifo_used = esp32s3_acm_tx_fifo_cnt(port);
pending = uart_port_tx_limited(port, ch,
ESP32S3_ACM_TX_FIFO_SIZE - tx_fifo_used,
true, esp32s3_acm_put_char(port, ch),
({}));
if (pending) {
u32 int_ena;
int_ena = esp32s3_acm_read(port, USB_SERIAL_JTAG_INT_ENA_REG);
int_ena |= USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA;
esp32s3_acm_write(port, USB_SERIAL_JTAG_INT_ENA_REG, int_ena);
}
esp32s3_acm_push(port);
}
static void esp32s3_acm_txint(struct uart_port *port)
{
esp32s3_acm_transmit_buffer(port);
}
static irqreturn_t esp32s3_acm_int(int irq, void *dev_id)
{
struct uart_port *port = dev_id;
u32 status;
status = esp32s3_acm_read(port, USB_SERIAL_JTAG_INT_ST_REG);
esp32s3_acm_write(port, USB_SERIAL_JTAG_INT_CLR_REG, status);
if (status & USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST)
esp32s3_acm_rxint(port);
if (status & USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST)
esp32s3_acm_txint(port);
return IRQ_RETVAL(status);
}
static void esp32s3_acm_start_tx(struct uart_port *port)
{
esp32s3_acm_transmit_buffer(port);
}
static void esp32s3_acm_stop_rx(struct uart_port *port)
{
u32 int_ena;
int_ena = esp32s3_acm_read(port, USB_SERIAL_JTAG_INT_ENA_REG);
int_ena &= ~USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA;
esp32s3_acm_write(port, USB_SERIAL_JTAG_INT_ENA_REG, int_ena);
}
static int esp32s3_acm_startup(struct uart_port *port)
{
int ret;
ret = request_irq(port->irq, esp32s3_acm_int, 0, DRIVER_NAME, port);
if (ret)
return ret;
esp32s3_acm_write(port, USB_SERIAL_JTAG_INT_ENA_REG,
USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA);
return 0;
}
static void esp32s3_acm_shutdown(struct uart_port *port)
{
esp32s3_acm_write(port, USB_SERIAL_JTAG_INT_ENA_REG, 0);
free_irq(port->irq, port);
}
static void esp32s3_acm_set_termios(struct uart_port *port,
struct ktermios *termios,
const struct ktermios *old)
{
}
static const char *esp32s3_acm_type(struct uart_port *port)
{
return "ESP32S3 ACM";
}
/* configure/auto-configure the port */
static void esp32s3_acm_config_port(struct uart_port *port, int flags)
{
if (flags & UART_CONFIG_TYPE)
port->type = PORT_GENERIC;
}
#ifdef CONFIG_CONSOLE_POLL
static void esp32s3_acm_poll_put_char(struct uart_port *port, unsigned char c)
{
esp32s3_acm_put_char_sync(port, c);
}
static int esp32s3_acm_poll_get_char(struct uart_port *port)
{
if (esp32s3_acm_rx_fifo_cnt(port))
return esp32s3_acm_read(port, USB_SERIAL_JTAG_EP1_REG);
else
return NO_POLL_CHAR;
}
#endif
static const struct uart_ops esp32s3_acm_pops = {
.tx_empty = esp32s3_acm_tx_empty,
.set_mctrl = esp32s3_acm_set_mctrl,
.get_mctrl = esp32s3_acm_get_mctrl,
.stop_tx = esp32s3_acm_stop_tx,
.start_tx = esp32s3_acm_start_tx,
.stop_rx = esp32s3_acm_stop_rx,
.startup = esp32s3_acm_startup,
.shutdown = esp32s3_acm_shutdown,
.set_termios = esp32s3_acm_set_termios,
.type = esp32s3_acm_type,
.config_port = esp32s3_acm_config_port,
#ifdef CONFIG_CONSOLE_POLL
.poll_put_char = esp32s3_acm_poll_put_char,
.poll_get_char = esp32s3_acm_poll_get_char,
#endif
};
static void esp32s3_acm_string_write(struct uart_port *port, const char *s,
unsigned int count)
{
uart_console_write(port, s, count, esp32s3_acm_put_char_sync);
}
static void
esp32s3_acm_console_write(struct console *co, const char *s, unsigned int count)
{
struct uart_port *port = esp32s3_acm_ports[co->index];
unsigned long flags;
bool locked = true;
if (port->sysrq)
locked = false;
else if (oops_in_progress)
locked = spin_trylock_irqsave(&port->lock, flags);
else
spin_lock_irqsave(&port->lock, flags);
esp32s3_acm_string_write(port, s, count);
if (locked)
spin_unlock_irqrestore(&port->lock, flags);
}
static struct uart_driver esp32s3_acm_reg;
static struct console esp32s3_acm_console = {
.name = DEV_NAME,
.write = esp32s3_acm_console_write,
.device = uart_console_device,
.flags = CON_PRINTBUFFER,
.index = -1,
.data = &esp32s3_acm_reg,
};
static void esp32s3_acm_earlycon_write(struct console *con, const char *s,
unsigned int n)
{
struct earlycon_device *dev = con->data;
uart_console_write(&dev->port, s, n, esp32s3_acm_put_char_sync);
}
#ifdef CONFIG_CONSOLE_POLL
static int esp32s3_acm_earlycon_read(struct console *con, char *s, unsigned int n)
{
struct earlycon_device *dev = con->data;
unsigned int num_read = 0;
while (num_read < n) {
int c = esp32s3_acm_poll_get_char(&dev->port);
if (c == NO_POLL_CHAR)
break;
s[num_read++] = c;
}
return num_read;
}
#endif
static int __init esp32s3_acm_early_console_setup(struct earlycon_device *device,
const char *options)
{
if (!device->port.membase)
return -ENODEV;
device->con->write = esp32s3_acm_earlycon_write;
#ifdef CONFIG_CONSOLE_POLL
device->con->read = esp32s3_acm_earlycon_read;
#endif
return 0;
}
OF_EARLYCON_DECLARE(esp32s3acm, "esp,esp32s3-acm",
esp32s3_acm_early_console_setup);
static struct uart_driver esp32s3_acm_reg = {
.owner = THIS_MODULE,
.driver_name = DRIVER_NAME,
.dev_name = DEV_NAME,
.nr = ARRAY_SIZE(esp32s3_acm_ports),
.cons = &esp32s3_acm_console,
};
static int esp32s3_acm_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct uart_port *port;
struct resource *res;
int ret;
port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
if (!port)
return -ENOMEM;
ret = of_alias_get_id(np, "serial");
if (ret < 0) {
dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
return ret;
}
if (ret >= UART_NR) {
dev_err(&pdev->dev, "driver limited to %d serial ports\n",
UART_NR);
return -ENOMEM;
}
port->line = ret;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res)
return -ENODEV;
port->mapbase = res->start;
port->membase = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(port->membase))
return PTR_ERR(port->membase);
port->dev = &pdev->dev;
port->type = PORT_GENERIC;
port->iotype = UPIO_MEM;
port->irq = platform_get_irq(pdev, 0);
port->ops = &esp32s3_acm_pops;
port->flags = UPF_BOOT_AUTOCONF;
port->has_sysrq = 1;
port->fifosize = ESP32S3_ACM_TX_FIFO_SIZE;
esp32s3_acm_ports[port->line] = port;
platform_set_drvdata(pdev, port);
return uart_add_one_port(&esp32s3_acm_reg, port);
}
static int esp32s3_acm_remove(struct platform_device *pdev)
{
struct uart_port *port = platform_get_drvdata(pdev);
uart_remove_one_port(&esp32s3_acm_reg, port);
return 0;
}
static struct platform_driver esp32s3_acm_driver = {
.probe = esp32s3_acm_probe,
.remove = esp32s3_acm_remove,
.driver = {
.name = DRIVER_NAME,
.of_match_table = esp32s3_acm_dt_ids,
},
};
static int __init esp32s3_acm_init(void)
{
int ret;
ret = uart_register_driver(&esp32s3_acm_reg);
if (ret)
return ret;
ret = platform_driver_register(&esp32s3_acm_driver);
if (ret)
uart_unregister_driver(&esp32s3_acm_reg);
return ret;
}
static void __exit esp32s3_acm_exit(void)
{
platform_driver_unregister(&esp32s3_acm_driver);
uart_unregister_driver(&esp32s3_acm_reg);
}
module_init(esp32s3_acm_init);
module_exit(esp32s3_acm_exit);
MODULE_AUTHOR("Max Filippov <jcmvbkbc@gmail.com>");
MODULE_LICENSE("GPL");

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drivers/tty/serial/esp32_uart.c Normal file
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// SPDX-License-Identifier: GPL-2.0-or-later
#include <linux/bitfield.h>
#include <linux/bits.h>
#include <linux/clk.h>
#include <linux/console.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/serial_core.h>
#include <linux/slab.h>
#include <linux/tty_flip.h>
#include <asm/serial.h>
#define DRIVER_NAME "esp32-uart"
#define DEV_NAME "ttyS"
#define UART_NR 3
#define ESP32_UART_TX_FIFO_SIZE 127
#define ESP32_UART_RX_FIFO_SIZE 127
#define UART_FIFO_REG 0x00
#define UART_INT_RAW_REG 0x04
#define UART_INT_ST_REG 0x08
#define UART_INT_ENA_REG 0x0c
#define UART_INT_CLR_REG 0x10
#define UART_RXFIFO_FULL_INT BIT(0)
#define UART_TXFIFO_EMPTY_INT BIT(1)
#define UART_BRK_DET_INT BIT(7)
#define UART_CLKDIV_REG 0x14
#define ESP32_UART_CLKDIV GENMASK(19, 0)
#define ESP32S3_UART_CLKDIV GENMASK(11, 0)
#define UART_CLKDIV_SHIFT 0
#define UART_CLKDIV_FRAG GENMASK(23, 20)
#define UART_STATUS_REG 0x1c
#define ESP32_UART_RXFIFO_CNT GENMASK(7, 0)
#define ESP32S3_UART_RXFIFO_CNT GENMASK(9, 0)
#define UART_RXFIFO_CNT_SHIFT 0
#define UART_DSRN BIT(13)
#define UART_CTSN BIT(14)
#define ESP32_UART_TXFIFO_CNT GENMASK(23, 16)
#define ESP32S3_UART_TXFIFO_CNT GENMASK(25, 16)
#define UART_TXFIFO_CNT_SHIFT 16
#define UART_CONF0_REG 0x20
#define UART_PARITY BIT(0)
#define UART_PARITY_EN BIT(1)
#define UART_BIT_NUM GENMASK(3, 2)
#define UART_BIT_NUM_5 0
#define UART_BIT_NUM_6 1
#define UART_BIT_NUM_7 2
#define UART_BIT_NUM_8 3
#define UART_STOP_BIT_NUM GENMASK(5, 4)
#define UART_STOP_BIT_NUM_1 1
#define UART_STOP_BIT_NUM_2 3
#define UART_SW_RTS BIT(6)
#define UART_SW_DTR BIT(7)
#define UART_LOOPBACK BIT(14)
#define UART_TX_FLOW_EN BIT(15)
#define UART_RTS_INV BIT(23)
#define UART_DTR_INV BIT(24)
#define UART_CONF1_REG 0x24
#define UART_RXFIFO_FULL_THRHD_SHIFT 0
#define ESP32_UART_TXFIFO_EMPTY_THRHD_SHIFT 8
#define ESP32S3_UART_TXFIFO_EMPTY_THRHD_SHIFT 10
#define ESP32_UART_RX_FLOW_EN BIT(23)
#define ESP32S3_UART_RX_FLOW_EN BIT(22)
#define ESP32S3_UART_CLK_CONF_REG 0x78
#define ESP32S3_UART_SCLK_DIV_B GENMASK(5, 0)
#define ESP32S3_UART_SCLK_DIV_A GENMASK(11, 6)
#define ESP32S3_UART_SCLK_DIV_NUM GENMASK(19, 12)
#define ESP32S3_UART_SCLK_SEL GENMASK(21, 20)
#define APB_CLK 1
#define RC_FAST_CLK 2
#define XTAL_CLK 3
#define ESP32S3_UART_SCLK_EN BIT(22)
#define ESP32S3_UART_RST_CORE BIT(23)
#define ESP32S3_UART_TX_SCLK_EN BIT(24)
#define ESP32S3_UART_RX_SCLK_EN BIT(25)
#define ESP32S3_UART_TX_RST_CORE BIT(26)
#define ESP32S3_UART_RX_RST_CORE BIT(27)
#define ESP32S3_UART_CLK_CONF_DEFAULT \
(ESP32S3_UART_RX_SCLK_EN | \
ESP32S3_UART_TX_SCLK_EN | \
ESP32S3_UART_SCLK_EN | \
FIELD_PREP(ESP32S3_UART_SCLK_SEL, XTAL_CLK))
struct esp32_port {
struct uart_port port;
struct clk *clk;
};
struct esp32_uart_variant {
u32 clkdiv_mask;
u32 rxfifo_cnt_mask;
u32 txfifo_cnt_mask;
u32 txfifo_empty_thrhd_shift;
u32 rx_flow_en;
const char *type;
bool has_clkconf;
};
static const struct esp32_uart_variant esp32_variant = {
.clkdiv_mask = ESP32_UART_CLKDIV,
.rxfifo_cnt_mask = ESP32_UART_RXFIFO_CNT,
.txfifo_cnt_mask = ESP32_UART_TXFIFO_CNT,
.txfifo_empty_thrhd_shift = ESP32_UART_TXFIFO_EMPTY_THRHD_SHIFT,
.rx_flow_en = ESP32_UART_RX_FLOW_EN,
.type = "ESP32 UART",
};
static const struct esp32_uart_variant esp32s3_variant = {
.clkdiv_mask = ESP32S3_UART_CLKDIV,
.rxfifo_cnt_mask = ESP32S3_UART_RXFIFO_CNT,
.txfifo_cnt_mask = ESP32S3_UART_TXFIFO_CNT,
.txfifo_empty_thrhd_shift = ESP32S3_UART_TXFIFO_EMPTY_THRHD_SHIFT,
.rx_flow_en = ESP32S3_UART_RX_FLOW_EN,
.type = "ESP32S3 UART",
.has_clkconf = true,
};
static const struct of_device_id esp32_uart_dt_ids[] = {
{
.compatible = "esp,esp32-uart",
.data = &esp32_variant,
}, {
.compatible = "esp,esp32s3-uart",
.data = &esp32s3_variant,
}, { /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, esp32_uart_dt_ids);
static struct esp32_port *esp32_uart_ports[UART_NR];
static const struct esp32_uart_variant *port_variant(struct uart_port *port)
{
return port->private_data;
}
static void esp32_uart_write(struct uart_port *port, unsigned long reg, u32 v)
{
writel(v, port->membase + reg);
}
static u32 esp32_uart_read(struct uart_port *port, unsigned long reg)
{
return readl(port->membase + reg);
}
static u32 esp32_uart_tx_fifo_cnt(struct uart_port *port)
{
u32 status = esp32_uart_read(port, UART_STATUS_REG);
return (status & port_variant(port)->txfifo_cnt_mask) >> UART_TXFIFO_CNT_SHIFT;
}
static u32 esp32_uart_rx_fifo_cnt(struct uart_port *port)
{
u32 status = esp32_uart_read(port, UART_STATUS_REG);
return (status & port_variant(port)->rxfifo_cnt_mask) >> UART_RXFIFO_CNT_SHIFT;
}
/* return TIOCSER_TEMT when transmitter is not busy */
static unsigned int esp32_uart_tx_empty(struct uart_port *port)
{
return esp32_uart_tx_fifo_cnt(port) ? 0 : TIOCSER_TEMT;
}
static void esp32_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
{
u32 conf0 = esp32_uart_read(port, UART_CONF0_REG);
conf0 &= ~(UART_LOOPBACK |
UART_SW_RTS | UART_RTS_INV |
UART_SW_DTR | UART_DTR_INV);
if (mctrl & TIOCM_RTS)
conf0 |= UART_SW_RTS;
if (mctrl & TIOCM_DTR)
conf0 |= UART_SW_DTR;
if (mctrl & TIOCM_LOOP)
conf0 |= UART_LOOPBACK;
esp32_uart_write(port, UART_CONF0_REG, conf0);
}
static unsigned int esp32_uart_get_mctrl(struct uart_port *port)
{
u32 status = esp32_uart_read(port, UART_STATUS_REG);
unsigned int ret = TIOCM_CAR;
if (status & UART_DSRN)
ret |= TIOCM_DSR;
if (status & UART_CTSN)
ret |= TIOCM_CTS;
return ret;
}
static void esp32_uart_stop_tx(struct uart_port *port)
{
u32 int_ena;
int_ena = esp32_uart_read(port, UART_INT_ENA_REG);
int_ena &= ~UART_TXFIFO_EMPTY_INT;
esp32_uart_write(port, UART_INT_ENA_REG, int_ena);
}
static void esp32_uart_rxint(struct uart_port *port)
{
struct tty_port *tty_port = &port->state->port;
u32 rx_fifo_cnt = esp32_uart_rx_fifo_cnt(port);
unsigned long flags;
u32 i;
if (!rx_fifo_cnt)
return;
spin_lock_irqsave(&port->lock, flags);
for (i = 0; i < rx_fifo_cnt; ++i) {
u32 rx = esp32_uart_read(port, UART_FIFO_REG);
if (!rx &&
(esp32_uart_read(port, UART_INT_ST_REG) & UART_BRK_DET_INT)) {
esp32_uart_write(port, UART_INT_CLR_REG, UART_BRK_DET_INT);
++port->icount.brk;
uart_handle_break(port);
} else {
if (uart_handle_sysrq_char(port, (unsigned char)rx))
continue;
tty_insert_flip_char(tty_port, rx, TTY_NORMAL);
++port->icount.rx;
}
}
spin_unlock_irqrestore(&port->lock, flags);
tty_flip_buffer_push(tty_port);
}
static void esp32_uart_put_char(struct uart_port *port, u8 c)
{
esp32_uart_write(port, UART_FIFO_REG, c);
}
static void esp32_uart_put_char_sync(struct uart_port *port, u8 c)
{
unsigned long timeout = jiffies + HZ;
while (esp32_uart_tx_fifo_cnt(port) >= ESP32_UART_TX_FIFO_SIZE) {
if (time_after(jiffies, timeout)) {
dev_warn(port->dev, "timeout waiting for TX FIFO\n");
return;
}
cpu_relax();
}
esp32_uart_put_char(port, c);
}
static void esp32_uart_transmit_buffer(struct uart_port *port)
{
u32 tx_fifo_used = esp32_uart_tx_fifo_cnt(port);
unsigned int pending;
u8 ch;
if (tx_fifo_used >= ESP32_UART_TX_FIFO_SIZE)
return;
pending = uart_port_tx_limited(port, ch,
ESP32_UART_TX_FIFO_SIZE - tx_fifo_used,
true, esp32_uart_put_char(port, ch),
({}));
if (pending) {
u32 int_ena;
int_ena = esp32_uart_read(port, UART_INT_ENA_REG);
int_ena |= UART_TXFIFO_EMPTY_INT;
esp32_uart_write(port, UART_INT_ENA_REG, int_ena);
}
}
static void esp32_uart_txint(struct uart_port *port)
{
esp32_uart_transmit_buffer(port);
}
static irqreturn_t esp32_uart_int(int irq, void *dev_id)
{
struct uart_port *port = dev_id;
u32 status;
status = esp32_uart_read(port, UART_INT_ST_REG);
if (status & (UART_RXFIFO_FULL_INT | UART_BRK_DET_INT))
esp32_uart_rxint(port);
if (status & UART_TXFIFO_EMPTY_INT)
esp32_uart_txint(port);
esp32_uart_write(port, UART_INT_CLR_REG, status);
return IRQ_RETVAL(status);
}
static void esp32_uart_start_tx(struct uart_port *port)
{
esp32_uart_transmit_buffer(port);
}
static void esp32_uart_stop_rx(struct uart_port *port)
{
u32 int_ena;
int_ena = esp32_uart_read(port, UART_INT_ENA_REG);
int_ena &= ~UART_RXFIFO_FULL_INT;
esp32_uart_write(port, UART_INT_ENA_REG, int_ena);
}
static int esp32_uart_startup(struct uart_port *port)
{
int ret = 0;
unsigned long flags;
struct esp32_port *sport = container_of(port, struct esp32_port, port);
ret = clk_prepare_enable(sport->clk);
if (ret)
return ret;
ret = request_irq(port->irq, esp32_uart_int, 0, DRIVER_NAME, port);
if (ret) {
clk_disable_unprepare(sport->clk);
return ret;
}
spin_lock_irqsave(&port->lock, flags);
if (port_variant(port)->has_clkconf)
esp32_uart_write(port, ESP32S3_UART_CLK_CONF_REG,
ESP32S3_UART_CLK_CONF_DEFAULT);
esp32_uart_write(port, UART_CONF1_REG,
(1 << UART_RXFIFO_FULL_THRHD_SHIFT) |
(1 << port_variant(port)->txfifo_empty_thrhd_shift));
esp32_uart_write(port, UART_INT_CLR_REG, UART_RXFIFO_FULL_INT | UART_BRK_DET_INT);
esp32_uart_write(port, UART_INT_ENA_REG, UART_RXFIFO_FULL_INT | UART_BRK_DET_INT);
spin_unlock_irqrestore(&port->lock, flags);
return ret;
}
static void esp32_uart_shutdown(struct uart_port *port)
{
struct esp32_port *sport = container_of(port, struct esp32_port, port);
esp32_uart_write(port, UART_INT_ENA_REG, 0);
free_irq(port->irq, port);
clk_disable_unprepare(sport->clk);
}
static bool esp32_uart_set_baud(struct uart_port *port, u32 baud)
{
u32 sclk = port->uartclk;
u32 div = sclk / baud;
if (port_variant(port)->has_clkconf) {
u32 sclk_div = div / port_variant(port)->clkdiv_mask;
if (div > port_variant(port)->clkdiv_mask) {
sclk /= (sclk_div + 1);
div = sclk / baud;
}
esp32_uart_write(port, ESP32S3_UART_CLK_CONF_REG,
FIELD_PREP(ESP32S3_UART_SCLK_DIV_NUM, sclk_div) |
ESP32S3_UART_CLK_CONF_DEFAULT);
}
if (div <= port_variant(port)->clkdiv_mask) {
u32 frag = (sclk * 16) / baud - div * 16;
esp32_uart_write(port, UART_CLKDIV_REG,
div | FIELD_PREP(UART_CLKDIV_FRAG, frag));
return true;
}
return false;
}
static void esp32_uart_set_termios(struct uart_port *port,
struct ktermios *termios,
const struct ktermios *old)
{
unsigned long flags;
u32 conf0, conf1;
u32 baud;
const u32 rx_flow_en = port_variant(port)->rx_flow_en;
u32 max_div = port_variant(port)->clkdiv_mask;
termios->c_cflag &= ~CMSPAR;
if (port_variant(port)->has_clkconf)
max_div *= FIELD_MAX(ESP32S3_UART_SCLK_DIV_NUM);
baud = uart_get_baud_rate(port, termios, old,
port->uartclk / max_div,
port->uartclk / 16);
spin_lock_irqsave(&port->lock, flags);
conf0 = esp32_uart_read(port, UART_CONF0_REG);
conf0 &= ~(UART_PARITY_EN | UART_PARITY | UART_BIT_NUM | UART_STOP_BIT_NUM);
conf1 = esp32_uart_read(port, UART_CONF1_REG);
conf1 &= ~rx_flow_en;
if (termios->c_cflag & PARENB) {
conf0 |= UART_PARITY_EN;
if (termios->c_cflag & PARODD)
conf0 |= UART_PARITY;
}
switch (termios->c_cflag & CSIZE) {
case CS5:
conf0 |= FIELD_PREP(UART_BIT_NUM, UART_BIT_NUM_5);
break;
case CS6:
conf0 |= FIELD_PREP(UART_BIT_NUM, UART_BIT_NUM_6);
break;
case CS7:
conf0 |= FIELD_PREP(UART_BIT_NUM, UART_BIT_NUM_7);
break;
case CS8:
conf0 |= FIELD_PREP(UART_BIT_NUM, UART_BIT_NUM_8);
break;
}
if (termios->c_cflag & CSTOPB)
conf0 |= FIELD_PREP(UART_STOP_BIT_NUM, UART_STOP_BIT_NUM_2);
else
conf0 |= FIELD_PREP(UART_STOP_BIT_NUM, UART_STOP_BIT_NUM_1);
if (termios->c_cflag & CRTSCTS)
conf1 |= rx_flow_en;
esp32_uart_write(port, UART_CONF0_REG, conf0);
esp32_uart_write(port, UART_CONF1_REG, conf1);
if (baud) {
esp32_uart_set_baud(port, baud);
uart_update_timeout(port, termios->c_cflag, baud);
} else {
if (esp32_uart_set_baud(port, 115200)) {
baud = 115200;
tty_termios_encode_baud_rate(termios, baud, baud);
uart_update_timeout(port, termios->c_cflag, baud);
} else {
dev_warn(port->dev,
"unable to set speed to %d baud or the default 115200\n",
baud);
}
}
spin_unlock_irqrestore(&port->lock, flags);
}
static const char *esp32_uart_type(struct uart_port *port)
{
return port_variant(port)->type;
}
/* configure/auto-configure the port */
static void esp32_uart_config_port(struct uart_port *port, int flags)
{
if (flags & UART_CONFIG_TYPE)
port->type = PORT_GENERIC;
}
#ifdef CONFIG_CONSOLE_POLL
static int esp32_uart_poll_init(struct uart_port *port)
{
struct esp32_port *sport = container_of(port, struct esp32_port, port);
return clk_prepare_enable(sport->clk);
}
static void esp32_uart_poll_put_char(struct uart_port *port, unsigned char c)
{
esp32_uart_put_char_sync(port, c);
}
static int esp32_uart_poll_get_char(struct uart_port *port)
{
if (esp32_uart_rx_fifo_cnt(port))
return esp32_uart_read(port, UART_FIFO_REG);
else
return NO_POLL_CHAR;
}
#endif
static const struct uart_ops esp32_uart_pops = {
.tx_empty = esp32_uart_tx_empty,
.set_mctrl = esp32_uart_set_mctrl,
.get_mctrl = esp32_uart_get_mctrl,
.stop_tx = esp32_uart_stop_tx,
.start_tx = esp32_uart_start_tx,
.stop_rx = esp32_uart_stop_rx,
.startup = esp32_uart_startup,
.shutdown = esp32_uart_shutdown,
.set_termios = esp32_uart_set_termios,
.type = esp32_uart_type,
.config_port = esp32_uart_config_port,
#ifdef CONFIG_CONSOLE_POLL
.poll_init = esp32_uart_poll_init,
.poll_put_char = esp32_uart_poll_put_char,
.poll_get_char = esp32_uart_poll_get_char,
#endif
};
static void esp32_uart_console_putchar(struct uart_port *port, u8 c)
{
esp32_uart_put_char_sync(port, c);
}
static void esp32_uart_string_write(struct uart_port *port, const char *s,
unsigned int count)
{
uart_console_write(port, s, count, esp32_uart_console_putchar);
}
static void
esp32_uart_console_write(struct console *co, const char *s, unsigned int count)
{
struct esp32_port *sport = esp32_uart_ports[co->index];
struct uart_port *port = &sport->port;
unsigned long flags;
bool locked = true;
if (port->sysrq)
locked = false;
else if (oops_in_progress)
locked = spin_trylock_irqsave(&port->lock, flags);
else
spin_lock_irqsave(&port->lock, flags);
esp32_uart_string_write(port, s, count);
if (locked)
spin_unlock_irqrestore(&port->lock, flags);
}
static int __init esp32_uart_console_setup(struct console *co, char *options)
{
struct esp32_port *sport;
int baud = 115200;
int bits = 8;
int parity = 'n';
int flow = 'n';
int ret;
/*
* check whether an invalid uart number has been specified, and
* if so, search for the first available port that does have
* console support.
*/
if (co->index == -1 || co->index >= ARRAY_SIZE(esp32_uart_ports))
co->index = 0;
sport = esp32_uart_ports[co->index];
if (!sport)
return -ENODEV;
ret = clk_prepare_enable(sport->clk);
if (ret)
return ret;
if (options)
uart_parse_options(options, &baud, &parity, &bits, &flow);
return uart_set_options(&sport->port, co, baud, parity, bits, flow);
}
static int esp32_uart_console_exit(struct console *co)
{
struct esp32_port *sport = esp32_uart_ports[co->index];
clk_disable_unprepare(sport->clk);
return 0;
}
static struct uart_driver esp32_uart_reg;
static struct console esp32_uart_console = {
.name = DEV_NAME,
.write = esp32_uart_console_write,
.device = uart_console_device,
.setup = esp32_uart_console_setup,
.exit = esp32_uart_console_exit,
.flags = CON_PRINTBUFFER,
.index = -1,
.data = &esp32_uart_reg,
};
static void esp32_uart_earlycon_putchar(struct uart_port *port, u8 c)
{
esp32_uart_put_char_sync(port, c);
}
static void esp32_uart_earlycon_write(struct console *con, const char *s,
unsigned int n)
{
struct earlycon_device *dev = con->data;
uart_console_write(&dev->port, s, n, esp32_uart_earlycon_putchar);
}
#ifdef CONFIG_CONSOLE_POLL
static int esp32_uart_earlycon_read(struct console *con, char *s, unsigned int n)
{
struct earlycon_device *dev = con->data;
unsigned int num_read = 0;
while (num_read < n) {
int c = esp32_uart_poll_get_char(&dev->port);
if (c == NO_POLL_CHAR)
break;
s[num_read++] = c;
}
return num_read;
}
#endif
static int __init esp32xx_uart_early_console_setup(struct earlycon_device *device,
const char *options)
{
if (!device->port.membase)
return -ENODEV;
device->con->write = esp32_uart_earlycon_write;
#ifdef CONFIG_CONSOLE_POLL
device->con->read = esp32_uart_earlycon_read;
#endif
if (device->port.uartclk != BASE_BAUD * 16)
esp32_uart_set_baud(&device->port, device->baud);
return 0;
}
static int __init esp32_uart_early_console_setup(struct earlycon_device *device,
const char *options)
{
device->port.private_data = (void *)&esp32_variant;
return esp32xx_uart_early_console_setup(device, options);
}
OF_EARLYCON_DECLARE(esp32uart, "esp,esp32-uart",
esp32_uart_early_console_setup);
static int __init esp32s3_uart_early_console_setup(struct earlycon_device *device,
const char *options)
{
device->port.private_data = (void *)&esp32s3_variant;
return esp32xx_uart_early_console_setup(device, options);
}
OF_EARLYCON_DECLARE(esp32s3uart, "esp,esp32s3-uart",
esp32s3_uart_early_console_setup);
static struct uart_driver esp32_uart_reg = {
.owner = THIS_MODULE,
.driver_name = DRIVER_NAME,
.dev_name = DEV_NAME,
.nr = ARRAY_SIZE(esp32_uart_ports),
.cons = &esp32_uart_console,
};
static int esp32_uart_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
static const struct of_device_id *match;
struct uart_port *port;
struct esp32_port *sport;
struct resource *res;
int ret;
match = of_match_device(esp32_uart_dt_ids, &pdev->dev);
if (!match)
return -ENODEV;
sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
if (!sport)
return -ENOMEM;
port = &sport->port;
ret = of_alias_get_id(np, "serial");
if (ret < 0) {
dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
return ret;
}
if (ret >= UART_NR) {
dev_err(&pdev->dev, "driver limited to %d serial ports\n", UART_NR);
return -ENOMEM;
}
port->line = ret;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res)
return -ENODEV;
port->mapbase = res->start;
port->membase = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(port->membase))
return PTR_ERR(port->membase);
sport->clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(sport->clk))
return PTR_ERR(sport->clk);
port->uartclk = clk_get_rate(sport->clk);
port->dev = &pdev->dev;
port->type = PORT_GENERIC;
port->iotype = UPIO_MEM;
port->irq = platform_get_irq(pdev, 0);
port->ops = &esp32_uart_pops;
port->flags = UPF_BOOT_AUTOCONF;
port->has_sysrq = 1;
port->fifosize = ESP32_UART_TX_FIFO_SIZE;
port->private_data = (void *)match->data;
esp32_uart_ports[port->line] = sport;
platform_set_drvdata(pdev, port);
return uart_add_one_port(&esp32_uart_reg, port);
}
static int esp32_uart_remove(struct platform_device *pdev)
{
struct uart_port *port = platform_get_drvdata(pdev);
uart_remove_one_port(&esp32_uart_reg, port);
return 0;
}
static struct platform_driver esp32_uart_driver = {
.probe = esp32_uart_probe,
.remove = esp32_uart_remove,
.driver = {
.name = DRIVER_NAME,
.of_match_table = esp32_uart_dt_ids,
},
};
static int __init esp32_uart_init(void)
{
int ret;
ret = uart_register_driver(&esp32_uart_reg);
if (ret)
return ret;
ret = platform_driver_register(&esp32_uart_driver);
if (ret)
uart_unregister_driver(&esp32_uart_reg);
return ret;
}
static void __exit esp32_uart_exit(void)
{
platform_driver_unregister(&esp32_uart_driver);
uart_unregister_driver(&esp32_uart_reg);
}
module_init(esp32_uart_init);
module_exit(esp32_uart_exit);
MODULE_AUTHOR("Max Filippov <jcmvbkbc@gmail.com>");
MODULE_LICENSE("GPL");

32
drivers/tty/serial/fsl_linflexuart.c
View File

@ -203,7 +203,7 @@ static irqreturn_t linflex_txint(int irq, void *dev_id)
struct circ_buf *xmit = &sport->state->xmit;
unsigned long flags;
spin_lock_irqsave(&sport->lock, flags);
uart_port_lock_irqsave(sport, &flags);
if (sport->x_char) {
linflex_put_char(sport, sport->x_char);
@ -217,7 +217,7 @@ static irqreturn_t linflex_txint(int irq, void *dev_id)
linflex_transmit_buffer(sport);
out:
spin_unlock_irqrestore(&sport->lock, flags);
uart_port_unlock_irqrestore(sport, flags);
return IRQ_HANDLED;
}
@ -230,7 +230,7 @@ static irqreturn_t linflex_rxint(int irq, void *dev_id)
unsigned char rx;
bool brk;
spin_lock_irqsave(&sport->lock, flags);
uart_port_lock_irqsave(sport, &flags);
status = readl(sport->membase + UARTSR);
while (status & LINFLEXD_UARTSR_RMB) {
@ -266,7 +266,7 @@ static irqreturn_t linflex_rxint(int irq, void *dev_id)
}
}
spin_unlock_irqrestore(&sport->lock, flags);
uart_port_unlock_irqrestore(sport, flags);
tty_flip_buffer_push(port);
@ -369,11 +369,11 @@ static int linflex_startup(struct uart_port *port)
int ret = 0;
unsigned long flags;
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
linflex_setup_watermark(port);
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
ret = devm_request_irq(port->dev, port->irq, linflex_int, 0,
DRIVER_NAME, port);
@ -386,14 +386,14 @@ static void linflex_shutdown(struct uart_port *port)
unsigned long ier;
unsigned long flags;
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
/* disable interrupts */
ier = readl(port->membase + LINIER);
ier &= ~(LINFLEXD_LINIER_DRIE | LINFLEXD_LINIER_DTIE);
writel(ier, port->membase + LINIER);
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
devm_free_irq(port->dev, port->irq, port);
}
@ -474,7 +474,7 @@ linflex_set_termios(struct uart_port *port, struct ktermios *termios,
cr &= ~LINFLEXD_UARTCR_PCE;
}
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
port->read_status_mask = 0;
@ -507,7 +507,7 @@ linflex_set_termios(struct uart_port *port, struct ktermios *termios,
writel(cr1, port->membase + LINCR1);
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
}
static const char *linflex_type(struct uart_port *port)
@ -646,14 +646,14 @@ linflex_console_write(struct console *co, const char *s, unsigned int count)
if (sport->sysrq)
locked = 0;
else if (oops_in_progress)
locked = spin_trylock_irqsave(&sport->lock, flags);
locked = uart_port_trylock_irqsave(sport, &flags);
else
spin_lock_irqsave(&sport->lock, flags);
uart_port_lock_irqsave(sport, &flags);
linflex_string_write(sport, s, count);
if (locked)
spin_unlock_irqrestore(&sport->lock, flags);
uart_port_unlock_irqrestore(sport, flags);
}
/*
@ -832,10 +832,14 @@ static int linflex_probe(struct platform_device *pdev)
return PTR_ERR(sport->membase);
sport->mapbase = res->start;
ret = platform_get_irq(pdev, 0);
if (ret < 0)
return ret;
sport->dev = &pdev->dev;
sport->type = PORT_LINFLEXUART;
sport->iotype = UPIO_MEM;
sport->irq = platform_get_irq(pdev, 0);
sport->irq = ret;
sport->ops = &linflex_pops;
sport->flags = UPF_BOOT_AUTOCONF;
sport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE);

88
drivers/tty/serial/fsl_lpuart.c
View File

@ -532,9 +532,9 @@ static void lpuart_dma_tx_complete(void *arg)
struct dma_chan *chan = sport->dma_tx_chan;
unsigned long flags;
spin_lock_irqsave(&sport->port.lock, flags);
uart_port_lock_irqsave(&sport->port, &flags);
if (!sport->dma_tx_in_progress) {
spin_unlock_irqrestore(&sport->port.lock, flags);
uart_port_unlock_irqrestore(&sport->port, flags);
return;
}
@ -543,7 +543,7 @@ static void lpuart_dma_tx_complete(void *arg)
uart_xmit_advance(&sport->port, sport->dma_tx_bytes);
sport->dma_tx_in_progress = false;
spin_unlock_irqrestore(&sport->port.lock, flags);
uart_port_unlock_irqrestore(&sport->port, flags);
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
uart_write_wakeup(&sport->port);
@ -553,12 +553,12 @@ static void lpuart_dma_tx_complete(void *arg)
return;
}
spin_lock_irqsave(&sport->port.lock, flags);
uart_port_lock_irqsave(&sport->port, &flags);
if (!lpuart_stopped_or_empty(&sport->port))
lpuart_dma_tx(sport);
spin_unlock_irqrestore(&sport->port.lock, flags);
uart_port_unlock_irqrestore(&sport->port, flags);
}
static dma_addr_t lpuart_dma_datareg_addr(struct lpuart_port *sport)
@ -651,7 +651,7 @@ static int lpuart_poll_init(struct uart_port *port)
sport->port.fifosize = 0;
spin_lock_irqsave(&sport->port.lock, flags);
uart_port_lock_irqsave(&sport->port, &flags);
/* Disable Rx & Tx */
writeb(0, sport->port.membase + UARTCR2);
@ -675,7 +675,7 @@ static int lpuart_poll_init(struct uart_port *port)
/* Enable Rx and Tx */
writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2);
spin_unlock_irqrestore(&sport->port.lock, flags);
uart_port_unlock_irqrestore(&sport->port, flags);
return 0;
}
@ -703,7 +703,7 @@ static int lpuart32_poll_init(struct uart_port *port)
sport->port.fifosize = 0;
spin_lock_irqsave(&sport->port.lock, flags);
uart_port_lock_irqsave(&sport->port, &flags);
/* Disable Rx & Tx */
lpuart32_write(&sport->port, 0, UARTCTRL);
@ -724,7 +724,7 @@ static int lpuart32_poll_init(struct uart_port *port)
/* Enable Rx and Tx */
lpuart32_write(&sport->port, UARTCTRL_RE | UARTCTRL_TE, UARTCTRL);
spin_unlock_irqrestore(&sport->port.lock, flags);
uart_port_unlock_irqrestore(&sport->port, flags);
return 0;
}
@ -879,9 +879,9 @@ static unsigned int lpuart32_tx_empty(struct uart_port *port)
static void lpuart_txint(struct lpuart_port *sport)
{
spin_lock(&sport->port.lock);
uart_port_lock(&sport->port);
lpuart_transmit_buffer(sport);
spin_unlock(&sport->port.lock);
uart_port_unlock(&sport->port);
}
static void lpuart_rxint(struct lpuart_port *sport)
@ -890,7 +890,7 @@ static void lpuart_rxint(struct lpuart_port *sport)
struct tty_port *port = &sport->port.state->port;
unsigned char rx, sr;
spin_lock(&sport->port.lock);
uart_port_lock(&sport->port);
while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) {
flg = TTY_NORMAL;
@ -956,9 +956,9 @@ out:
static void lpuart32_txint(struct lpuart_port *sport)
{
spin_lock(&sport->port.lock);
uart_port_lock(&sport->port);
lpuart32_transmit_buffer(sport);
spin_unlock(&sport->port.lock);
uart_port_unlock(&sport->port);
}
static void lpuart32_rxint(struct lpuart_port *sport)
@ -968,7 +968,7 @@ static void lpuart32_rxint(struct lpuart_port *sport)
unsigned long rx, sr;
bool is_break;
spin_lock(&sport->port.lock);
uart_port_lock(&sport->port);
while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) {
flg = TTY_NORMAL;
@ -1170,12 +1170,12 @@ static void lpuart_copy_rx_to_tty(struct lpuart_port *sport)
async_tx_ack(sport->dma_rx_desc);
spin_lock_irqsave(&sport->port.lock, flags);
uart_port_lock_irqsave(&sport->port, &flags);
dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state);
if (dmastat == DMA_ERROR) {
dev_err(sport->port.dev, "Rx DMA transfer failed!\n");
spin_unlock_irqrestore(&sport->port.lock, flags);
uart_port_unlock_irqrestore(&sport->port, flags);
return;
}
@ -1244,7 +1244,7 @@ exit:
dma_sync_sg_for_device(chan->device->dev, &sport->rx_sgl, 1,
DMA_FROM_DEVICE);
spin_unlock_irqrestore(&sport->port.lock, flags);
uart_port_unlock_irqrestore(&sport->port, flags);
tty_flip_buffer_push(port);
if (!sport->dma_idle_int)
@ -1335,9 +1335,9 @@ static void lpuart_timer_func(struct timer_list *t)
mod_timer(&sport->lpuart_timer,
jiffies + sport->dma_rx_timeout);
if (spin_trylock_irqsave(&sport->port.lock, flags)) {
if (uart_port_trylock_irqsave(&sport->port, &flags)) {
sport->last_residue = state.residue;
spin_unlock_irqrestore(&sport->port.lock, flags);
uart_port_unlock_irqrestore(&sport->port, flags);
}
}
@ -1802,14 +1802,14 @@ static void lpuart_hw_setup(struct lpuart_port *sport)
{
unsigned long flags;
spin_lock_irqsave(&sport->port.lock, flags);
uart_port_lock_irqsave(&sport->port, &flags);
lpuart_setup_watermark_enable(sport);
lpuart_rx_dma_startup(sport);
lpuart_tx_dma_startup(sport);
spin_unlock_irqrestore(&sport->port.lock, flags);
uart_port_unlock_irqrestore(&sport->port, flags);
}
static int lpuart_startup(struct uart_port *port)
@ -1859,7 +1859,7 @@ static void lpuart32_hw_setup(struct lpuart_port *sport)
{
unsigned long flags;
spin_lock_irqsave(&sport->port.lock, flags);
uart_port_lock_irqsave(&sport->port, &flags);
lpuart32_hw_disable(sport);
@ -1869,7 +1869,7 @@ static void lpuart32_hw_setup(struct lpuart_port *sport)
lpuart32_setup_watermark_enable(sport);
lpuart32_configure(sport);
spin_unlock_irqrestore(&sport->port.lock, flags);
uart_port_unlock_irqrestore(&sport->port, flags);
}
static int lpuart32_startup(struct uart_port *port)
@ -1932,7 +1932,7 @@ static void lpuart_shutdown(struct uart_port *port)
unsigned char temp;
unsigned long flags;
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
/* disable Rx/Tx and interrupts */
temp = readb(port->membase + UARTCR2);
@ -1940,7 +1940,7 @@ static void lpuart_shutdown(struct uart_port *port)
UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
writeb(temp, port->membase + UARTCR2);
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
lpuart_dma_shutdown(sport);
}
@ -1952,7 +1952,7 @@ static void lpuart32_shutdown(struct uart_port *port)
unsigned long temp;
unsigned long flags;
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
/* clear status */
temp = lpuart32_read(&sport->port, UARTSTAT);
@ -1969,7 +1969,7 @@ static void lpuart32_shutdown(struct uart_port *port)
UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE | UARTCTRL_SBK);
lpuart32_write(port, temp, UARTCTRL);
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
lpuart_dma_shutdown(sport);
}
@ -2069,7 +2069,7 @@ lpuart_set_termios(struct uart_port *port, struct ktermios *termios,
if (old && sport->lpuart_dma_rx_use)
lpuart_dma_rx_free(&sport->port);
spin_lock_irqsave(&sport->port.lock, flags);
uart_port_lock_irqsave(&sport->port, &flags);
sport->port.read_status_mask = 0;
if (termios->c_iflag & INPCK)
@ -2124,7 +2124,7 @@ lpuart_set_termios(struct uart_port *port, struct ktermios *termios,
sport->lpuart_dma_rx_use = false;
}
spin_unlock_irqrestore(&sport->port.lock, flags);
uart_port_unlock_irqrestore(&sport->port, flags);
}
static void __lpuart32_serial_setbrg(struct uart_port *port,
@ -2304,7 +2304,7 @@ lpuart32_set_termios(struct uart_port *port, struct ktermios *termios,
if (old && sport->lpuart_dma_rx_use)
lpuart_dma_rx_free(&sport->port);
spin_lock_irqsave(&sport->port.lock, flags);
uart_port_lock_irqsave(&sport->port, &flags);
sport->port.read_status_mask = 0;
if (termios->c_iflag & INPCK)
@ -2359,7 +2359,7 @@ lpuart32_set_termios(struct uart_port *port, struct ktermios *termios,
sport->lpuart_dma_rx_use = false;
}
spin_unlock_irqrestore(&sport->port.lock, flags);
uart_port_unlock_irqrestore(&sport->port, flags);
}
static const char *lpuart_type(struct uart_port *port)
@ -2477,9 +2477,9 @@ lpuart_console_write(struct console *co, const char *s, unsigned int count)
int locked = 1;
if (oops_in_progress)
locked = spin_trylock_irqsave(&sport->port.lock, flags);
locked = uart_port_trylock_irqsave(&sport->port, &flags);
else
spin_lock_irqsave(&sport->port.lock, flags);
uart_port_lock_irqsave(&sport->port, &flags);
/* first save CR2 and then disable interrupts */
cr2 = old_cr2 = readb(sport->port.membase + UARTCR2);
@ -2495,7 +2495,7 @@ lpuart_console_write(struct console *co, const char *s, unsigned int count)
writeb(old_cr2, sport->port.membase + UARTCR2);
if (locked)
spin_unlock_irqrestore(&sport->port.lock, flags);
uart_port_unlock_irqrestore(&sport->port, flags);
}
static void
@ -2507,9 +2507,9 @@ lpuart32_console_write(struct console *co, const char *s, unsigned int count)
int locked = 1;
if (oops_in_progress)
locked = spin_trylock_irqsave(&sport->port.lock, flags);
locked = uart_port_trylock_irqsave(&sport->port, &flags);
else
spin_lock_irqsave(&sport->port.lock, flags);
uart_port_lock_irqsave(&sport->port, &flags);
/* first save CR2 and then disable interrupts */
cr = old_cr = lpuart32_read(&sport->port, UARTCTRL);
@ -2525,7 +2525,7 @@ lpuart32_console_write(struct console *co, const char *s, unsigned int count)
lpuart32_write(&sport->port, old_cr, UARTCTRL);
if (locked)
spin_unlock_irqrestore(&sport->port.lock, flags);
uart_port_unlock_irqrestore(&sport->port, flags);
}
/*
@ -3089,7 +3089,7 @@ static int lpuart_suspend(struct device *dev)
uart_suspend_port(&lpuart_reg, &sport->port);
if (lpuart_uport_is_active(sport)) {
spin_lock_irqsave(&sport->port.lock, flags);
uart_port_lock_irqsave(&sport->port, &flags);
if (lpuart_is_32(sport)) {
/* disable Rx/Tx and interrupts */
temp = lpuart32_read(&sport->port, UARTCTRL);
@ -3101,7 +3101,7 @@ static int lpuart_suspend(struct device *dev)
temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE);
writeb(temp, sport->port.membase + UARTCR2);
}
spin_unlock_irqrestore(&sport->port.lock, flags);
uart_port_unlock_irqrestore(&sport->port, flags);
if (sport->lpuart_dma_rx_use) {
/*
@ -3114,7 +3114,7 @@ static int lpuart_suspend(struct device *dev)
lpuart_dma_rx_free(&sport->port);
/* Disable Rx DMA to use UART port as wakeup source */
spin_lock_irqsave(&sport->port.lock, flags);
uart_port_lock_irqsave(&sport->port, &flags);
if (lpuart_is_32(sport)) {
temp = lpuart32_read(&sport->port, UARTBAUD);
lpuart32_write(&sport->port, temp & ~UARTBAUD_RDMAE,
@ -3123,11 +3123,11 @@ static int lpuart_suspend(struct device *dev)
writeb(readb(sport->port.membase + UARTCR5) &
~UARTCR5_RDMAS, sport->port.membase + UARTCR5);
}
spin_unlock_irqrestore(&sport->port.lock, flags);
uart_port_unlock_irqrestore(&sport->port, flags);
}
if (sport->lpuart_dma_tx_use) {
spin_lock_irqsave(&sport->port.lock, flags);
uart_port_lock_irqsave(&sport->port, &flags);
if (lpuart_is_32(sport)) {
temp = lpuart32_read(&sport->port, UARTBAUD);
temp &= ~UARTBAUD_TDMAE;
@ -3137,7 +3137,7 @@ static int lpuart_suspend(struct device *dev)
temp &= ~UARTCR5_TDMAS;
writeb(temp, sport->port.membase + UARTCR5);
}
spin_unlock_irqrestore(&sport->port.lock, flags);
uart_port_unlock_irqrestore(&sport->port, flags);
sport->dma_tx_in_progress = false;
dmaengine_terminate_sync(sport->dma_tx_chan);
}

26
drivers/tty/serial/icom.c
View File

@ -929,7 +929,7 @@ static inline void check_modem_status(struct icom_port *icom_port)
char delta_status;
unsigned char status;
spin_lock(&icom_port->uart_port.lock);
uart_port_lock(&icom_port->uart_port);
/*modem input register */
status = readb(&icom_port->dram->isr);
@ -951,7 +951,7 @@ static inline void check_modem_status(struct icom_port *icom_port)
port.delta_msr_wait);
old_status = status;
}
spin_unlock(&icom_port->uart_port.lock);
uart_port_unlock(&icom_port->uart_port);
}
static void xmit_interrupt(u16 port_int_reg, struct icom_port *icom_port)
@ -1093,7 +1093,7 @@ static void process_interrupt(u16 port_int_reg,
struct icom_port *icom_port)
{
spin_lock(&icom_port->uart_port.lock);
uart_port_lock(&icom_port->uart_port);
trace(icom_port, "INTERRUPT", port_int_reg);
if (port_int_reg & (INT_XMIT_COMPLETED | INT_XMIT_DISABLED))
@ -1102,7 +1102,7 @@ static void process_interrupt(u16 port_int_reg,
if (port_int_reg & INT_RCV_COMPLETED)
recv_interrupt(port_int_reg, icom_port);
spin_unlock(&icom_port->uart_port.lock);
uart_port_unlock(&icom_port->uart_port);
}
static irqreturn_t icom_interrupt(int irq, void *dev_id)
@ -1186,14 +1186,14 @@ static unsigned int icom_tx_empty(struct uart_port *port)
int ret;
unsigned long flags;
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
if (le16_to_cpu(icom_port->statStg->xmit[0].flags) &
SA_FLAGS_READY_TO_XMIT)
ret = TIOCSER_TEMT;
else
ret = 0;
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
return ret;
}
@ -1276,7 +1276,7 @@ static void icom_send_xchar(struct uart_port *port, char ch)
/* wait .1 sec to send char */
for (index = 0; index < 10; index++) {
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
xdata = readb(&icom_port->dram->xchar);
if (xdata == 0x00) {
trace(icom_port, "QUICK_WRITE", 0);
@ -1284,10 +1284,10 @@ static void icom_send_xchar(struct uart_port *port, char ch)
/* flush write operation */
xdata = readb(&icom_port->dram->xchar);
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
break;
}
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
msleep(10);
}
}
@ -1307,7 +1307,7 @@ static void icom_break(struct uart_port *port, int break_state)
unsigned char cmdReg;
unsigned long flags;
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
trace(icom_port, "BREAK", 0);
cmdReg = readb(&icom_port->dram->CmdReg);
if (break_state == -1) {
@ -1315,7 +1315,7 @@ static void icom_break(struct uart_port *port, int break_state)
} else {
writeb(cmdReg & ~CMD_SND_BREAK, &icom_port->dram->CmdReg);
}
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
}
static int icom_open(struct uart_port *port)
@ -1365,7 +1365,7 @@ static void icom_set_termios(struct uart_port *port, struct ktermios *termios,
unsigned long offset;
unsigned long flags;
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
trace(icom_port, "CHANGE_SPEED", 0);
cflag = termios->c_cflag;
@ -1516,7 +1516,7 @@ static void icom_set_termios(struct uart_port *port, struct ktermios *termios,
trace(icom_port, "XR_ENAB", 0);
writeb(CMD_XMIT_RCV_ENABLE, &icom_port->dram->CmdReg);
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
}
static const char *icom_type(struct uart_port *port)

128
drivers/tty/serial/imx.c
View File

@ -177,8 +177,6 @@
enum imx_uart_type {
IMX1_UART,
IMX21_UART,
IMX53_UART,
IMX6Q_UART,
};
/* device type dependent stuff */
@ -240,30 +238,26 @@ struct imx_port_ucrs {
unsigned int ucr3;
};
static struct imx_uart_data imx_uart_devdata[] = {
[IMX1_UART] = {
.uts_reg = IMX1_UTS,
.devtype = IMX1_UART,
},
[IMX21_UART] = {
.uts_reg = IMX21_UTS,
.devtype = IMX21_UART,
},
[IMX53_UART] = {
.uts_reg = IMX21_UTS,
.devtype = IMX53_UART,
},
[IMX6Q_UART] = {
.uts_reg = IMX21_UTS,
.devtype = IMX6Q_UART,
},
static const struct imx_uart_data imx_uart_imx1_devdata = {
.uts_reg = IMX1_UTS,
.devtype = IMX1_UART,
};
static const struct imx_uart_data imx_uart_imx21_devdata = {
.uts_reg = IMX21_UTS,
.devtype = IMX21_UART,
};
static const struct of_device_id imx_uart_dt_ids[] = {
{ .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
{ .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], },
{ .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
{ .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
/*
* For reasons unknown to me, some UART devices (e.g. imx6ul's) are
* compatible to fsl,imx6q-uart, but not fsl,imx21-uart, while the
* original imx6q's UART is compatible to fsl,imx21-uart. This driver
* doesn't make any distinction between these two variants.
*/
{ .compatible = "fsl,imx6q-uart", .data = &imx_uart_imx21_devdata, },
{ .compatible = "fsl,imx1-uart", .data = &imx_uart_imx1_devdata, },
{ .compatible = "fsl,imx21-uart", .data = &imx_uart_imx21_devdata, },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
@ -575,7 +569,7 @@ static void imx_uart_dma_tx_callback(void *data)
unsigned long flags;
u32 ucr1;
spin_lock_irqsave(&sport->port.lock, flags);
uart_port_lock_irqsave(&sport->port, &flags);
dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
@ -600,7 +594,7 @@ static void imx_uart_dma_tx_callback(void *data)
imx_uart_writel(sport, ucr4, UCR4);
}
spin_unlock_irqrestore(&sport->port.lock, flags);
uart_port_unlock_irqrestore(&sport->port, flags);
}
/* called with port.lock taken and irqs off */
@ -766,11 +760,11 @@ static irqreturn_t imx_uart_rtsint(int irq, void *dev_id)
struct imx_port *sport = dev_id;
irqreturn_t ret;
spin_lock(&sport->port.lock);
uart_port_lock(&sport->port);
ret = __imx_uart_rtsint(irq, dev_id);
spin_unlock(&sport->port.lock);
uart_port_unlock(&sport->port);
return ret;
}
@ -779,9 +773,9 @@ static irqreturn_t imx_uart_txint(int irq, void *dev_id)
{
struct imx_port *sport = dev_id;
spin_lock(&sport->port.lock);
uart_port_lock(&sport->port);
imx_uart_transmit_buffer(sport);
spin_unlock(&sport->port.lock);
uart_port_unlock(&sport->port);
return IRQ_HANDLED;
}
@ -895,11 +889,11 @@ static irqreturn_t imx_uart_rxint(int irq, void *dev_id)
struct imx_port *sport = dev_id;
irqreturn_t ret;
spin_lock(&sport->port.lock);
uart_port_lock(&sport->port);
ret = __imx_uart_rxint(irq, dev_id);
spin_unlock(&sport->port.lock);
uart_port_unlock(&sport->port);
return ret;
}
@ -962,7 +956,7 @@ static irqreturn_t imx_uart_int(int irq, void *dev_id)
unsigned int usr1, usr2, ucr1, ucr2, ucr3, ucr4;
irqreturn_t ret = IRQ_NONE;
spin_lock(&sport->port.lock);
uart_port_lock(&sport->port);
usr1 = imx_uart_readl(sport, USR1);
usr2 = imx_uart_readl(sport, USR2);
@ -1032,7 +1026,7 @@ static irqreturn_t imx_uart_int(int irq, void *dev_id)
ret = IRQ_HANDLED;
}
spin_unlock(&sport->port.lock);
uart_port_unlock(&sport->port);
return ret;
}
@ -1115,7 +1109,7 @@ static void imx_uart_break_ctl(struct uart_port *port, int break_state)
unsigned long flags;
u32 ucr1;
spin_lock_irqsave(&sport->port.lock, flags);
uart_port_lock_irqsave(&sport->port, &flags);
ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK;
@ -1124,7 +1118,7 @@ static void imx_uart_break_ctl(struct uart_port *port, int break_state)
imx_uart_writel(sport, ucr1, UCR1);
spin_unlock_irqrestore(&sport->port.lock, flags);
uart_port_unlock_irqrestore(&sport->port, flags);
}
/*
@ -1137,9 +1131,9 @@ static void imx_uart_timeout(struct timer_list *t)
unsigned long flags;
if (sport->port.state) {
spin_lock_irqsave(&sport->port.lock, flags);
uart_port_lock_irqsave(&sport->port, &flags);
imx_uart_mctrl_check(sport);
spin_unlock_irqrestore(&sport->port.lock, flags);
uart_port_unlock_irqrestore(&sport->port, flags);
mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
}
@ -1169,9 +1163,9 @@ static void imx_uart_dma_rx_callback(void *data)
status = dmaengine_tx_status(chan, sport->rx_cookie, &state);
if (status == DMA_ERROR) {
spin_lock(&sport->port.lock);
uart_port_lock(&sport->port);
imx_uart_clear_rx_errors(sport);
spin_unlock(&sport->port.lock);
uart_port_unlock(&sport->port);
return;
}
@ -1200,9 +1194,9 @@ static void imx_uart_dma_rx_callback(void *data)
r_bytes = rx_ring->head - rx_ring->tail;
/* If we received something, check for 0xff flood */
spin_lock(&sport->port.lock);
uart_port_lock(&sport->port);
imx_uart_check_flood(sport, imx_uart_readl(sport, USR2));
spin_unlock(&sport->port.lock);
uart_port_unlock(&sport->port);
if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) {
@ -1457,10 +1451,12 @@ static int imx_uart_startup(struct uart_port *port)
imx_uart_writel(sport, ucr4 & ~UCR4_DREN, UCR4);
/* Can we enable the DMA support? */
if (!uart_console(port) && imx_uart_dma_init(sport) == 0)
if (!uart_console(port) && imx_uart_dma_init(sport) == 0) {
lockdep_set_subclass(&port->lock, 1);
dma_is_inited = 1;
}
spin_lock_irqsave(&sport->port.lock, flags);
uart_port_lock_irqsave(&sport->port, &flags);
/* Reset fifo's and state machines */
imx_uart_soft_reset(sport);
@ -1533,7 +1529,7 @@ static int imx_uart_startup(struct uart_port *port)
imx_uart_disable_loopback_rs485(sport);
spin_unlock_irqrestore(&sport->port.lock, flags);
uart_port_unlock_irqrestore(&sport->port, flags);
return 0;
}
@ -1558,21 +1554,21 @@ static void imx_uart_shutdown(struct uart_port *port)
sport->dma_is_rxing = 0;
}
spin_lock_irqsave(&sport->port.lock, flags);
uart_port_lock_irqsave(&sport->port, &flags);
imx_uart_stop_tx(port);
imx_uart_stop_rx(port);
imx_uart_disable_dma(sport);
spin_unlock_irqrestore(&sport->port.lock, flags);
uart_port_unlock_irqrestore(&sport->port, flags);
imx_uart_dma_exit(sport);
}
mctrl_gpio_disable_ms(sport->gpios);
spin_lock_irqsave(&sport->port.lock, flags);
uart_port_lock_irqsave(&sport->port, &flags);
ucr2 = imx_uart_readl(sport, UCR2);
ucr2 &= ~(UCR2_TXEN | UCR2_ATEN);
imx_uart_writel(sport, ucr2, UCR2);
spin_unlock_irqrestore(&sport->port.lock, flags);
uart_port_unlock_irqrestore(&sport->port, flags);
/*
* Stop our timer.
@ -1583,7 +1579,7 @@ static void imx_uart_shutdown(struct uart_port *port)
* Disable all interrupts, port and break condition.
*/
spin_lock_irqsave(&sport->port.lock, flags);
uart_port_lock_irqsave(&sport->port, &flags);
ucr1 = imx_uart_readl(sport, UCR1);
ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_RXDMAEN |
@ -1605,7 +1601,7 @@ static void imx_uart_shutdown(struct uart_port *port)
ucr4 &= ~UCR4_TCEN;
imx_uart_writel(sport, ucr4, UCR4);
spin_unlock_irqrestore(&sport->port.lock, flags);
uart_port_unlock_irqrestore(&sport->port, flags);
clk_disable_unprepare(sport->clk_per);
clk_disable_unprepare(sport->clk_ipg);
@ -1668,7 +1664,7 @@ imx_uart_set_termios(struct uart_port *port, struct ktermios *termios,
baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
quot = uart_get_divisor(port, baud);
spin_lock_irqsave(&sport->port.lock, flags);
uart_port_lock_irqsave(&sport->port, &flags);
/*
* Read current UCR2 and save it for future use, then clear all the bits
@ -1796,7 +1792,7 @@ imx_uart_set_termios(struct uart_port *port, struct ktermios *termios,
if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
imx_uart_enable_ms(&sport->port);
spin_unlock_irqrestore(&sport->port.lock, flags);
uart_port_unlock_irqrestore(&sport->port, flags);
}
static const char *imx_uart_type(struct uart_port *port)
@ -1858,7 +1854,7 @@ static int imx_uart_poll_init(struct uart_port *port)
imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
spin_lock_irqsave(&sport->port.lock, flags);
uart_port_lock_irqsave(&sport->port, &flags);
/*
* Be careful about the order of enabling bits here. First enable the
@ -1886,7 +1882,7 @@ static int imx_uart_poll_init(struct uart_port *port)
imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1);
imx_uart_writel(sport, ucr2 | UCR2_ATEN, UCR2);
spin_unlock_irqrestore(&sport->port.lock, flags);
uart_port_unlock_irqrestore(&sport->port, flags);
return 0;
}
@ -2005,9 +2001,9 @@ imx_uart_console_write(struct console *co, const char *s, unsigned int count)
if (sport->port.sysrq)
locked = 0;
else if (oops_in_progress)
locked = spin_trylock_irqsave(&sport->port.lock, flags);
locked = uart_port_trylock_irqsave(&sport->port, &flags);
else
spin_lock_irqsave(&sport->port.lock, flags);
uart_port_lock_irqsave(&sport->port, &flags);
/*
* First, save UCR1/2/3 and then disable interrupts
@ -2035,7 +2031,7 @@ imx_uart_console_write(struct console *co, const char *s, unsigned int count)
imx_uart_ucrs_restore(sport, &old_ucr);
if (locked)
spin_unlock_irqrestore(&sport->port.lock, flags);
uart_port_unlock_irqrestore(&sport->port, flags);
}
/*
@ -2193,10 +2189,10 @@ static enum hrtimer_restart imx_trigger_start_tx(struct hrtimer *t)
struct imx_port *sport = container_of(t, struct imx_port, trigger_start_tx);
unsigned long flags;
spin_lock_irqsave(&sport->port.lock, flags);
uart_port_lock_irqsave(&sport->port, &flags);
if (sport->tx_state == WAIT_AFTER_RTS)
imx_uart_start_tx(&sport->port);
spin_unlock_irqrestore(&sport->port.lock, flags);
uart_port_unlock_irqrestore(&sport->port, flags);
return HRTIMER_NORESTART;
}
@ -2206,10 +2202,10 @@ static enum hrtimer_restart imx_trigger_stop_tx(struct hrtimer *t)
struct imx_port *sport = container_of(t, struct imx_port, trigger_stop_tx);
unsigned long flags;
spin_lock_irqsave(&sport->port.lock, flags);
uart_port_lock_irqsave(&sport->port, &flags);
if (sport->tx_state == WAIT_AFTER_SEND)
imx_uart_stop_tx(&sport->port);
spin_unlock_irqrestore(&sport->port.lock, flags);
uart_port_unlock_irqrestore(&sport->port, flags);
return HRTIMER_NORESTART;
}
@ -2482,9 +2478,9 @@ static void imx_uart_restore_context(struct imx_port *sport)
{
unsigned long flags;
spin_lock_irqsave(&sport->port.lock, flags);
uart_port_lock_irqsave(&sport->port, &flags);
if (!sport->context_saved) {
spin_unlock_irqrestore(&sport->port.lock, flags);
uart_port_unlock_irqrestore(&sport->port, flags);
return;
}
@ -2499,7 +2495,7 @@ static void imx_uart_restore_context(struct imx_port *sport)
imx_uart_writel(sport, sport->saved_reg[2], UCR3);
imx_uart_writel(sport, sport->saved_reg[3], UCR4);
sport->context_saved = false;
spin_unlock_irqrestore(&sport->port.lock, flags);
uart_port_unlock_irqrestore(&sport->port, flags);
}
static void imx_uart_save_context(struct imx_port *sport)
@ -2507,7 +2503,7 @@ static void imx_uart_save_context(struct imx_port *sport)
unsigned long flags;
/* Save necessary regs */
spin_lock_irqsave(&sport->port.lock, flags);
uart_port_lock_irqsave(&sport->port, &flags);
sport->saved_reg[0] = imx_uart_readl(sport, UCR1);
sport->saved_reg[1] = imx_uart_readl(sport, UCR2);
sport->saved_reg[2] = imx_uart_readl(sport, UCR3);
@ -2519,7 +2515,7 @@ static void imx_uart_save_context(struct imx_port *sport)
sport->saved_reg[8] = imx_uart_readl(sport, UBMR);
sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS);
sport->context_saved = true;
spin_unlock_irqrestore(&sport->port.lock, flags);
uart_port_unlock_irqrestore(&sport->port, flags);
}
static void imx_uart_enable_wakeup(struct imx_port *sport, bool on)

36
drivers/tty/serial/ip22zilog.c
View File

@ -432,7 +432,7 @@ static irqreturn_t ip22zilog_interrupt(int irq, void *dev_id)
unsigned char r3;
bool push = false;
spin_lock(&up->port.lock);
uart_port_lock(&up->port);
r3 = read_zsreg(channel, R3);
/* Channel A */
@ -448,7 +448,7 @@ static irqreturn_t ip22zilog_interrupt(int irq, void *dev_id)
if (r3 & CHATxIP)
ip22zilog_transmit_chars(up, channel);
}
spin_unlock(&up->port.lock);
uart_port_unlock(&up->port);
if (push)
tty_flip_buffer_push(&up->port.state->port);
@ -458,7 +458,7 @@ static irqreturn_t ip22zilog_interrupt(int irq, void *dev_id)
channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
push = false;
spin_lock(&up->port.lock);
uart_port_lock(&up->port);
if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) {
writeb(RES_H_IUS, &channel->control);
ZSDELAY();
@ -471,7 +471,7 @@ static irqreturn_t ip22zilog_interrupt(int irq, void *dev_id)
if (r3 & CHBTxIP)
ip22zilog_transmit_chars(up, channel);
}
spin_unlock(&up->port.lock);
uart_port_unlock(&up->port);
if (push)
tty_flip_buffer_push(&up->port.state->port);
@ -504,11 +504,11 @@ static unsigned int ip22zilog_tx_empty(struct uart_port *port)
unsigned char status;
unsigned int ret;
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
status = ip22zilog_read_channel_status(port);
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
if (status & Tx_BUF_EMP)
ret = TIOCSER_TEMT;
@ -664,7 +664,7 @@ static void ip22zilog_break_ctl(struct uart_port *port, int break_state)
else
clear_bits |= SND_BRK;
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
new_reg = (up->curregs[R5] | set_bits) & ~clear_bits;
if (new_reg != up->curregs[R5]) {
@ -674,7 +674,7 @@ static void ip22zilog_break_ctl(struct uart_port *port, int break_state)
write_zsreg(channel, R5, up->curregs[R5]);
}
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
}
static void __ip22zilog_reset(struct uart_ip22zilog_port *up)
@ -735,9 +735,9 @@ static int ip22zilog_startup(struct uart_port *port)
if (ZS_IS_CONS(up))
return 0;
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
__ip22zilog_startup(up);
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
return 0;
}
@ -775,7 +775,7 @@ static void ip22zilog_shutdown(struct uart_port *port)
if (ZS_IS_CONS(up))
return;
spin_lock_irqsave(&port->lock, flags);
uart_port_lock_irqsave(port, &flags);
channel = ZILOG_CHANNEL_FROM_PORT(port);
@ -788,7 +788,7 @@ static void ip22zilog_shutdown(struct uart_port *port)
up->curregs[R5] &= ~SND_BRK;
ip22zilog_maybe_update_regs(up, channel);
spin_unlock_irqrestore(&port->lock, flags);
uart_port_unlock_irqrestore(port, flags);
}
/* Shared by TTY driver and serial console setup. The port lock is held
@ -880,7 +880,7 @@ ip22zilog_set_termios(struct uart_port *port, struct ktermios *termios,
baud = uart_get_baud_rate(port, termios, old, 1200, 76800);
spin_lock_irqsave(&up->port.lock, flags);
uart_port_lock_irqsave(&up->port, &flags);
brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
@ -894,7 +894,7 @@ ip22zilog_set_termios(struct uart_port *port, struct ktermios *termios,
ip22zilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(port));
uart_update_timeout(port, termios->c_cflag, baud);
spin_unlock_irqrestore(&up->port.lock, flags);
uart_port_unlock_irqrestore(&up->port, flags);
}
static const char *ip22zilog_type(struct uart_port *port)
@ -1016,10 +1016,10 @@ ip22zilog_console_write(struct console *con, const char *s, unsigned int count)
struct uart_ip22zilog_port *up = &ip22zilog_port_table[con->index];
unsigned long flags;
spin_lock_irqsave(&up->port.lock, flags);
uart_port_lock_irqsave(&up->port, &flags);
uart_console_write(&up->port, s, count, ip22zilog_put_char);
udelay(2);
spin_unlock_irqrestore(&up->port.lock, flags);
uart_port_unlock_irqrestore(&up->port, flags);
}
static int __init ip22zilog_console_setup(struct console *con, char *options)
@ -1034,13 +1034,13 @@ static int __init ip22zilog_console_setup(struct console *con, char *options)
printk(KERN_INFO "Console: ttyS%d (IP22-Zilog)\n", con->index);
spin_lock_irqsave(&up->port.lock, flags);
uart_port_lock_irqsave(&up->port, &flags);
up->curregs[R15] |= BRKIE;
__ip22zilog_startup(up);
spin_unlock_irqrestore(&up->port.lock, flags);
uart_port_unlock_irqrestore(&up->port, flags);
if (options)
uart_parse_options(options, &baud, &parity, &bits, &flow);

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