x86, mce: Rename MSR_IA32_MCx_CTL2 value
Rename CMCI_EN to MCI_CTL2_CMCI_EN and CMCI_THRESHOLD_MASK to MCI_CTL2_CMCI_THRESHOLD_MASK to make naming consistent. Signed-off-by: Huang Ying <ying.huang@intel.com> LKML-Reference: <1275977348.3444.659.camel@yhuang-dev.sh.intel.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
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@ -38,6 +38,10 @@
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#define MCM_ADDR_MEM 3 /* memory address */
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#define MCM_ADDR_GENERIC 7 /* generic */
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/* CTL2 register defines */
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#define MCI_CTL2_CMCI_EN (1ULL << 30)
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#define MCI_CTL2_CMCI_THRESHOLD_MASK 0xffffULL
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#define MCJ_CTX_MASK 3
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#define MCJ_CTX(flags) ((flags) & MCJ_CTX_MASK)
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#define MCJ_CTX_RANDOM 0 /* inject context: random */
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@ -94,9 +94,6 @@
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#define MSR_IA32_MC0_CTL2 0x00000280
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#define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x))
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#define CMCI_EN (1ULL << 30)
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#define CMCI_THRESHOLD_MASK 0xffffULL
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#define MSR_P6_PERFCTR0 0x000000c1
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#define MSR_P6_PERFCTR1 0x000000c2
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#define MSR_P6_EVNTSEL0 0x00000186
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@ -95,19 +95,19 @@ static void cmci_discover(int banks, int boot)
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rdmsrl(MSR_IA32_MCx_CTL2(i), val);
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/* Already owned by someone else? */
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if (val & CMCI_EN) {
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if (val & MCI_CTL2_CMCI_EN) {
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if (test_and_clear_bit(i, owned) && !boot)
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print_update("SHD", &hdr, i);
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__clear_bit(i, __get_cpu_var(mce_poll_banks));
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continue;
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}
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val |= CMCI_EN | CMCI_THRESHOLD;
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val |= MCI_CTL2_CMCI_EN | CMCI_THRESHOLD;
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wrmsrl(MSR_IA32_MCx_CTL2(i), val);
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rdmsrl(MSR_IA32_MCx_CTL2(i), val);
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/* Did the enable bit stick? -- the bank supports CMCI */
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if (val & CMCI_EN) {
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if (val & MCI_CTL2_CMCI_EN) {
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if (!test_and_set_bit(i, owned) && !boot)
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print_update("CMCI", &hdr, i);
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__clear_bit(i, __get_cpu_var(mce_poll_banks));
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@ -155,7 +155,7 @@ void cmci_clear(void)
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continue;
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/* Disable CMCI */
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rdmsrl(MSR_IA32_MCx_CTL2(i), val);
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val &= ~(CMCI_EN|CMCI_THRESHOLD_MASK);
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val &= ~(MCI_CTL2_CMCI_EN|MCI_CTL2_CMCI_THRESHOLD_MASK);
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wrmsrl(MSR_IA32_MCx_CTL2(i), val);
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__clear_bit(i, __get_cpu_var(mce_banks_owned));
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}
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